463 lines
24 KiB
C
463 lines
24 KiB
C
/* hp2100_defs.h: HP 2100 simulator definitions
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Copyright (c) 1993-2011, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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28-Mar-11 JDB Tidied up signal handling
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29-Oct-10 JDB DMA channels renamed from 0,1 to 1,2 to match documentation
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27-Oct-10 JDB Revised I/O signal enum values for concurrent signals
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Revised I/O macros for new signal handling
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07-Sep-08 JDB Added POLL_FIRST to indicate immediate connection attempt
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15-Jul-08 JDB Rearranged declarations with hp2100_cpu.h
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26-Jun-08 JDB Rewrote device I/O to model backplane signals
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25-Jun-08 JDB Added PIF device
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17-Jun-08 JDB Declared fmt_char() function
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26-May-08 JDB Added MPX device
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24-Apr-08 JDB Added I_MRG_I, I_JSB, I_JSB_I, and I_JMP instruction masks
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14-Apr-08 JDB Changed TMR_MUX to TMR_POLL for idle support
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Added POLLMODE, sync_poll() declaration
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Added I_MRG, I_ISZ, I_IOG, I_STF, and I_SFS instruction masks
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07-Dec-07 JDB Added BACI device
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10-Nov-07 JDB Added 16/32-bit unsigned-to-signed conversions
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11-Jan-07 JDB Added 12578A DMA byte packing to DMA structure
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28-Dec-06 JDB Added CRS backplane signal as I/O pseudo-opcode
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Added DMASK32 32-bit mask value
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21-Dec-06 JDB Changed MEM_ADDR_OK for 21xx loader support
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12-Sep-06 JDB Define NOTE_IOG to recalc interrupts after instr exec
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Rename STOP_INDINT to NOTE_INDINT (not a stop condition)
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30-Dec-04 JDB Added IBL_DS_HEAD head number mask
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19-Nov-04 JDB Added STOP_OFFLINE, STOP_PWROFF stop codes
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25-Apr-04 RMS Added additional IBL definitions
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Added DMA EDT I/O pseudo-opcode
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25-Apr-03 RMS Revised for extended file support
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24-Oct-02 RMS Added indirect address interrupt
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08-Feb-02 RMS Added DMS definitions
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01-Feb-02 RMS Added terminal multiplexor support
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16-Jan-02 RMS Added additional device support
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30-Nov-01 RMS Added extended SET/SHOW support
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15-Oct-00 RMS Added dynamic device numbers
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14-Apr-99 RMS Changed t_addr to unsigned
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The author gratefully acknowledges the help of Jeff Moffat in answering
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questions about the HP2100; and of Dave Bryan in adding features and
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correcting errors throughout the simulator.
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*/
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#ifndef _HP2100_DEFS_H_
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#define _HP2100_DEFS_H_ 0
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#include "sim_defs.h" /* simulator defns */
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/* Simulator stop and notification codes */
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#define STOP_RSRV 1 /* must be 1 */
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#define STOP_IODV 2 /* must be 2 */
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#define STOP_HALT 3 /* HALT */
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#define STOP_IBKPT 4 /* breakpoint */
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#define STOP_IND 5 /* indirect loop */
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#define NOTE_INDINT 6 /* indirect intr */
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#define STOP_NOCONN 7 /* no connection */
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#define STOP_OFFLINE 8 /* device offline */
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#define STOP_PWROFF 9 /* device powered off */
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#define NOTE_IOG 10 /* I/O instr executed */
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/* Memory */
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#define MEMSIZE (cpu_unit.capac) /* actual memory size */
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#define VA_N_SIZE 15 /* virtual addr size */
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#define VASIZE (1 << VA_N_SIZE)
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#define VAMASK 077777 /* virt addr mask */
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#define PA_N_SIZE 20 /* phys addr size */
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#define PASIZE (1 << PA_N_SIZE)
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#define PAMASK (PASIZE - 1) /* phys addr mask */
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/* Architectural constants */
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#define SIGN32 020000000000 /* 32b sign */
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#define DMASK32 037777777777 /* 32b data mask/maximum value */
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#define DMAX32 017777777777 /* 32b maximum signed value */
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#define SIGN 0100000 /* 16b sign */
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#define DMASK 0177777 /* 16b data mask/maximum value */
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#define DMAX 0077777 /* 16b maximum signed value */
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#define DMASK8 0377 /* 8b data mask/maximum value */
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/* Portable conversions (sign-extension, unsigned-to-signed) */
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#define SEXT(x) ((int32) (((x) & SIGN)? ((x) | ~DMASK): ((x) & DMASK)))
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#define INT16(u) ((u) > DMAX ? (-(int16) (DMASK - (u)) - 1) : (int16) (u))
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#define INT32(u) ((u) > DMAX32 ? (-(int32) (DMASK32 - (u)) - 1) : (int32) (u))
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/* Timers */
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#define TMR_CLK 0 /* clock */
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#define TMR_POLL 1 /* input polling */
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#define POLL_RATE 100 /* poll 100 times per second */
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#define POLL_FIRST 1 /* first poll is "immediate" */
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#define POLL_WAIT 15800 /* initial poll ~ 10 msec. */
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typedef enum { INITIAL, SERVICE } POLLMODE; /* poll synchronization modes */
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/* I/O instruction sub-opcodes */
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#define soHLT 0 /* halt */
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#define soFLG 1 /* set/clear flag */
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#define soSFC 2 /* skip on flag clear */
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#define soSFS 3 /* skip on flag set */
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#define soMIX 4 /* merge into A/B */
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#define soLIX 5 /* load into A/B */
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#define soOTX 6 /* output from A/B */
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#define soCTL 7 /* set/clear control */
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/* I/O devices - fixed select code assignments */
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#define CPU 000 /* interrupt control */
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#define OVF 001 /* overflow */
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#define DMALT1 002 /* DMA 1 alternate */
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#define DMALT2 003 /* DMA 2 alternate */
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#define PWR 004 /* power fail */
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#define PRO 005 /* parity/mem protect */
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#define DMA1 006 /* DMA channel 1 */
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#define DMA2 007 /* DMA channel 2 */
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/* I/O devices - variable select code assignment defaults */
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#define PTR 010 /* 12597A-002 paper tape reader */
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#define TTY 011 /* 12531C teleprinter */
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#define PTP 012 /* 12597A-005 paper tape punch */
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#define CLK 013 /* 12539C time-base generator */
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#define LPS 014 /* 12653A line printer */
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#define LPT 015 /* 12845A line printer */
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#define MTD 020 /* 12559A data */
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#define MTC 021 /* 12559A control */
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#define DPD 022 /* 12557A data */
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#define DPC 023 /* 12557A control */
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#define DQD 024 /* 12565A data */
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#define DQC 025 /* 12565A control */
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#define DRD 026 /* 12610A data */
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#define DRC 027 /* 12610A control */
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#define MSD 030 /* 13181A data */
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#define MSC 031 /* 13181A control */
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#define IPLI 032 /* 12566B link in */
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#define IPLO 033 /* 12566B link out */
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#define DS 034 /* 13037A control */
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#define BACI 035 /* 12966A Buffered Async Comm Interface */
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#define MPX 036 /* 12792A/B/C 8-channel multiplexer */
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#define PIF 037 /* 12620A/12936A Privileged Interrupt Fence */
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#define MUXL 040 /* 12920A lower data */
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#define MUXU 041 /* 12920A upper data */
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#define MUXC 042 /* 12920A control */
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#define OPTDEV 002 /* start of optional devices */
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#define CRSDEV 006 /* start of devices that receive CRS */
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#define VARDEV 010 /* start of variable assignments */
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#define MAXDEV 077 /* end of select code range */
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/* IBL assignments */
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#define IBL_V_SEL 14 /* ROM select */
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#define IBL_M_SEL 03
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#define IBL_PTR 0000000 /* PTR */
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#define IBL_DP 0040000 /* disk: DP */
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#define IBL_DQ 0060000 /* disk: DQ */
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#define IBL_MS 0100000 /* option 0: MS */
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#define IBL_DS 0140000 /* option 1: DS */
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#define IBL_MAN 0010000 /* RPL/man boot */
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#define IBL_V_DEV 6 /* dev in <11:6> */
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#define IBL_OPT 0000070 /* options in <5:3> */
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#define IBL_DP_REM 0000001 /* DP removable */
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#define IBL_DS_HEAD 0000003 /* DS head number */
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#define IBL_LNT 64 /* boot ROM length */
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#define IBL_MASK (IBL_LNT - 1) /* boot length mask */
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#define IBL_DPC (IBL_LNT - 2) /* DMA ctrl word */
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#define IBL_END (IBL_LNT - 1) /* last location */
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typedef uint16 BOOT_ROM [IBL_LNT]; /* boot ROM data */
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/* I/O backplane signals.
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The IOSIGNAL declarations mirror the hardware I/O backplane signals. A set
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of one or more signals forms an IOCYCLE that is sent to a device IOHANDLER
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for action. The CPU and DMA dispatch one signal set to the target device
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handler per I/O cycle. A CPU cycle consists of either one or two signals; if
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present, the second signal will be CLF. A DMA cycle consists of from two to
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five signals. In addition, a front-panel PRESET or power-on reset dispatches
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two or three signals, respectively.
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In hardware, signals are assigned to one or more specific I/O T-periods, and
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some signals are asserted concurrently. For example, a programmed STC sc,C
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instruction asserts the STC and CLF signals together in period T4. Under
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simulation, signals are ORed to form an I/O cycle; in this example, the
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signal handler would receive an IOCYCLE value of "ioSTC | ioCLF".
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Hardware allows parallel action for concurrent signals. Under simulation, a
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"concurrent" set of signals is processed sequentially by the signal handler
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in order of ascending numerical value. Although assigned T-periods differ
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between programmed I/O and DMA I/O cycles, a single processing order is used.
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The order of execution generally follows the order of T-period assertion,
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except that ioSIR is processed after all other signals that may affect the
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interrupt request chain.
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Implementation notes:
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1. The ioCLF signal must be processed after ioSFS/ioSFC to ensure that a
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true skip test generates ioSKF before the flag is cleared, and after
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ioIOI/ioIOO/ioSTC/ioCLC to meet the requirement that executing an
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instruction having the H/C bit set is equivalent to executing the same
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instruction with the H/C bit clear and then a CLF instruction.
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2. The ioSKF signal is never sent to an I/O handler. Rather, it is returned
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from the handler if the SFC or SFS condition is true. If the condition
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is false, ioNONE is returned instead. As these two values are returned
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in the 16-bit data portion of the returned value, their assigned values
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must be <= 100000 octal.
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3. An I/O handler will receive ioCRS as a result of a CLC 0 instruction,
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ioPOPIO and ioCRS as a result of a RESET command, and ioPON, ioPOPIO, and
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ioCRS as a result of a RESET -P command.
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4. An I/O handler will receive ioNONE when a HLT instruction is executed
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that has the H/C bit clear (i.e., no CLF generated).
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5. In hardware, the SIR signal is generated unconditionally every T5 period
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to time the setting of the IRQ flip-flop. Under simulation, ioSIR
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indicates that the I/O handler must set the PRL, IRQ, and SRQ signals as
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required by the interface logic. ioSIR must be included in the I/O cycle
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if any of the flip-flops affecting these signals are changed and the
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interface supports interrupts or DMA transfers.
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6. In hardware, the ENF signal is unconditionally generated every T2 period
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to time the setting of the flag flip-flop and to reset the IRQ flip-flop.
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If the flag buffer flip-flip is set, then flag will be set by ENF. If
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the flag buffer is clear, ENF will not affect flag. Under simulation,
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ioENF is sent to set the flag buffer and flag flip-flops. For those
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interfaces where this action is identical to that provided by STF, the
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ioENF handler may simply fall into the ioSTF handler.
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7. In hardware, the PON signal is asserted continuously while the CPU is
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operating. Under simulation, ioPON is asserted only at simulator
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initialization or when processing a RESET -P command.
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*/
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typedef enum { ioNONE = 0000000, /* -- -- -- -- -- no signal asserted */
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ioPON = 0000001, /* T2 T3 T4 T5 T6 power on normal */
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ioENF = 0000002, /* T2 -- -- -- -- enable flag */
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ioIOI = 0000004, /* -- -- T4 T5 -- I/O data input (CPU)
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T2 T3 -- -- -- I/O data input (DMA) */
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ioIOO = 0000010, /* -- T3 T4 -- -- I/O data output */
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ioSKF = 0000020, /* -- T3 T4 T5 -- skip on flag */
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ioSFS = 0000040, /* -- T3 T4 T5 -- skip if flag is set */
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ioSFC = 0000100, /* -- T3 T4 T5 -- skip if flag is clear */
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ioSTC = 0000200, /* -- -- T4 -- -- set control flip-flop (CPU)
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-- T3 -- -- -- set control flip-flop (DMA) */
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ioCLC = 0000400, /* -- -- T4 -- -- clear control flip-flop (CPU)
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-- T3 T4 -- -- clear control flip-flop (DMA) */
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ioSTF = 0001000, /* -- T3 -- -- -- set flag flip-flop */
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ioCLF = 0002000, /* -- -- T4 -- -- clear flag flip-flop (CPU)
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-- T3 -- -- -- clear flag flip-flop (DMA) */
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ioEDT = 0004000, /* -- -- T4 -- -- end data transfer */
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ioCRS = 0010000, /* -- -- -- T5 -- control reset */
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ioPOPIO = 0020000, /* -- -- -- T5 -- power-on preset to I/O */
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ioIAK = 0040000, /* -- -- -- -- T6 interrupt acknowledge */
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ioSIR = 0100000 } IOSIGNAL; /* -- -- -- T5 -- set interrupt request */
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typedef uint32 IOCYCLE; /* a set of signals forming one I/O cycle */
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#define IOIRQSET (ioSTC | ioCLC | ioENF | \
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ioSTF | ioCLF | ioIAK | \
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ioCRS | ioPOPIO | ioPON) /* signals that may affect interrupt state */
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/* I/O structures */
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typedef enum { CLEAR, SET } FLIP_FLOP; /* flip-flop type and values */
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typedef struct dib DIB; /* incomplete definition */
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typedef uint32 IOHANDLER (DIB *dibptr, /* I/O signal handler prototype */
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IOCYCLE signal_set,
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uint32 stat_data);
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struct dib { /* Device information block */
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IOHANDLER *io_handler; /* pointer to device's I/O signal handler */
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uint32 select_code; /* device's select code */
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uint32 card_index; /* device's card index for state variables */
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};
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/* I/O signal and status macros.
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The following macros are useful in I/O signal handlers and unit service
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routines. The parameter definition symbols employed are:
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I = an IOCYCLE value
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E = a t_stat error status value
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D = a uint16 data value
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C = a uint32 combined status and data value
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P = a pointer to a DIB structure
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B = a Boolean test value
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Implementation notes:
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1. The IONEXT macro isolates the next signal in sequence to process from the
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I/O cycle I.
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2. The IOADDSIR macro adds an ioSIR signal to the I/O cycle I if it
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contains signals that might change the interrupt state.
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3. The IORETURN macro forms the combined status and data value to be
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returned by a handler from the t_stat error code E and the 16-bit data
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value D.
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4. The IOSTATUS macro isolates the t_stat error code from a combined status
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and data value value C.
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5. The IODATA macro isolates the 16-bit data value from a combined status
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and data value value C.
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6. The IOPOWERON macro calls signal handler P->H with DIB pointer P to
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process a power-on reset action.
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7. The IOPRESET macro calls signal handler P->H with DIB pointer P to
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process a front-panel PRESET action.
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8. The IOERROR macro returns t_stat error code E from a unit service routine
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if the Boolean test B is true.
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*/
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#define IONEXT(I) (IOSIGNAL) ((I) & (IOCYCLE) (- (int32) (I))) /* extract next I/O signal to handle */
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#define IOADDSIR(I) ((I) & IOIRQSET ? (I) | ioSIR : (I)) /* add SIR if IRQ state might change */
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#define IORETURN(E,D) ((uint32) ((E) << 16 | (D) & DMASK)) /* form I/O handler return value */
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#define IOSTATUS(C) ((t_stat) ((C) >> 16) & DMASK) /* extract I/O status from combined value */
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#define IODATA(C) ((uint16) ((C) & DMASK)) /* extract data from combined value */
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#define IOPOWERON(P) (P)->io_handler ((P), ioPON | ioPOPIO | ioCRS, 0) /* send power-on signals to handler */
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#define IOPRESET(P) (P)->io_handler ((P), ioPOPIO | ioCRS, 0) /* send PRESET signals to handler */
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#define IOERROR(B,E) ((B) ? (E) : SCPE_OK) /* stop on I/O error if enabled */
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/* I/O signal logic macros.
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The following macros implement the logic for the SKF, PRL, IRQ, and SRQ
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signals. Both standard and general logic macros are provided. The parameter
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definition symbols employed are:
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S = a uint32 select code value
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B = a Boolean test value
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N = a name of a structure containing the standard flip-flops
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Implementation notes:
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1. The setSKF macro sets the Skip on Flag signal in the return data value if
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the Boolean value B is true.
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2. The setPRL macro sets the Priority Low signal for select code S to the
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Boolean value B.
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3. The setIRQ macro sets the Interrupt Request signal for select code S to
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the Boolean value B.
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4. The setSRQ macro sets the Service Request signal for select code S to the
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Boolean value B.
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5. The PRL macro returns the Priority Low signal for select code S as a
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Boolean value.
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6. The IRQ macro returns the Interrupt Request signal for select code S as a
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Boolean value.
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7. The SRQ macro returns the Service Request signal for select code S as a
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Boolean value.
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8. The setstdSKF macro sets Skip on Flag signal in the return data value if
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the flag state in structure N matches the current skip test condition.
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9. The setstdPRL macro sets the Priority Low signal for the select code
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referenced by "dibptr" using the standard logic and the control and flag
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states in structure N.
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10. The setstdIRQ macro sets the Interrupt Request signal for the select code
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referenced by "dibptr" using the standard logic and the control, flag,
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and flag buffer states in structure N.
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11. The setstdSRQ macro sets the Service Request signal for the select code
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referenced by "dibptr" using the standard logic and the flag state in
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structure N.
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*/
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#define BIT_V(S) ((S) & 037) /* convert select code to bit position */
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#define BIT_M(S) (1u << BIT_V (S)) /* convert select code to bit mask */
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#define setSKF(B) stat_data = IORETURN (SCPE_OK, (uint16) ((B) ? ioSKF : ioNONE))
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#define setPRL(S,B) dev_prl[(S)/32] = dev_prl[(S)/32] & ~BIT_M (S) | (((B) & 1) << BIT_V (S))
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#define setIRQ(S,B) dev_irq[(S)/32] = dev_irq[(S)/32] & ~BIT_M (S) | (((B) & 1) << BIT_V (S))
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#define setSRQ(S,B) dev_srq[(S)/32] = dev_srq[(S)/32] & ~BIT_M (S) | (((B) & 1) << BIT_V (S))
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#define PRL(S) ((dev_prl[(S)/32] >> BIT_V (S)) & 1)
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#define IRQ(S) ((dev_irq[(S)/32] >> BIT_V (S)) & 1)
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#define SRQ(S) ((dev_srq[(S)/32] >> BIT_V (S)) & 1)
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#define setstdSKF(N) setSKF ((signal == ioSFC) && !N.flag || \
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(signal == ioSFS) && N.flag)
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#define setstdPRL(N) setPRL (dibptr->select_code, !(N.control & N.flag));
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#define setstdIRQ(N) setIRQ (dibptr->select_code, N.control & N.flag & N.flagbuf);
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#define setstdSRQ(N) setSRQ (dibptr->select_code, N.flag);
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/* CPU state */
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extern uint32 SR; /* S register (for IBL) */
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extern uint32 dev_prl [2], dev_irq [2], dev_srq [2]; /* I/O signal vectors */
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/* Simulator state */
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extern FILE *sim_deb;
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extern FILE *sim_log;
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extern int32 sim_step;
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extern int32 sim_switches;
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/* CPU functions */
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extern t_stat ibl_copy (const BOOT_ROM rom, int32 dev);
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extern void hp_enbdis_pair (DEVICE *ccp, DEVICE *dcp);
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/* System functions */
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extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val, UNIT *uptr, int32 sw);
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extern const char *fmt_char (uint8 ch);
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extern t_stat hp_setdev (UNIT *uptr, int32 val, char *cptr, void *desc);
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extern t_stat hp_showdev (FILE *st, UNIT *uptr, int32 val, void *desc);
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/* Standard device functions */
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extern int32 sync_poll (POLLMODE poll_mode);
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#endif
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