136 lines
3.9 KiB
C
136 lines
3.9 KiB
C
/* i7094_clk.c: IBM 7094 clock
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Copyright (c) 2003-2011, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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clk RPQ F89349 interval timer
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Chronolog calendar clock
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25-Mar-11 RMS According to RPQ, clock clears on RESET
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*/
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#include "i7094_defs.h"
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#include <time.h>
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uint32 chtr_clk = 0;
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extern t_uint64 *M;
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t_stat clk_svc (UNIT *uptr);
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t_stat clk_reset (DEVICE *dptr);
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uint8 bcd_2d (uint32 n, uint8 *b2);
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/* CLK data structures
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clk_dev CLK device descriptor
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clk_unit CLK unit
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clk_reg CLK register list
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*/
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UNIT clk_unit = { UDATA (&clk_svc, 0, 0), 16000 };
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REG clk_reg[] = {
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{ FLDATA (TRAP, chtr_clk, 0) },
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{ DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },
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{ NULL }
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};
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DEVICE clk_dev = {
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"CLK", &clk_unit, clk_reg, NULL,
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1, 0, 0, 0, 0, 0,
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NULL, NULL, &clk_reset,
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NULL, NULL, NULL,
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NULL, DEV_DISABLE+DEV_DIS
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};
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/* Clock unit service */
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t_stat clk_svc (UNIT *uptr)
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{
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t_uint64 ctr;
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if ((clk_dev.flags & DEV_DIS) == 0) { /* clock enabled? */
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ctr = ReadP (CLK_CTR);
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ctr = (ctr + 1) & MMASK; /* increment */
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WriteP (CLK_CTR, ctr);
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if (ctr == 0) /* overflow? req trap */
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chtr_clk = 1;
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sim_activate (uptr, sim_rtcn_calb (CLK_TPS, TMR_CLK)); /* reactivate unit */
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}
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return SCPE_OK;
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}
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/* Chronolog clock */
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uint32 chrono_rd (uint8 *buf, uint32 bufsiz)
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{
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time_t curtim;
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t_uint64 ctr;
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struct tm *tptr;
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if (bufsiz < 12)
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return 0;
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curtim = time (NULL); /* get time */
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tptr = localtime (&curtim); /* decompose */
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if (tptr == NULL) /* error? */
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return 0;
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buf[0] = bcd_2d (tptr->tm_mon + 1, buf + 1);
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buf[2] = bcd_2d (tptr->tm_mday, buf + 3);
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buf[4] = bcd_2d (tptr->tm_hour, buf + 5);
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buf[6] = bcd_2d (tptr->tm_min, buf + 7);
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buf[8] = bcd_2d (tptr->tm_sec, buf + 9);
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ctr = ReadP (CLK_CTR);
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buf[10] = bcd_2d ((uint32) (ctr % 60), buf + 11);
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return 12;
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}
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/* Convert number (0-99) to BCD */
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uint8 bcd_2d (uint32 n, uint8 *b2)
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{
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uint8 d1, d2;
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d1 = n / 10;
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d2 = n % 10;
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if (d1 == 0)
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d1 = BCD_ZERO;
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if (d2 == 0)
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d2 = BCD_ZERO;
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if (b2 != NULL)
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*b2 = d2;
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return d1;
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}
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/* Reset routine */
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t_stat clk_reset (DEVICE *dptr)
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{
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chtr_clk = 0;
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if (clk_dev.flags & DEV_DIS)
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sim_cancel (&clk_unit);
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else {
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sim_activate (&clk_unit, sim_rtcn_init (clk_unit.wait, TMR_CLK));
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WriteP (CLK_CTR, 0);
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}
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return SCPE_OK;
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}
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