ASH/ASHC fix (another)
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1095e4823b
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ac96e9afe5
1 changed files with 7 additions and 7 deletions
12
cpu.cpp
12
cpu.cpp
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@ -521,9 +521,9 @@ bool cpu::additional_double_operand_instructions(const uint16_t instr)
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else {
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else {
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// extend sign-bit
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// extend sign-bit
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if (R & 0x8000) // convert to unsigned 32b int & extend sign
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if (R & 0x8000) // convert to unsigned 32b int & extend sign
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R = (uint32_t(R) | 0xffff0000) >> (64 - (shift - 1));
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R = (uint32_t(R) | 0xffff0000) >> (64 - (shift + 1));
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else
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else
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R >>= 64 - (shift - 1);
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R >>= 64 - (shift + 1);
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setPSW_c(R & 1);
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setPSW_c(R & 1);
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R >>= 1;
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R >>= 1;
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@ -556,17 +556,17 @@ bool cpu::additional_double_operand_instructions(const uint16_t instr)
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else {
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else {
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// extend sign-bit
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// extend sign-bit
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if (R0R1 & 0x80000000) // convert to unsigned 64b int & extend sign
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if (R0R1 & 0x80000000) // convert to unsigned 64b int & extend sign
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R0R1 = (uint64_t(R0R1) | 0xffffffff00000000ll) >> (64 - (shift - 1));
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R0R1 = (uint64_t(R0R1) | 0xffffffff00000000ll) >> (64 - (shift + 1));
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else
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else
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R0R1 >>= 64 - (shift - 1);
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R0R1 >>= 64 - (shift + 1);
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setPSW_c(R0R1 & 1);
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setPSW_c(R0R1 & 1);
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R0R1 >>= 1;
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R0R1 >>= 1;
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}
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}
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setRegister(reg, R0R1 & 65535);
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setRegister(reg, R0R1 >> 16);
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setRegister(reg + 1, R0R1 >> 16);
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setRegister(reg + 1, R0R1 & 65535);
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setPSW_n(R0R1 >> 31);
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setPSW_n(R0R1 >> 31);
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setPSW_z(R0R1 == 0);
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setPSW_z(R0R1 == 0);
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