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PSW bit masking for RTI/RTT

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Folkert van Heusden 2025-04-05 15:35:07 +02:00
parent 9bb0dc305c
commit c749db63e8
Signed by untrusted user who does not match committer: folkert
GPG key ID: 6B6455EDFEED3BD1
1 changed files with 4 additions and 8 deletions
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12
cpu.cpp
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@ -316,14 +316,10 @@ int cpu::getPSW_spl() const
void cpu::setPSW(const uint16_t v, const bool limited) void cpu::setPSW(const uint16_t v, const bool limited)
{ {
if (limited) { if (limited)
// cannot replace the run-mode bits nor the set of registers psw = (psw & 0174340) | (v & 037);
// psw = (psw & ~0340) | (v & 0174340); else
psw = (psw & 0177400) | (v & 037777); psw = v & 0174377; // mask off reserved bits
}
else {
psw = v;
}
} }
void cpu::setPSW_flags_nzv(const uint16_t value, const word_mode_t word_mode) void cpu::setPSW_flags_nzv(const uint16_t value, const word_mode_t word_mode)