folkert/python-pdp1170
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Squeeze another 1% out of reg-reg mov

Browse source
This commit is contained in:
Neil Webber 2024-05-17 11:26:12 -05:00
parent 0a5b2b8a69
commit 156972e88f
1 changed files with 16 additions and 13 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

29
op4.py
View file

@ -67,20 +67,22 @@ def op01_mov(cpu, inst):
# avoid call to the more-general operandx for mode 0, direct register. # avoid call to the more-general operandx for mode 0, direct register.
# This optimization is a substantial speed up for register MOVs. # This optimization is a substantial speed up for register MOVs.
if (inst & 0o7000) == 0: srcb6 = (inst & 0o7700) >> 6
val = cpu.r[(inst & 0o700) >> 6] if srcb6 < 8:
val = cpu.r[srcb6]
else: else:
val = cpu.operandx((inst & 0o7700) >> 6) val = cpu.operandx(srcb6)
cpu.psw_v = 0 # per manual; V is cleared cpu.psw_v = 0 # per manual; V is cleared
cpu.psw_z = (val == 0) cpu.psw_z = (val == 0)
cpu.psw_n = (val > 32767) cpu.psw_n = (val > 32767)
# same optimization on the write side. # same optimization on the write side.
if (inst & 0o70) == 0: dstb6 = (inst & 0o77)
cpu.r[(inst & 0o07)] = val if dstb6 < 8:
cpu.r[dstb6] = val
else: else:
cpu.operandx(inst & 0o0077, val) cpu.operandx(dstb6, val)
# This is ALWAYS an 8-bit MOVB # This is ALWAYS an 8-bit MOVB
@ -89,10 +91,11 @@ def op11_movb(cpu, inst):
# avoid call to the more-general operandx for mode 0, direct register. # avoid call to the more-general operandx for mode 0, direct register.
# This optimization is a substantial speed up for register MOVs. # This optimization is a substantial speed up for register MOVs.
if (inst & 0o7000) == 0: srcb6 = (inst & 0o7700) >> 6
val = cpu.r[(inst & 0o700) >> 6] & 0o377 if srcb6 < 8:
val = cpu.r[srcb6] & 0o377
else: else:
val = cpu.operandx((inst & 0o7700) >> 6, opsize=1) val = cpu.operandx(srcb6, opsize=1)
cpu.psw_v = 0 cpu.psw_v = 0
cpu.psw_z = (val == 0) cpu.psw_z = (val == 0)
@ -101,13 +104,13 @@ def op11_movb(cpu, inst):
# avoid call to the more-general operandx for mode 0, direct register # avoid call to the more-general operandx for mode 0, direct register
# not only as an optimization, but because unlike other byte operations # not only as an optimization, but because unlike other byte operations
# in register-direct mode, MOVB does a sign-extend. # in register-direct mode, MOVB does a sign-extend.
dst = inst & 0o0077 dstb6 = inst & 0o0077
if (dst < 8): # i.e., mode 0 if (dstb6 < 8): # i.e., mode 0
if val > 127: if val > 127:
val |= 0o177400 val |= 0o177400
cpu.r[dst] = val cpu.r[dstb6] = val
else: else:
cpu.operandx(dst, val, opsize=1) cpu.operandx(dstb6, val, opsize=1)
def op02_cmp(cpu, inst, opsize=2): def op02_cmp(cpu, inst, opsize=2):