Fixed interrupt logic causing OS device timeouts when I/O was happening to multiple drives simultaneously (from Bob Supnik)
This commit is contained in:
Mark Pizzolato
parent
e0bb8fed91
commit
0290b4bee4
1 changed files with 287 additions and 38 deletions
325
PDP11/pdp11_hk.c
325
PDP11/pdp11_hk.c
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@ -25,6 +25,7 @@
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hk RK611/RK06/RK07 disk
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10-Dec-12 RMS Fixed interrupt logic
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19-Mar-12 RMS Fixed declaration of cpu_opt (Mark Pizzolato)
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29-Apr-07 RMS NOP and DCLR (at least) do not check drive type
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MR2 and MR3 only updated on NOP
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@ -136,12 +137,44 @@ extern uint16 *M;
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#define GET_UAE(x) (((x) >> CS1_V_UAE) & CS1_M_UAE)
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#define PUT_UAE(x,n) (((x) & ~ CS1_UAE) | (((n) << CS1_V_UAE) & CS1_UAE))
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char *hk_funcs[] = {
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"NOP", "PACK", "DCLR", "UNLOAD", "START", "RECAL", "OFFSET", "SEEK",
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"READ", "WRITE", "READH", "WRITEH", "WCHK"};
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BITFIELD hk_cs1_bits[] = {
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BIT(GO), /* go */
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BITFNAM(FNC,4,hk_funcs), /* function */
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BIT(SPARE), /* Spare Bit */
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BIT(IE), /* Interrupt Enable */
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BIT(RDY), /* Controller Ready */
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BIT(BA16), /* Unibus addr ext bit 16 */
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BIT(BA17), /* Unibus addr ext bit 17 */
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BIT(DT), /* Controller Drive Type */
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BIT(CTO), /* Controller Timeout */
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BIT(CFMT), /* Controller Format */
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BIT(DTCPAR), /* Drive-To-Controller Parity Error */
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BIT(DI), /* Drive Interrupt */
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BIT(ERR), /* error */
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ENDBITS
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};
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/* HKWC - 177442 - word count */
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BITFIELD hk_wc_bits[] = {
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BITF(WC,16), /* Word Count */
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ENDBITS
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};
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/* HKBA - 177444 - base address */
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#define BA_MBZ 0000001 /* must be zero */
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BITFIELD hk_ba_bits[] = {
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BITF(BA,16), /* Bus Address */
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ENDBITS
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};
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/* HKDA - 177446 - sector/track */
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#define DA_V_SC 0 /* sector pos */
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@ -152,6 +185,14 @@ extern uint16 *M;
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#define GET_SC(x) (((x) >> DA_V_SC) & DA_M_SC)
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#define GET_SF(x) (((x) >> DA_V_SF) & DA_M_SF)
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BITFIELD hk_da_bits[] = {
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BITF(SA,5), /* Sector */
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BITNCF(3), /* 05:07 Zero */
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BITF(TA,3), /* Track */
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BITNCF(5), /* 11:15 Zero */
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ENDBITS
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};
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/* HKCS2 - 177450 - control/status 2 */
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#define CS2_V_UNIT 0 /* unit pos */
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@ -176,6 +217,25 @@ extern uint16 *M;
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CS2_NED | CS2_PE | CS2_WCE | CS2_DLT )
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#define GET_UNIT(x) (((x) >> CS2_V_UNIT) & CS2_M_UNIT)
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BITFIELD hk_cs2_bits[] = {
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BITF(DS,3), /* Drive Select */
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BIT(RLS), /* Release */
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BIT(BAI), /* Bus Address Increment Inhibit */
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BIT(SCLR), /* Subsystem Clear */
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BIT(IR), /* Input Ready */
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BIT(OR), /* Output Ready */
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BIT(UFE), /* Unit Field Error */
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BIT(MDS), /* Multiple Drive Select */
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BIT(PGE), /* Programming Error */
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BIT(NEM), /* Nonexistant Memory */
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BIT(NED), /* Nonexistant Drive */
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BIT(UPE), /* Unibus Parity Error */
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BIT(WCE), /* Write Check Error */
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BIT(DLT), /* Data Late Error */
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ENDBITS
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};
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/* HKDS - 177452 - drive status ^ = calculated dynamically */
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#define DS_DRA 0000001 /* ^drive avail */
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@ -192,6 +252,25 @@ extern uint16 *M;
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#define DS_VLD 0100000 /* ^status valid */
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#define DS_MBZ 0013002
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BITFIELD hk_ds_bits[] = {
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BIT(DRA), /* Drive Available */
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BITNCF(1), /* 01 Spare */
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BIT(OFST), /* Offset */
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BIT(ACLO), /* Drive AC Low */
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BIT(SPLS), /* Speed Loss */
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BIT(DROT), /* Drive Off Track */
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BIT(VV), /* Volume Valid */
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BIT(DRDY), /* Drive Ready */
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BIT(DDT), /* Disk Drive Type */
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BITNCF(2), /* 09:10 Spare */
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BIT(WRL), /* Write Lock */
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BITNCF(1), /* 12 Spare */
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BIT(PIP), /* Positioning in Progress */
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BIT(ATA), /* Current Drive Attention */
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BIT(SVAL), /* Status Valid */
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ENDBITS
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};
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/* HKER - 177454 - error status */
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#define ER_ILF 0000001 /* illegal func */
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@ -211,11 +290,44 @@ extern uint16 *M;
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#define ER_UNS 0040000 /* drive unsafe */
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#define ER_DCK 0100000 /* data check NI */
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BITFIELD hk_er_bits[] = {
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BIT(ILF), /* Illegal Function */
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BIT(SKI), /* Seek Incomplete */
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BIT(NXF), /* Nonexecutable Function */
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BIT(DROAR), /* Control-to-Drive Parity Error */
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BIT(FMTE), /* Format Error */
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BIT(DTYE), /* Drive Type Error */
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BIT(ECH), /* Error Correction Hard */
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BIT(BSE), /* Bad Sector Error */
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BIT(HRVC), /* Header Virtical Redundancy */
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BIT(COE), /* Cylinder Overflow Error */
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BIT(IDAE), /* Invalid Disk Address Error */
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BIT(WLE), /* Write Lock Error */
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BIT(DTE), /* Drive Timing Error */
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BIT(OPI), /* Operation Incomplete */
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BIT(UNS), /* Drive Unsafe */
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BIT(DCK), /* Data Check */
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ENDBITS
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};
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/* HKAS - 177456 - attention summary/offset */
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#define AS_U0 0000400 /* unit 0 flag */
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#define AS_OF 0000277 /* offset mask */
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BITFIELD hk_as_bits[] = {
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BITF(OF,8), /* Offset */
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BIT(ATN0), /* Attention Drive 0 */
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BIT(ATN1), /* Attention Drive 1 */
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BIT(ATN2), /* Attention Drive 2 */
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BIT(ATN3), /* Attention Drive 3 */
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BIT(ATN4), /* Attention Drive 4 */
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BIT(ATN5), /* Attention Drive 5 */
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BIT(ATN6), /* Attention Drive 6 */
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BIT(ATN7), /* Attention Drive 7 */
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ENDBITS
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};
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/* HKDC - 177460 - desired cylinder */
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#define DC_V_CY 0 /* cylinder pos */
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@ -225,6 +337,12 @@ extern uint16 *M;
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#define GET_DA(c,fs) ((((GET_CY (c) * HK_NUMSF) + \
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GET_SF (fs)) * HK_NUMSC) + GET_SC (fs))
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BITFIELD hk_dc_bits[] = {
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BITF(DC,10), /* Desired Cylinder */
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BITNCF(6), /* 10:15 Spare */
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ENDBITS
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};
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/* Spare - 177462 - read/write */
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#define XM_KMASK 0177700 /* Qbus XM key mask */
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@ -234,6 +352,11 @@ extern uint16 *M;
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/* HKDB - 177464 - read/write */
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BITFIELD hk_db_bits[] = {
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BITF(DB,16), /* Data Buffer Register */
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ENDBITS
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};
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/* HKMR - 177466 - maintenance register 1 */
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#define MR_V_MS 0 /* message select */
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@ -244,9 +367,37 @@ extern uint16 *M;
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#define MR_DMD 0000040 /* diagnostic mode */
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#define MR_RW 0001777
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BITFIELD hk_mr_bits[] = {
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BITF(MS,4), /* Message Select */
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BIT(PAT), /* Parity Test */
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BIT(DMD), /* Diagnostic Mode */
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BIT(MSP), /* Maintenance Selector Pulse */
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BIT(MIND), /* Maintenance Index */
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BIT(MCLK), /* Maintenance Clock */
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BIT(MERD), /* Maintenance Encoded Read Data */
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BIT(MEWD), /* Maintenance Encoded Write Data */
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BIT(PCA), /* Precompensation Advance */
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BIT(PCD), /* Precompensation Delay */
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BIT(ECCW), /* ECC Word */
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BIT(WRTGT), /* Write Gate */
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BIT(RDGT), /* Read Gate */
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ENDBITS
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};
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/* HKEC1 - 177470 - ECC status 1 - always reads as 0 */
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BITFIELD hk_ec1_bits[] = {
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BITF(EC1,16), /* ECC status 1 */
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ENDBITS
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};
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/* HKEC2 - 177472 - ECC status 2 - always reads as 0 */
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BITFIELD hk_ec2_bits[] = {
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BITF(EC2,16), /* ECC status 2 */
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ENDBITS
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};
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/* HKMR2 - 177474 - maintenance register 2 */
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#define AX_V_UNIT 0 /* unit #, all msgs */
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@ -280,6 +431,11 @@ extern uint16 *M;
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#define A3_V_SNO 3 /* serial # */
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BITFIELD hk_mr2_bits[] = {
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BITF(MR2,16), /* Maintenance Register 2 */
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ENDBITS
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};
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/* HKMR3 - 177476 - maintenance register 3 */
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#define B0_IAE 0000040 /* invalid addr */
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@ -317,14 +473,58 @@ extern uint16 *M;
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#define RDH2_V_DHA 5 /* decoded head */
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#define RDH2_GOOD 0140000 /* good sector flags */
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BITFIELD hk_mr3_bits[] = {
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BITF(MR3,16), /* Maintenance Register 3 */
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ENDBITS
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};
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char *hk_regnames[] = {
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"HKCS1",
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"HKWC",
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"HKBA",
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"HKDA",
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"HKCS2",
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"HKDS",
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"HKER",
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"HKAS",
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"HKDC",
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"spare",
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"HKDB",
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"HKMR",
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"HKEC1",
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"HKEC2",
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"HKMR2",
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"HKMR3"
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};
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BITFIELD *hk_reg_bits[] = {
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hk_cs1_bits,
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hk_wc_bits,
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hk_ba_bits,
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hk_da_bits,
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hk_cs2_bits,
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hk_ds_bits,
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hk_er_bits,
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hk_as_bits,
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hk_dc_bits,
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NULL,
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hk_db_bits,
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hk_mr_bits,
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hk_ec1_bits,
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hk_ec2_bits,
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hk_mr2_bits,
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hk_mr3_bits,
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};
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/* Debug detail levels */
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#define HKDEB_OPS 001 /* transactions */
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#define HKDEB_RRD 002 /* reg reads */
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#define HKDEB_RWR 004 /* reg writes */
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#define HKDEB_TRC 010 /* trace */
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#define HKDEB_INT 020 /* interrupts */
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extern int32 int_req[IPL_HLVL];
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extern FILE *sim_deb;
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uint16 *hkxb = NULL; /* xfer buffer */
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int32 hkcs1 = 0; /* control/status 1 */
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@ -464,6 +664,8 @@ DEBTAB hk_deb[] = {
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{ "OPS", HKDEB_OPS },
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{ "RRD", HKDEB_RRD },
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{ "RWR", HKDEB_RWR },
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{ "INTERRUPT", HKDEB_INT },
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{ "TRACE", HKDEB_TRC },
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{ NULL, 0 }
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};
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@ -563,14 +765,14 @@ switch (j) { /* decode PA<4:1> */
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break;
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}
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if (DEBUG_PRI (hk_dev, HKDEB_RRD))
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fprintf (sim_deb, ">>HK%d read: reg%d=%o\n", drv, j, *data);
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sim_debug (HKDEB_RRD, &hk_dev, ">>HK%d read: %s=0%o\n", drv, hk_regnames[j], *data);
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sim_debug_bits (HKDEB_RRD, &hk_dev, hk_reg_bits[j], *data, *data, 1);
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return SCPE_OK;
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}
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t_stat hk_wr (int32 data, int32 PA, int32 access)
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{
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int32 drv, i, j;
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int32 drv, i, j, old_val, new_val;
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UNIT *uptr;
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drv = GET_UNIT (hkcs2); /* get current unit */
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@ -584,11 +786,11 @@ if ((hkcs1 & CS1_GO) && /* busy? */
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return SCPE_OK;
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}
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if (DEBUG_PRI (hk_dev, HKDEB_RWR))
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fprintf (sim_deb, ">>HK%d write: reg%d=%o\n", drv, j, data);
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sim_debug (HKDEB_RWR, &hk_dev, ">>HK%d write: %s=0%o\n", drv, hk_regnames[j], data);
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switch (j) { /* decode PA<4:1> */
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case 000: /* HKCS1 */
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old_val = hkcs1;
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if (data & CS1_CCLR) { /* controller reset? */
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hkcs1 = CS1_DONE; /* CS1 = done */
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hkcs2 = CS2_IR; /* CS2 = ready */
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@ -599,68 +801,98 @@ switch (j) { /* decode PA<4:1> */
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CLR_INT (HK); /* clr int */
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for (i = 0; i < HK_NUMDR; i++) { /* stop data xfr */
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if (sim_is_active (&hk_unit[i]) &&
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((uptr->FNC & CS1_M_FNC) >= FNC_XFER))
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((hk_unit[i].FNC & CS1_M_FNC) >= FNC_XFER))
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sim_cancel (&hk_unit[i]);
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}
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drv = 0;
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break;
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}
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if (data & CS1_IE) { /* setting IE? */
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if (data & CS1_DONE) /* write to DONE+IE? */
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if (data & CS1_DONE) { /* write to DONE+IE? */
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sim_debug (HKDEB_INT, &hk_dev, "hk_wr(SET_INT)\n");
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SET_INT (HK);
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}
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}
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else {
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sim_debug (HKDEB_INT, &hk_dev, "hk_wr(CLR_INT)\n");
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CLR_INT (HK); /* no, clr intr */
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}
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else CLR_INT (HK); /* no, clr intr */
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hkcs1 = (hkcs1 & ~CS1_RW) | (data & CS1_RW); /* merge data */
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if (SC02C)
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hkspr = (hkspr & ~CS1_M_UAE) | GET_UAE (hkcs1);
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if ((data & CS1_GO) && !(hkcs1 & CS1_ERR)) /* go? */
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hk_go (drv);
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new_val = hkcs1;
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break;
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case 001: /* HKWC */
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hkwc = data;
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old_val = hkwc;
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new_val = hkwc = data;
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break;
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case 002: /* HKBA */
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hkba = data & ~BA_MBZ;
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old_val = hkba;
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new_val = hkba = data & ~BA_MBZ;
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break;
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case 003: /* HKDA */
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hkda = data & ~DA_MBZ;
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old_val = hkda;
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new_val = hkda = data & ~DA_MBZ;
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break;
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case 004: /* HKCS2 */
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old_val = hkcs2;
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if (data & CS2_CLR) /* init? */
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hk_reset (&hk_dev);
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else hkcs2 = (hkcs2 & ~CS2_RW) | (data & CS2_RW) | CS2_IR;
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drv = GET_UNIT (hkcs2);
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new_val = hkcs2;
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break;
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case 007: /* HKAS */
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hkof = data & AS_OF;
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old_val = hkof;
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new_val = hkof = data & AS_OF;
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break;
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case 010: /* HKDC */
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hkdc = data & ~DC_MBZ;
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old_val = hkdc;
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new_val = hkdc = data & ~DC_MBZ;
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break;
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case 011: /* spare */
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hkspr = data;
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old_val = hkspr;
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new_val = hkspr = data;
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if (SC02C) /* SC02C? upd UAE */
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hkcs1 = PUT_UAE (hkcs1, hkspr & 03);
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break;
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case 012: /* HKDB */
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hkdb[0] = data;
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old_val = hkdb[0];
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new_val = hkdb[0] = data;
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break;
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case 013: /* HKMR */
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hkmr = data & MR_RW;
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old_val = hkmr;
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new_val = hkmr = data & MR_RW;
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break;
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default: /* all others RO */
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case 014: /* HKEC1 */
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new_val = old_val = hkmr;
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break;
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case 015: /* HKEC2 */
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new_val = old_val = hkmr;
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break;
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case 016: /* HKMR2 */
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new_val = old_val = hkmr2;
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break;
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case 017: /* HKMR3 */
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new_val = old_val = hkmr3;
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break;
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} /* end switch */
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sim_debug_bits (HKDEB_RWR, &hk_dev, hk_reg_bits[j], old_val, new_val, 1);
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update_hkcs (0, drv); /* update status */
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return SCPE_OK;
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@ -691,9 +923,8 @@ static uint8 fnc_cyl[16] = {
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};
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||||
|
||||
fnc = GET_FNC (hkcs1);
|
||||
if (DEBUG_PRI (hk_dev, HKDEB_OPS))
|
||||
fprintf (sim_deb, ">>HK%d strt: fnc=%o, cs1=%o, cs2=%o, ds=%o, er=%o, cyl=%o, da=%o, ba=%o, wc=%o\n",
|
||||
drv, fnc, hkcs1, hkcs2, hkds[drv], hker[drv], hkdc, hkda, hkba, hkwc);
|
||||
sim_debug (HKDEB_OPS, &hk_dev, ">>HK%d strt: fnc=%s, cs1=%o, cs2=%o, ds=%o, er=%o, cyl=%o, da=%o, ba=%o, wc=%o\n",
|
||||
drv, hk_funcs[fnc], hkcs1, hkcs2, hkds[drv], hker[drv], hkdc, hkda, hkba, hkwc);
|
||||
uptr = hk_dev.units + drv; /* get unit */
|
||||
if (fnc != FNC_NOP) /* !nop, clr msg sel */
|
||||
hkmr = hkmr & ~MR_MS;
|
||||
|
|
@ -730,7 +961,7 @@ switch (fnc) { /* case on function */
|
|||
|
||||
/* Instantaneous functions (unit may be busy, can't schedule thread) */
|
||||
|
||||
case FNC_NOP: /* no operation */
|
||||
case FNC_NOP: /* no operation/select drive */
|
||||
hkmr2 = hk_rdmr2 (GET_MS (hkmr)); /* get serial msgs */
|
||||
hkmr3 = hk_rdmr3 (GET_MS (hkmr));
|
||||
update_hkcs (CS1_DONE, drv); /* done */
|
||||
|
|
@ -804,6 +1035,7 @@ uint16 comp;
|
|||
|
||||
drv = (uint32) (uptr - hk_dev.units); /* get drv number */
|
||||
fnc = uptr->FNC & CS1_M_FNC; /* get function */
|
||||
sim_debug (HKDEB_TRC, &hk_dev, "hk_svc(HK%d, fnc=%s)\n", drv, hk_funcs[fnc]);
|
||||
switch (fnc) { /* case on function */
|
||||
|
||||
/* Fast commands - start spindle only provides one interrupt
|
||||
|
|
@ -985,27 +1217,37 @@ return SCPE_OK;
|
|||
|
||||
void update_hkcs (int32 flag, int32 drv)
|
||||
{
|
||||
int32 i;
|
||||
int32 i, old_hkcs1 = hkcs1, old_hkcs2 = hkcs2;
|
||||
|
||||
sim_debug (HKDEB_TRC, &hk_dev, "update_hkcs(flag=0%o, drv=%d)\n", flag, drv);
|
||||
update_hkds (drv); /* upd drv status */
|
||||
if (flag & CS1_DONE) /* clear go */
|
||||
hkcs1 = hkcs1 & ~CS1_GO;
|
||||
if (hkcs1 & CS1_IE) { /* intr enable? */
|
||||
if (((flag & CS1_DONE) && ((hkcs1 & CS1_DONE) == 0)) ||
|
||||
((flag & CS1_DI) && (hkcs1 & CS1_DONE))) /* done 0->1 or DI? */
|
||||
SET_INT (HK);
|
||||
}
|
||||
else CLR_INT (HK);
|
||||
hkcs1 = (hkcs1 & (CS1_DT|CS1_UAE|CS1_DONE|CS1_IE|CS1_SPA|CS1_FNC|CS1_GO)) | flag;
|
||||
if (hkcs1 & CS1_DONE) /* done? clear GO */
|
||||
hkcs1 = hkcs1 & ~CS1_GO;
|
||||
for (i = 0; i < HK_NUMDR; i++) { /* if ATA, set DI */
|
||||
if (hkds[i] & DS_ATA) hkcs1 = hkcs1 | CS1_DI;
|
||||
if (hkds[i] & DS_ATA)
|
||||
hkcs1 = hkcs1 | CS1_DI;
|
||||
}
|
||||
if (hker[drv] | (hkcs1 & (CS1_PAR | CS1_CTO)) | /* if err, set ERR */
|
||||
(hkcs2 & CS2_ERR)) hkcs1 = hkcs1 | CS1_ERR;
|
||||
if ((flag & CS1_DONE) && /* set done && debug? */
|
||||
(DEBUG_PRI (hk_dev, HKDEB_OPS)))
|
||||
fprintf (sim_deb, ">>HK%d done: fnc=%o, cs1=%o, cs2=%o, ds=%o, er=%o, cyl=%o, da=%o, ba=%o, wc=%o\n",
|
||||
drv, GET_FNC (hkcs1), hkcs1, hkcs2, hkds[drv], hker[drv], hkdc, hkda, hkba, hkwc);
|
||||
if (hker[drv] || (hkcs1 & (CS1_PAR | CS1_CTO)) || (hkcs2 & CS2_ERR))
|
||||
hkcs1 = hkcs1 | CS1_ERR; /* if err, set ERR */
|
||||
if (hkcs1 & CS1_IE) { /* intr enable? */
|
||||
if (((hkcs1 & CS1_DONE) && ((old_hkcs1 & CS1_DONE) == 0)) ||
|
||||
((hkcs1 & CS1_DI) && (hkcs1 & CS1_DONE))) { /* done 0->1 or DI&done? */
|
||||
sim_debug (HKDEB_INT, &hk_dev, "update_hkcs(SET_INT)\n");
|
||||
SET_INT (HK);
|
||||
}
|
||||
}
|
||||
else {
|
||||
sim_debug (HKDEB_INT, &hk_dev, "update_hkcs(CLR_INT)\n");
|
||||
CLR_INT (HK);
|
||||
}
|
||||
if (old_hkcs1 != hkcs1)
|
||||
sim_debug_bits (HKDEB_OPS, &hk_dev, hk_cs1_bits, old_hkcs1, hkcs1, 1);
|
||||
if (old_hkcs2 != hkcs2)
|
||||
sim_debug_bits (HKDEB_OPS, &hk_dev, hk_cs2_bits, old_hkcs2, hkcs2, 1);
|
||||
if (flag & CS1_DONE) /* set done */
|
||||
sim_debug (HKDEB_OPS, &hk_dev, ">>HK%d done: fnc=%s, cs1=%o, cs2=%o, ds=%o, er=%o, cyl=%o, da=%o, ba=%o, wc=%o\n",
|
||||
drv, hk_funcs[GET_FNC (hkcs1)], hkcs1, hkcs2, hkds[drv], hker[drv], hkdc, hkda, hkba, hkwc);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -1013,10 +1255,13 @@ return;
|
|||
|
||||
void update_hkds (int32 drv)
|
||||
{
|
||||
int old_ds = hkds[drv];
|
||||
|
||||
if (hk_unit[drv].flags & UNIT_DIS) { /* disabled? */
|
||||
hkds[drv] = hker[drv] = 0; /* all clear */
|
||||
return;
|
||||
}
|
||||
sim_debug (HKDEB_TRC, &hk_dev, "update_hkds(drv=%d)\n", drv);
|
||||
hkds[drv] = (hkds[drv] & (DS_VV | DS_PIP | DS_ATA)) | DS_VLD | DS_DRA;
|
||||
if (hk_unit[drv].flags & UNIT_ATT) { /* attached? */
|
||||
if (!sim_is_active (&hk_unit[drv])) /* not busy? */
|
||||
|
|
@ -1034,6 +1279,8 @@ else {
|
|||
}
|
||||
if (hk_unit[drv].flags & UNIT_RK07)
|
||||
hkds[drv] = hkds[drv] | DS_DT;
|
||||
if (old_ds != hkds[drv])
|
||||
sim_debug_bits (HKDEB_TRC, &hk_dev, hk_ds_bits, old_ds, hkds[drv], 1);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -1041,6 +1288,7 @@ return;
|
|||
|
||||
void hk_cmderr (int32 err, int32 drv)
|
||||
{
|
||||
sim_debug (HKDEB_TRC, &hk_dev, "update_hkds(drv=%d, err=%d)\n", drv, err);
|
||||
hker[drv] = hker[drv] | err; /* set error */
|
||||
hkds[drv] = hkds[drv] | DS_ATA; /* set attn */
|
||||
update_hkcs (CS1_DONE, drv); /* set done */
|
||||
|
|
@ -1158,6 +1406,7 @@ t_stat hk_reset (DEVICE *dptr)
|
|||
int32 i;
|
||||
UNIT *uptr;
|
||||
|
||||
sim_debug (HKDEB_TRC, &hk_dev, "hk_reset()\n");
|
||||
hkcs1 = CS1_DONE; /* set done */
|
||||
hkcs2 = CS2_IR; /* clear state */
|
||||
hkmr = hkmr2 = hkmr3 = 0;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue