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VAX420: Fix for LANCE when system memory > 16MB

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Fixes #689
This commit is contained in:
Matt Burke 2019-04-28 23:33:07 +01:00
parent 4b43f32deb
commit 1d133bfc8e
6 changed files with 16 additions and 2 deletions
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1
VAX/is1000_defs.h
View file

@ -262,6 +262,7 @@ extern int32 sys_model;
#define XS_READW(ba,bc,buf) Map_ReadW(ba, bc, buf, FALSE)
#define XS_WRITEB(ba,bc,buf) Map_WriteB(ba, bc, buf, FALSE)
#define XS_WRITEW(ba,bc,buf) Map_WriteW(ba, bc, buf, FALSE)
#define XS_ADRMBO (0)
/* Function prototypes for I/O */

1
VAX/vax410_defs.h
View file

@ -337,6 +337,7 @@ extern int32 sys_model;
#define XS_READW Map_ReadW
#define XS_WRITEB Map_WriteB
#define XS_WRITEW Map_WriteW
#define XS_ADRMBO (0)
/* Function prototypes for I/O */

5
VAX/vax420_defs.h
View file

@ -381,6 +381,11 @@ extern int32 sys_model;
#define XS_READW Map_ReadW
#define XS_WRITEB Map_WriteB
#define XS_WRITEW Map_WriteW
#if (defined (VAX_411) || defined (VAX_412)) /* InfoServer? */
#define XS_ADRMBO (0)
#else
#define XS_ADRMBO ((MEMSIZE -1) & 0xFF000000) /* bits 31:24 have pull-ups */
#endif
/* Function prototypes for I/O */

1
VAX/vax43_defs.h
View file

@ -356,6 +356,7 @@ extern int32 sys_model;
#define XS_READW Map_ReadW
#define XS_WRITEB Map_WriteB
#define XS_WRITEW Map_WriteW
#define XS_ADRMBO (0)
/* Function prototypes for I/O */

1
VAX/vax440_defs.h
View file

@ -315,6 +315,7 @@ extern int32 sys_model;
#define XS_READW Map_ReadW
#define XS_WRITEB Map_WriteB
#define XS_WRITEW Map_WriteW
#define XS_ADRMBO (0)
/* Function prototypes for I/O */

5
VAX/vax_xs.c
View file

@ -346,6 +346,7 @@ while (xs->var->ReadQ.count > 0) {
/* set buffer length and address */
slen = (uint16)(xs->var->rxhdr[2] * -1); /* 2s Complement */
segb = xs->var->rxhdr[0] + ((xs->var->rxhdr[1] & RXR_HADR) << 16);
segb |= XS_ADRMBO; /* set system specific bits */
/* get first packet from receive queue */
if (!item) {
@ -474,6 +475,7 @@ for (;;) {
/* set buffer length and address */
slen = (uint16)(xs->var->txhdr[2] * -1); /* 2s complement */
segb = xs->var->txhdr[0] + ((xs->var->txhdr[1] & TXR_HADR) << 16);
segb |= XS_ADRMBO; /* set system specific bits */
wlen = slen;
sim_debug(DBG_TRC, xs->dev, "Using transmit descriptor=0x%X, slen=0x%04X(%d), segb=0x%04X, ", ba, slen, slen, segb);
@ -587,6 +589,7 @@ ethq_clear (&xs->var->ReadQ);
memset (&xs->var->setup, 0, sizeof(struct xs_setup));
xs->var->inbb = ((xs->var->csr2 & 0xFF) << 16) | (xs->var->csr1 & 0xFFFE);
xs->var->inbb |= XS_ADRMBO; /* set system specific bits */
sim_debug (DBG_REG, &xs_dev, "xs_inbb = %04X\n", xs->var->inbb);
if (XS_READB (xs->var->inbb, 0x18, &inb[0])) {
@ -610,6 +613,7 @@ w1 = GETW (inb, 0x10);
w2 = GETW (inb, 0x12);
xs->var->rdrb = ((w2 << 16) | w1) & 0xFFFFF8;
xs->var->rdrb |= XS_ADRMBO; /* set system specific bits */
xs->var->rrlen = (w2 >> 13) & 0x7;
xs->var->rrlen = (1u << xs->var->rrlen);
xs->var->relen = 4;
@ -621,6 +625,7 @@ w1 = GETW (inb, 0x14);
w2 = GETW (inb, 0x16);
xs->var->tdrb = ((w2 << 16) | w1) & 0xFFFFF8;
xs->var->tdrb |= XS_ADRMBO; /* set system specific bits */
xs->var->trlen = (w2 >> 13) & 0x7;
xs->var->trlen = (1u << xs->var->trlen);
xs->var->telen = 4;