ALL: make sure all useful state is in simh registers while processing events

ALTAIR/altair_cpu.c

@@ -309,6 +309,8 @@ t_stat sim_instr (void)
 
     while (reason == 0) {                               /* loop until halted */
         if (sim_interval <= 0) {                        /* check clock queue */
+            /* make sure all useful state is in simh registers while processing events */
+            saved_PC = PC;
             if ((reason = sim_process_event ())) break;
         }
 

GRI/gri_cpu.c

@@ -417,6 +417,9 @@ ao_update ();                                           /* update AO */
 while (reason == 0) {                                   /* loop until halted */
 
     if (sim_interval <= 0) {                            /* check clock queue */
+        /* make sure all useful state is in simh registers while processing events */
+        ao_update ();                                   /* update AO */
+        scq_r->qptr = scq_p;                            /* update sc q ptr */
         if ((reason = sim_process_event ()))
             break;
         }

H316/h316_cpu.c

@@ -441,6 +441,11 @@ reason = 0;
 while (reason == 0) {                                   /* loop until halted */
 
 if (sim_interval <= 0) {                                /* check clock queue */
+    /* make sure all useful state is in simh registers while processing events */
+    saved_AR = AR & DMASK;
+    saved_BR = BR & DMASK;
+    saved_XR = XR & DMASK;
+    pcq_r->qptr = pcq_p;                                /* update pc q ptr */
     if ((reason = sim_process_event ()))
         break;
     }

I1401/i1401_cpu.c

@@ -550,6 +550,12 @@ while (reason == 0) {                                   /* loop until halted */
 
     saved_IS = IS;                                      /* commit prev instr */
     if (sim_interval <= 0) {                            /* check clock queue */
+        /* make sure all useful state is in simh registers while processing events */
+        as_err = ADDR_ERR (AS);                         /* get addr err flags */
+        bs_err = ADDR_ERR (BS);
+        AS = AS & ADDRMASK;                             /* clean addresses */
+        BS = BS & ADDRMASK;
+        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
         if ((reason = sim_process_event ()))
             break;
         }

I1620/i1620_cpu.c

@@ -488,6 +488,9 @@ while (reason == 0) {                                   /* loop until halted */
 
     saved_PC = PC;                                      /* commit prev instr */
     if (sim_interval <= 0) {                            /* check clock queue */
+        /* make sure all useful state is in simh registers while processing events */
+        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
+        upd_ind ();
         if ((reason = sim_process_event ()))
             break;
         }

I7094/i7094_cpu.c

@@ -659,6 +659,8 @@ while (reason == SCPE_OK) {                             /* loop until error */
         }
 
     if (sim_interval <= 0) {                            /* intv cnt expired? */
+        /* make sure all useful state is in simh registers while processing events */
+        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
         if ((reason = sim_process_event ()))            /* process events */
             break;
         chtr_pend = chtr_eval (NULL);                   /* eval chan traps */

Interdata/id16_cpu.c

@@ -599,6 +599,10 @@ while (reason == 0) {                                   /* loop until halted */
     int32 sr, st;
 
     if (sim_interval <= 0) {                            /* check clock queue */
+        /* make sure all useful state is in simh registers while processing events */
+        PSW = BUILD_PSW (cc);
+        PC = PC & VAMASK;
+        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
         if ((reason = sim_process_event ()))
             break;
         int_eval ();

Interdata/id32_cpu.c

@@ -658,6 +658,11 @@ while (reason == 0) {                                   /* loop until halted */
     int32 sr, st;
 
     if (sim_interval <= 0) {                            /* check clock queue */
+        /* make sure all useful state is in simh registers while processing events */
+        PSW = BUILD_PSW (cc);
+        PC = PC & VAMASK;
+        set_r_display (R);
+        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
         if ((reason = sim_process_event ()))
             break;
         int_eval ();

LGP/lgp_cpu.c

@@ -283,6 +283,8 @@ if (lgp21_sov) {                                        /* stop sense pending? *
 
 do {
     if (sim_interval <= 0) {                            /* check clock queue */
+        /* make sure all useful state is in simh registers while processing events */
+        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
         if ((r = sim_process_event ()))
             break;
         }

NOVA/eclipse_cpu.c

@@ -737,6 +737,8 @@ if (MapInit == 0) {
 
 while (reason == 0) {                                   /* loop until halted */
 if (sim_interval <= 0) {                                /* check clock queue */
+    /* make sure all useful state is in simh registers while processing events */
+    saved_PC = PC;
     if ((reason = sim_process_event ())) 
         break;
 }

NOVA/nova_cpu.c

@@ -428,6 +428,9 @@ reason = 0;
 while (reason == 0) {                                   /* loop until halted */
 
     if (sim_interval <= 0) {                            /* check clock queue */
+        /* make sure all useful state is in simh registers while processing events */
+        saved_PC = PC;
+        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
         if ( (reason = sim_process_event ()) )
             break;
         }

PDP1/pdp1_cpu.c

@@ -546,6 +546,8 @@ reason = 0;
 while (reason == 0) {                                   /* loop until halted */
 
     if (sim_interval <= 0) {                            /* check clock queue */
+        /* Make sure all intermediate state is visible in simh registers */
+        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
         if ((reason = sim_process_event ()))
             break;
         sbs_lvl = sbs_eval ();                          /* eval sbs system */

PDP18B/pdp18b_cpu.c

@@ -597,6 +597,9 @@ while (reason == 0) {                                   /* loop until halted */
     int32 link_init, fill;
 
     if (sim_interval <= 0) {                            /* check clock queue */
+        /* Make sure all intermediate state is visible in simh registers */
+        iors = upd_iors ();                             /* get IORS */
+        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
         if ((reason = sim_process_event ()))
             break;
         api_int = api_eval (&int_pend);                 /* eval API */

PDP8/pdp8_cpu.c

@@ -339,6 +339,12 @@ reason = 0;
 while (reason == 0) {                                   /* loop until halted */
 
     if (sim_interval <= 0) {                            /* check clock queue */
+        /* Make sure all intermediate state is visible in simh registers */
+        saved_PC = IF | (PC & 07777);                   /* save copies */
+        saved_DF = DF & 070000;
+        saved_LAC = LAC & 017777;
+        saved_MQ = MQ & 07777;
+        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
         if ((reason = sim_process_event ()))
             break;
         }

S3/s3_cpu.c

@@ -521,6 +521,8 @@ reason = 0;
 
 while (reason == 0) {                                   /* loop until halted */
 if (sim_interval <= 0) {                                /* check clock queue */
+    /* make sure all useful state is in simh registers while processing events */
+    saved_PC = PC;
     if ((reason = sim_process_event ())) break;
 }
 

SDS/sds_cpu.c

@@ -382,6 +382,8 @@ while (reason == 0) {                                   /* loop until halted */
         }
 
     if (sim_interval <= 0) {                            /* event queue? */
+        /* make sure all useful state is in simh registers while processing events */
+        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
         if ((reason = sim_process_event ()))            /* process */
             break;
         int_reqhi = api_findreq ();                     /* recalc int req */

TX-0/tx0_cpu.c

@@ -462,6 +462,8 @@ t_stat sim_instr (void)
     while (reason == 0) {                                   /* loop until halted */
 
         if (sim_interval <= 0) {                            /* check clock queue */
+            /* make sure all useful state is in simh registers while processing events */
+            pcq_r->qptr = pcq_p;                            /* update pc q ptr */
             reason = sim_process_event ();
             if (reason != SCPE_OK)
                 break;

alpha/alpha_cpu.c

@@ -393,6 +393,11 @@ while (reason == 0) {
         }
 
     if (sim_interval <= 0) {                            /* chk clock queue */
+        /* make sure all useful state is in simh registers while processing events */
+        pcc_l = pcc_l & M32;
+        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
+        pc_align = ((uint32) PC) & 3;                   /* separate PC<1:0> */
+        PC = PC & 0xFFFFFFFFFFFFFFFC;
         if ((reason = sim_process_event ())) break;
         intr_summ = pal_eval_intr (1);                  /* eval interrupts */
         }

sigma/sigma_cpu.c

@@ -433,6 +433,10 @@ while (reason == 0) {                                   /* loop until stop */
         }
 
     if (sim_interval <= 0) {                            /* event queue? */
+        /* make sure all useful state is in simh registers while processing events */
+        pcq_r->qptr = pcq_p;                            /* update pc q ptr */
+        cpu_assemble_PSD ();                            /* visible PSD */
+        set_rf_display (R);                             /* visible registers */
         if (reason = sim_process_event ())              /* process */
             break;
         int_hireq = io_eval_int ();                     /* re-evaluate intr */