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MicroVAX1, all VAX: Add model specific instruction execution and emulation

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- Different VAX models had different groups of instructions which were
  implemented in hardware vs trappng to the OS for emulation.  Functionality
  has been added to differentiate the various mix of instruction groups for
  different models and to display both the groups and the actual instructions.
- Visibility to Instruction groups is provided by SHOW CPU INSTRUCTIONS
  and the list of the active instructions implemented and emulated via
  SHOW CPU -V INSTRUCTIONS.
- The MicroVAX I CPU handled some execution fault conditions differently
  from other VAX systems these differences are now specifically handled.
- Add build time test support to MicroVAX I running EHKAA v1.13
  suggested in #683
- Add more CPU debug details relating to exception and interrupt processing
This commit is contained in:
Mark Pizzolato 2019-04-30 14:28:37 -07:00
parent 5e540cea98
commit 621e97e170
37 changed files with 1048 additions and 751 deletions
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5
VAX/is1000_defs.h
View file

@ -79,8 +79,7 @@
/* CPU */
#define CPU_MODEL_MODIFIERS \
{ 0 }
#define CPU_MODEL_MODIFIERS
/* Memory */
@ -157,7 +156,7 @@
#define LP_MBZ84_TEST(r)
#define LP_MBZ92_TEST(r)
#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST)
/* Common CSI flags */

4
VAX/is1000_sysdev.c
View file

@ -582,7 +582,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(ReadIPR);
}
return val;
@ -627,7 +627,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(WriteIPR);
}
return;

BIN
VAX/tests/ehkaa-uv1.exe Normal file
View file

Binary file not shown.

9
VAX/tests/vax-diag_test.ini
View file

@ -26,7 +26,6 @@ goto DIAG_%SIM_BIN_NAME%
:DIAG_INFOSERVER100
:DIAG_INFOSERVER1000
:DIAG_INFOSERVER150VTX
:DIAG_MICROVAX1
:DIAG_MICROVAX2
:DIAG_MICROVAX2000
:DIAG_MICROVAX3100
@ -41,6 +40,14 @@ goto DIAG_%SIM_BIN_NAME%
echof "No diagnostics are available for the %SIM_NAME% Simulator\n"
exit 0
:DIAG_MICROVAX1
echo Running Hardware Core Test (EHKAA)
if not exist ehkaa-uv1.exe echof "\r\nMISSING - Diagnostic '%~p0ehkaa-uv1.exe' is missing\n"; exit 1
load ehkaa-uv1.exe
go -q 200
if (PC != 0x1150DA51) echof "\r\n*** FAILED - %SIM_NAME% Hardware Core Instruction test EHKAA\n"; exit 1
else echof "\r\n*** PASSED - %SIM_NAME% Hardware Core Instruction test EHKAA\n"; exit 0
:DIAG_VAX
:DIAG_MICROVAX3900
echo Running Hardware Core Test (EHKAA)

4
VAX/vax410_defs.h
View file

@ -84,7 +84,7 @@
#define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={MICROVAX|VAXSTATION|VAXSTATIONGPX}", \
cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" }
cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" },
/* Memory */
@ -208,7 +208,7 @@
#define LP_MBZ84_TEST(r)
#define LP_MBZ92_TEST(r)
#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST)
/* Common CSI flags */

4
VAX/vax410_sysdev.c
View file

@ -484,7 +484,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(ReadIPR);
}
return val;
@ -516,7 +516,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(WriteIPR);
}
return;

9
VAX/vax420_defs.h
View file

@ -84,17 +84,16 @@
/* CPU */
#if defined (VAX_411) || defined (VAX_412)
#define CPU_MODEL_MODIFIERS \
{ 0 }
#define CPU_MODEL_MODIFIERS
#else
#if defined (VAX_41A) || defined (VAX_41D)
#define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={MICROVAX|VAXSERVER}", \
cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" }
cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" },
#else /* defined (VAX_42A) || defined (VAX_42B) */
#define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={MICROVAX|VAXSTATION|VAXSTATIONGPX|VAXSTATIONSPX}", \
cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" }
cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" },
#endif
#endif
@ -235,7 +234,7 @@
#define LP_MBZ84_TEST(r)
#define LP_MBZ92_TEST(r)
#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST)
/* Common CSI flags */

4
VAX/vax43_defs.h
View file

@ -93,7 +93,7 @@
#define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={MICROVAX|VAXSTATION|VAXSTATIONSPX}", \
cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" }
cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" },
/* Memory */
@ -230,7 +230,7 @@
#define LP_MBZ84_TEST(r)
#define LP_MBZ92_TEST(r)
#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST)
/* Common CSI flags */

4
VAX/vax43_sysdev.c
View file

@ -603,7 +603,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(ReadIPR);
}
return val;
@ -666,7 +666,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(WriteIPR);
}
return;

7
VAX/vax440_defs.h
View file

@ -98,10 +98,9 @@
#if defined (VAX_46) || defined (VAX_48)
#define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={MICROVAX|VAXSTATION}", \
cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" }
cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" },
#else
#define CPU_MODEL_MODIFIERS \
{ 0 }
#define CPU_MODEL_MODIFIERS
#endif
/* Memory */
@ -210,7 +209,7 @@
#define LP_MBZ84_TEST(r)
#define LP_MBZ92_TEST(r)
#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST)
/* Common CSI flags */

4
VAX/vax440_sysdev.c
View file

@ -519,7 +519,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(ReadIPR);
}
return val;
@ -576,7 +576,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(WriteIPR);
}
return;

9
VAX/vax610_defs.h
View file

@ -96,7 +96,12 @@
#define CPU_MODEL_MODIFIERS { MTAB_XTD|MTAB_VDV, 0, "LEDS", NULL, \
NULL, &cpu_show_leds, NULL, "Display the CPU LED values" }, \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={MicroVAX|VAXStation}", \
&cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" }
&cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" },
#define CPU_INSTRUCTION_SET (VAX_BASE | VAX_GFLOAT)
#define CPU_INST_MODIFIERS { MTAB_XTD|MTAB_VDV|MTAB_VALR|MTAB_NMO, 0, "INSTRUCTIONS", "INSTRUCTIONS={G-FLOAT|NOG-FLOAT|D-FLOAT|NOD-FLOAT}", \
&cpu_set_instruction_set, NULL, NULL, "Set the CPU Instruction Set" }, \
{ MTAB_XTD|MTAB_VDV, 0, "INSTRUCTIONS", NULL, \
NULL, &cpu_show_instruction_set, NULL, "Show the CPU Instruction Set (SHOW -V)" },
/* QVSS memory space */
@ -150,7 +155,7 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc
#define LP_MBZ84_TEST(r)
#define LP_MBZ92_TEST(r)
#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST)
#define IDX_IMM_TEST
/* Qbus I/O modes */

2
VAX/vax610_stddev.c
View file

@ -312,7 +312,7 @@ if (sel == TXDB_MISC) { /* misc function? */
}
else
if (sel != 0)
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(txdb_func);
}

6
VAX/vax610_sysdev.c
View file

@ -184,7 +184,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(ReadIPR);
}
return val;
@ -223,7 +223,7 @@ switch (rg) {
case MT_CONISP:
case MT_CONPC:
case MT_CONPSL: /* halt reg */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(WriteIPR);
case MT_NICR: /* NICR */
case MT_ICR: /* ICR */
@ -249,7 +249,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(WriteIPR);
}
return;

4
VAX/vax630_defs.h
View file

@ -108,7 +108,7 @@
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 1, "NOAUTOBOOT", "NOAUTOBOOT", \
&sysd_set_halt, &sysd_show_halt, NULL, "Disable autoboot (Enable Halt)" }, \
{ MTAB_XTD|MTAB_VDV, 0, "LEDS", NULL, \
NULL, &sysd_show_leds, NULL, "Display the CPU LED values" }
NULL, &sysd_show_leds, NULL, "Display the CPU LED values" },
/* Memory */
@ -215,7 +215,7 @@ extern uint32 va_addr; /* QDSS memory offset */
#define LP_MBZ84_TEST(r)
#define LP_MBZ92_TEST(r)
#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST)
/* Qbus I/O modes */

6
VAX/vax630_sysdev.c
View file

@ -609,7 +609,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(ReadIPR);
}
return val;
@ -648,7 +648,7 @@ switch (rg) {
case MT_CONISP:
case MT_CONPC:
case MT_CONPSL: /* halt reg */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(WriteIPR);
case MT_NICR: /* NICR */
case MT_ICR: /* ICR */
@ -674,7 +674,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(WriteIPR);
}
return;

18
VAX/vax730_defs.h
View file

@ -104,24 +104,24 @@
/* 780 microcode patch 37 - only test LR<23:0> for appropriate length */
#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT
#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT(ML_LR_TEST)
/* 780 microcode patch 38 - only test PxBR<31>=1, PxBR<30> = 0, and xBR<1:0> = 0 */
#define ML_PXBR_TEST(r) if (((((uint32)(r)) & 0x80000000) == 0) || \
((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT
#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT
((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT(ML_PXBR_TEST)
#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT(ML_SBR_TEST)
/* 780 microcode patch 78 - test xCBB<1:0> = 0 */
#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT
#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT(ML_PA_TEST)
#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(LP_AST_TEST)
#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT(LP_MBZ84_TEST)
#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT(LP_MBZ92_TEST)
#define MT_AST_TEST(r) r = (r) & 07; \
if ((r) > AST_MAX) RSVD_OPND_FAULT
if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST)
#define IDX_IMM_TEST
/* Memory */
@ -142,7 +142,7 @@
extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc);
#define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \
NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" }
NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" },
/* Unibus I/O registers */

4
VAX/vax730_sys.c
View file

@ -289,7 +289,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(ReadIPR);
}
return val;
@ -355,7 +355,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(WriteIPR);
}
return;

4
VAX/vax750_cmi.c
View file

@ -349,7 +349,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(ReadIPR);
}
return val;
@ -418,7 +418,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(WriteIPR);
}
return;

18
VAX/vax750_defs.h
View file

@ -125,24 +125,24 @@
/* 780 microcode patch 37 - only test LR<23:0> for appropriate length */
#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT
#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT(ML_LR_TEST)
/* 780 microcode patch 38 - only test PxBR<31>=1, PxBR<30> = 0, and xBR<1:0> = 0 */
#define ML_PXBR_TEST(r) if (((((uint32)(r)) & 0x80000000) == 0) || \
((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT
#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT
((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT(ML_PXBR_TEST)
#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT(ML_SBR_TEST)
/* 780 microcode patch 78 - test xCBB<1:0> = 0 */
#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT
#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT(ML_PA_TEST)
#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(LP_AST_TEST)
#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT(LP_MBZ84_TEST)
#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT(LP_MBZ92_TEST)
#define MT_AST_TEST(r) r = (r) & 07; \
if ((r) > AST_MAX) RSVD_OPND_FAULT
if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST)
#define IDX_IMM_TEST
/* Memory */
@ -168,7 +168,7 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc
#define CPU_MODEL_MODIFIERS { MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \
NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" }, \
{ MTAB_XTD|MTAB_VDV, 0, "BOOTDEV", "BOOTDEV={A|B|C|D}", \
&vax750_set_bootdev, &vax750_show_bootdev, NULL, "Set Boot Device" }
&vax750_set_bootdev, &vax750_show_bootdev, NULL, "Set Boot Device" },
extern t_stat vax750_set_bootdev (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat vax750_show_bootdev (FILE *st, UNIT *uptr, int32 val, CONST void *desc);

18
VAX/vax780_defs.h
View file

@ -144,24 +144,24 @@
/* 780 microcode patch 37 - only test LR<23:0> for appropriate length */
#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT
#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT(ML_LR_TEST)
/* 780 microcode patch 38 - only test PxBR<31>=1, PxBR<30> = 0, and xBR<1:0> = 0 */
#define ML_PXBR_TEST(r) if (((((uint32)(r)) & 0x80000000) == 0) || \
((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT
#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT
((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT(ML_PXBR_TEST)
#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT(ML_SBR_TEST)
/* 780 microcode patch 78 - test xCBB<1:0> = 0 */
#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT
#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT(ML_PA_TEST)
#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(LP_AST_TEST)
#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT(LP_MBZ84_TEST)
#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT(LP_MBZ92_TEST)
#define MT_AST_TEST(r) r = (r) & 07; \
if ((r) > AST_MAX) RSVD_OPND_FAULT
if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST)
#define IDX_IMM_TEST
/* Memory */
@ -186,7 +186,7 @@
extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc);
#define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={780|785}", \
&cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" }
&cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" },
/* Unibus I/O registers */

6
VAX/vax780_sbi.c
View file

@ -387,7 +387,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(ReadIPR);
}
return val;
@ -466,7 +466,7 @@ switch (rg) {
case MT_SBIQC: /* SBIQC */
if (val & SBIQC_MBZ) {
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(WriteIPR);
}
WriteLP (val, 0);
WriteLP (val + 4, 0);
@ -477,7 +477,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(WriteIPR);
}
return;

4
VAX/vax820_bi.c
View file

@ -390,7 +390,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(ReadIPR);
}
return val;
@ -470,7 +470,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(WriteIPR);
}
return;

4
VAX/vax820_defs.h
View file

@ -149,13 +149,13 @@
#define LP_MBZ84_TEST(r)
#define LP_MBZ92_TEST(r)
#define MT_AST_TEST(r) r = (r) & 07; \
if ((r) > AST_MAX) RSVD_OPND_FAULT
if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST)
/* CPU */
#define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={8200|8250}", \
&cpu_set_model, &cpu_show_model, NULL, "Set/Display processor model" }
&cpu_set_model, &cpu_show_model, NULL, "Set/Display processor model" },
/* Memory */

4
VAX/vax860_abus.c
View file

@ -486,7 +486,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(ReadIPR);
}
return val;
@ -559,7 +559,7 @@ switch (rg) {
break;
default:
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(WriteIPR);
}
return;

18
VAX/vax860_defs.h
View file

@ -162,24 +162,24 @@
/* 780 microcode patch 37 - only test LR<23:0> for appropriate length */
#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT
#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT(ML_LR_TEST)
/* 780 microcode patch 38 - only test PxBR<31>=1, PxBR<30> = 0, and xBR<1:0> = 0 */
#define ML_PXBR_TEST(r) if (((((uint32)(r)) & 0x80000000) == 0) || \
((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT
#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT
((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT(ML_PXBR_TEST)
#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT(ML_SBR_TEST)
/* 780 microcode patch 78 - test xCBB<1:0> = 0 */
#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT
#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT(ML_PA_TEST)
#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(LP_AST_TEST)
#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT(LP_MBZ84_TEST)
#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT(LP_MBZ92_TEST)
#define MT_AST_TEST(r) r = (r) & 07; \
if ((r) > AST_MAX) RSVD_OPND_FAULT
if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST)
#define IDX_IMM_TEST
/* Memory */
@ -206,7 +206,7 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc
#define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={8600|8650}", \
&cpu_set_model, &cpu_show_model, NULL, "Set/Display processor model" }
&cpu_set_model, &cpu_show_model, NULL, "Set/Display processor model" },
/* Unibus I/O registers */

86
VAX/vax_cis.c
View file

@ -418,7 +418,7 @@ switch (opc) { /* case on opcode */
case MOVP:
if ((PSL & PSL_FPD) || (op[0] > 31))
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(MOVP);
ReadDstr (op[0], op[1], &dst, acc); /* read source */
cc = WriteDstr (op[0], op[2], &dst, 0, acc) | /* write dest */
(cc & CC_C); /* preserve C */
@ -456,7 +456,7 @@ switch (opc) { /* case on opcode */
case ADDP6: case SUBP6:
if ((PSL & PSL_FPD) || (op[0] > 31) ||
(op[2] > 31) || (op[4] > 31))
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(ADDP-SUBP);
ReadDstr (op[0], op[1], &src1, acc); /* get src1 */
ReadDstr (op[2], op[3], &src2, acc); /* get src2 */
if (opc & 2) /* sub? invert sign */
@ -510,7 +510,7 @@ switch (opc) { /* case on opcode */
case MULP:
if ((PSL & PSL_FPD) || (op[0] > 31) ||
(op[2] > 31) || (op[4] > 31))
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(MULP);
dst = Dstr_zero; /* clear result */
if (ReadDstr (op[0], op[1], &src1, acc) && /* read src1, src2 */
ReadDstr (op[2], op[3], &src2, acc)) { /* if both > 0 */
@ -560,7 +560,7 @@ switch (opc) { /* case on opcode */
case DIVP:
if ((PSL & PSL_FPD) || (op[0] > 31) ||
(op[2] > 31) || (op[4] > 31))
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(DIVP);
ldivr = ReadDstr (op[0], op[1], &src1, acc); /* get divisor */
if (ldivr == 0) { /* divisor = 0? */
SET_TRAP (TRAP_FLTDIV); /* dec div trap */
@ -624,7 +624,7 @@ switch (opc) { /* case on opcode */
op[2] = op[0];
case CMPP4:
if ((PSL & PSL_FPD) || (op[0] > 31) || (op[2] > 31))
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(CMPP);
ReadDstr (op[0], op[1], &src1, acc); /* get src1 */
ReadDstr (op[2], op[3], &src2, acc); /* get src2 */
cc = 0;
@ -664,7 +664,7 @@ switch (opc) { /* case on opcode */
case ASHP:
if ((PSL & PSL_FPD) || (op[1] > 31) || (op[4] > 31))
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(ASHP);
ReadDstr (op[1], op[2], &src1, acc); /* get source */
V = 0; /* init V */
shift = op[0]; /* get shift count */
@ -710,7 +710,7 @@ switch (opc) { /* case on opcode */
case CVTPL:
if ((PSL & PSL_FPD) || (op[0] > 31))
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(CVTPL);
ReadDstr (op[0], op[1], &src1, acc); /* get source */
V = result = 0; /* clear V, result */
for (i = (DSTRLNT * 8) - 1; i > 0; i--) { /* loop thru digits */
@ -759,7 +759,7 @@ switch (opc) { /* case on opcode */
case CVTLP:
if ((PSL & PSL_FPD) || (op[1] > 31))
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(CVTLP);
dst = Dstr_zero; /* clear result */
result = op[0];
if ((result & LSIGN) != 0) {
@ -797,17 +797,17 @@ switch (opc) { /* case on opcode */
case CVTSP:
if ((PSL & PSL_FPD) || (op[0] > 31) || (op[2] > 31))
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(CVTSP);
dst = Dstr_zero; /* clear result */
t = Read (op[1], L_BYTE, RA); /* read source sign */
if (t == C_MINUS) /* sign -, */
dst.sign = 1;
else if ((t != C_PLUS) && (t != C_SPACE)) /* + or blank? */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(CVTSP);
for (i = 1; i <= op[0]; i++) { /* loop thru chars */
c = Read ((op[1] + op[0] + 1 - i) & LMASK, L_BYTE, RA);
if ((c < C_ZERO) || (c > C_NINE)) /* [0:9]? */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(CVTSP);
d = c & 0xF;
dst.val[i / 8] = dst.val[i / 8] | (d << ((i % 8) * 4));
}
@ -838,7 +838,7 @@ switch (opc) { /* case on opcode */
case CVTPS:
if ((PSL & PSL_FPD) || (op[0] > 31) || (op[2] > 31))
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(CVTPS);
lenl = ReadDstr (op[0], op[1], &dst, acc); /* get source, lw len */
lenp = LntDstr (&dst, lenl); /* get exact nz src len */
ProbeDstr (op[2], op[3], WA); /* test dst write */
@ -879,13 +879,13 @@ switch (opc) { /* case on opcode */
case CVTTP:
if ((PSL & PSL_FPD) || (op[0] > 31) || (op[3] > 31))
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(CVTTP);
dst = Dstr_zero; /* clear result */
for (i = 1; i <= op[0]; i++) { /* loop thru char */
c = Read ((op[1] + op[0] - i) & LMASK, L_BYTE, RA); /* read char */
if (i != 1) { /* normal byte? */
if ((c < C_ZERO) || (c > C_NINE)) /* valid digit? */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(CVTTP);
d = c & 0xF;
}
else { /* highest byte */
@ -893,7 +893,7 @@ switch (opc) { /* case on opcode */
d = (t >> 4) & 0xF; /* digit */
t = t & 0xF; /* sign */
if ((d > 0x9) || (t < 0xA))
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(CVTTP);
if ((t == 0xB) || (t == 0xD))
dst.sign = 1;
}
@ -927,7 +927,7 @@ switch (opc) { /* case on opcode */
case CVTPT:
if ((PSL & PSL_FPD) || (op[0] > 31) || (op[3] > 31))
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(CVTPT);
lenl = ReadDstr (op[0], op[1], &dst, acc); /* get source, lw len */
lenp = LntDstr (&dst, lenl); /* get exact src len */
ProbeDstr (op[3], op[4], WA); /* test writeability */
@ -1007,7 +1007,7 @@ switch (opc) { /* case on opcode */
}
else { /* new instr */
if (op[0] > 31) /* lnt > 31? */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(EDITPC);
t = Read ((op[1] + (op[0] / 2)) & LMASK, L_BYTE, RA) & 0xF;
if ((t == 0xB) || (t == 0xD)) {
cc = CC_N | CC_Z;
@ -1034,7 +1034,7 @@ switch (opc) { /* case on opcode */
if (pop & EO_RPT_FLAG) { /* repeat class? */
rpt = pop & EO_RPT_MASK; /* isolate count */
if (rpt == 0) /* can't be zero */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(EDITPC);
pop = pop & ~EO_RPT_MASK; /* isolate op */
}
switch (pop) { /* case on op */
@ -1093,7 +1093,7 @@ switch (opc) { /* case on opcode */
case EO_BLANK_ZERO: /* blank zero */
t = Read ((R[3] + 1) & LMASK, L_BYTE, RA);
if (t == 0)
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(EDITPC);
if (cc & CC_Z) { /* zero? */
do { /* repeat and blank */
Write ((R[5] - t) & LMASK, fill, L_BYTE, WA);
@ -1105,7 +1105,7 @@ switch (opc) { /* case on opcode */
case EO_REPL_SIGN: /* replace sign */
t = Read ((R[3] + 1) & LMASK, L_BYTE, RA);
if (t == 0)
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(EDITPC);
if (cc & CC_Z)
Write ((R[5] - t) & LMASK, fill, L_BYTE, WA);
R[3]++; /* now fault safe */
@ -1114,7 +1114,7 @@ switch (opc) { /* case on opcode */
case EO_ADJUST_LNT: /* adjust length */
t = Read ((R[3] + 1) & LMASK, L_BYTE, RA);
if ((t == 0) || (t > 31))
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(EDITPC);
R[0] = R[0] & WMASK; /* clr old ld zero */
if (R[0] > t) { /* decrease */
for (i = 0; i < (R[0] - t); i++) { /* loop thru src */
@ -1162,7 +1162,7 @@ switch (opc) { /* case on opcode */
break;
default: /* undefined */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(EDITPC);
} /* end case pattern */
R[3] = (R[3] + 1) & LMASK; /* next pattern byte */
@ -1170,7 +1170,7 @@ switch (opc) { /* case on opcode */
} /* end for pattern */
if (R[0]) /* pattern too short */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(EDITPC);
PSL = PSL & ~PSL_FPD; /* clear FPD */
if (cc & CC_Z) /* zero? clear n */
cc = cc & ~CC_N;
@ -1182,7 +1182,7 @@ switch (opc) { /* case on opcode */
return cc;
default:
RSVD_INST_FAULT;
RSVD_INST_FAULT(opc);
}
/* end case op */
return cc;
@ -1614,7 +1614,7 @@ r1 = (R[1] + (inc / 2) + ((~R[0] & inc) & 1)) & LMASK; /* eff addr */
r0 = (R[0] - inc) & 0x1F; /* eff lnt left */
if (r0 == 0) { /* nothing left? */
R[0] = -1; /* out of input */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(edit_read_src);
}
c = Read (r1, L_BYTE, RA);
return (((r0 & 1)? (c >> 4): c) & 0xF);
@ -1646,49 +1646,19 @@ return sign;
#else
extern int32 cpu_emulate_exception (int32 *opnd, int32 cc, int32 opc, int32 acc);
/* CIS instructions - invoke emulator interface
opnd[0:5] = six operands to be pushed (if PSL<fpd> = 0)
cc = condition codes
opc = opcode
If FPD is set, push old PC and PSL on stack, vector thru SCB.
If FPD is clear, push opcode, old PC, operands, new PC, and PSL
on stack, vector thru SCB.
In both cases, the exception occurs in the current mode.
*/
int32 op_cis (int32 *opnd, int32 cc, int32 opc, int32 acc)
{
int32 vec;
if (PSL & PSL_FPD) { /* FPD set? */
Read (SP - 1, L_BYTE, WA); /* wchk stack */
Write (SP - 8, fault_PC, L_LONG, WA); /* push old PC */
Write (SP - 4, PSL | cc, L_LONG, WA); /* push PSL */
SP = SP - 8; /* decr stk ptr */
vec = ReadLP ((SCBB + SCB_EMULFPD) & PAMASK);
}
else {
if (opc == CVTPL) /* CVTPL? .wl */
opnd[2] = (opnd[2] >= 0)? ~opnd[2]: opnd[3];
Read (SP - 1, L_BYTE, WA); /* wchk stack */
Write (SP - 48, opc, L_LONG, WA); /* push opcode */
Write (SP - 44, fault_PC, L_LONG, WA); /* push old PC */
Write (SP - 40, opnd[0], L_LONG, WA); /* push operands */
Write (SP - 36, opnd[1], L_LONG, WA);
Write (SP - 32, opnd[2], L_LONG, WA);
Write (SP - 28, opnd[3], L_LONG, WA);
Write (SP - 24, opnd[4], L_LONG, WA);
Write (SP - 20, opnd[5], L_LONG, WA);
Write (SP - 8, PC, L_LONG, WA); /* push cur PC */
Write (SP - 4, PSL | cc, L_LONG, WA); /* push PSL */
SP = SP - 48; /* decr stk ptr */
vec = ReadLP ((SCBB + SCB_EMULATE) & PAMASK);
}
PSL = PSL & ~(PSL_TP | PSL_FPD | PSW_DV | PSW_FU | PSW_IV | PSW_T);
JUMP (vec & ~03); /* set new PC */
return 0; /* set new cc's */
return cpu_emulate_exception (opnd, cc, opc, acc);
}
#endif

2
VAX/vax_cmode.c
View file

@ -1308,7 +1308,7 @@ return TRUE; /* always bad */
int32 op_cmode (int32 cc)
{
RSVD_INST_FAULT;
RSVD_INST_FAULT(0);
return cc;
}

257
VAX/vax_cpu.c
View file

@ -262,6 +262,7 @@ int32 fault_PC; /* fault PC */
int32 mxpr_cc_vc = 0; /* MxPR V,C bits */
int32 pcq_p = 0; /* PC queue ptr */
int32 badabo = 0;
int32 cpu_instruction_set = CPU_INSTRUCTION_SET; /* Instruction Groups */
int32 cpu_astop = 0;
int32 mchk_va, mchk_ref; /* mem ref param */
int32 ibufl, ibufh; /* prefetch buf */
@ -307,7 +308,6 @@ const uint32 align[4] = {
/* External and forward references */
extern int32 sys_model;
extern const char *opcode[];
t_stat cpu_reset (DEVICE *dptr);
t_bool cpu_is_pc_a_subroutine_call (t_addr **ret_addrs);
@ -319,12 +319,15 @@ t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
t_stat cpu_show_virt (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
t_stat cpu_set_idle (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
t_stat cpu_show_idle (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
t_stat cpu_set_instruction_set (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
t_stat cpu_show_instruction_set (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
const char *cpu_description (DEVICE *dptr);
int32 cpu_get_vsw (int32 sw);
static SIM_INLINE int32 get_istr (int32 lnt, int32 acc);
int32 ReadOcta (int32 va, int32 *opnd, int32 j, int32 acc);
t_bool cpu_show_opnd (FILE *st, InstHistory *h, int32 line);
t_stat cpu_show_hist_records (FILE *st, t_bool do_header, int32 start, int32 count);
int32 cpu_emulate_exception (int32 *opnd, int32 cc, int32 opc, int32 acc);
void cpu_idle (void);
/* CPU data structures
@ -342,7 +345,7 @@ UNIT cpu_unit = {
const char *psl_modes[] = {"K", "E", "S", "U"};
BITFIELD psl_bits[] = {
BITFIELD cpu_psl_bits[] = {
BIT(C), /* Carry */
BIT(V), /* Overflow */
BIT(Z), /* Zero */
@ -384,7 +387,7 @@ REG cpu_reg[] = {
{ HRDATAD (AP, R[nAP], 32, "Alias for R12") },
{ HRDATAD (FP, R[nFP], 32, "Alias for R13") },
{ HRDATAD (SP, R[nSP], 32, "Alias for R14") },
{ HRDATADF(PSL, PSL, 32, "processor status longword", psl_bits) },
{ HRDATADF(PSL, PSL, 32, "processor status longword", cpu_psl_bits) },
{ HRDATAD (CC, PSL, 4, "condition codes, PSL<3:0>") },
{ HRDATAD (KSP, KSP, 32, "kernel stack pointer") },
{ HRDATAD (ESP, ESP, 32, "executive stack pointer") },
@ -428,18 +431,21 @@ MTAB cpu_mod[] = {
&cpu_set_hist, &cpu_show_hist, NULL, "Displays instruction history" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL,
NULL, &cpu_show_virt, NULL, "show translation for address arg in KESU mode" },
CPU_MODEL_MODIFIERS, /* Model specific cpu modifiers from vaxXXX_defs.h */
CPU_MODEL_MODIFIERS /* Model specific cpu modifiers from vaxXXX_defs.h */
CPU_INST_MODIFIERS /* Model specific cpu instruction modifiers from vaxXXX_defs.h */
{ 0 }
};
DEBTAB cpu_deb[] = {
{ "INTEXC", LOG_CPU_I, "interrupt and exception activities" },
{ "REI", LOG_CPU_R, "REI activities" },
{ "ABORT", LOG_CPU_A, "Abort activities" },
{ "CONTEXT", LOG_CPU_P, "context switching activities" },
{ "RSVDFAULT", LOG_CPU_FAULT_RSVD, "reserved fault activities" },
{ "FLTFAULT", LOG_CPU_FAULT_FLT, "floating fault activities" },
{ "CMODFAULT", LOG_CPU_FAULT_CMODE, "cmode fault activities" },
{ "MCHKFAULT", LOG_CPU_FAULT_MCHK, "machine check fault activities" },
{ "EMULFAULT", LOG_CPU_FAULT_EMUL, "instruction emulation fault activities" },
{ NULL, 0 }
};
@ -527,6 +533,9 @@ else if (abortval < 0) { /* mm or rsrv or int */
else R[rrn] = R[rrn] + rlnt;
}
}
sim_debug (LOG_CPU_A, &cpu_dev, "abort=%08X, fault_PC=%08x, SP=%08x, PC=%08x, PSL=%08x ",
-abortval, fault_PC, PC, SP, PSL);
sim_debug_bits(LOG_CPU_A, &cpu_dev, cpu_psl_bits, PSL, PSL, 1);
PSL = PSL & ~PSL_TP; /* clear <tp> */
recqptr = 0; /* clear queue */
delta = PC - fault_PC; /* save delta PC */
@ -574,6 +583,8 @@ else if (abortval < 0) { /* mm or rsrv or int */
break;
case SCB_MCHK: /* machine check */
sim_debug (LOG_CPU_FAULT_MCHK, &cpu_dev, "%s fault_PC=%08x, PSL=%08x, cc=%08x, PC=%08x, delta-%08X, p1=%08X\n",
opcode[opc], fault_PC, PSL, cc, PC, delta, p1);
cc = machine_check (p1, opc, cc, delta); /* system specific */
in_ie = 0;
GET_CUR; /* PSL<cur> changed */
@ -717,9 +728,27 @@ for ( ;; ) {
opc = opc | 0x100; /* flag */
}
numspec = drom[opc][0]; /* get # specs */
#if !defined(FULL_VAX)
if (((DR_GETIGRP(numspec) == DR_GETIGRP(IG_BSDFL)) && (!(cpu_instruction_set & VAX_DFLOAT))) ||
((DR_GETIGRP(numspec) == DR_GETIGRP(IG_BSGFL)) && (!(cpu_instruction_set & VAX_GFLOAT))) ||
(DR_GETIGRP(numspec) == DR_GETIGRP(IG_RSVD))) /* explicit reserved instruction? */
RSVD_INST_FAULT(opc);
#endif
#if defined(VAX_610)
/*
* This case is formally UNPREDICTABLE, but how the MicroVAX I CPU
* worked. Instructions without the DR_F in their drom table entry
* are specifically uninterruptible instructions, so this would not
* ever happen during normal execution, but the MicroVAX I HCORE
* diagnostic contrives this as a test and expects thost cases to
* be ignored.
*/
if ((PSL & PSL_FPD) && (numspec & DR_F)) {
#else
if (PSL & PSL_FPD) {
if ((numspec & DR_F) == 0)
RSVD_INST_FAULT;
RSVD_INST_FAULT(opc);
#endif
j = 0; /* no operands */
}
else {
@ -1784,7 +1813,7 @@ for ( ;; ) {
if (op1 >= 0) temp = R[op1] & WMASK; /* reg? ADDW2 */
else {
if (op2 & 1) /* mem? chk align */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(ADAWI);
temp = Read (op2, L_WORD, WA); /* ok, ADDW2 */
}
r = (op0 + temp) & WMASK;
@ -2590,7 +2619,7 @@ for ( ;; ) {
case HALT:
if (PSL & PSL_CUR) /* not kern? rsvd inst */
RSVD_INST_FAULT;
RSVD_INST_FAULT(HALT);
else {
/* allow potentially pending I/O (console output,
or other devices) to complete before taking
@ -2628,14 +2657,14 @@ for ( ;; ) {
case BISPSW:
if (opnd[0] & PSW_MBZ)
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(BISPW);
PSL = PSL | (opnd[0] & ~CC_MASK);
cc = cc | (opnd[0] & CC_MASK);
break;
case BICPSW:
if (opnd[0] & PSW_MBZ)
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(BICPSW);
PSL = PSL & ~opnd[0];
cc = cc & ~opnd[0];
break;
@ -2694,6 +2723,12 @@ for ( ;; ) {
break;
case CMPC3: case CMPC5:
#if defined(VAX_610)
if (opc == CMPC5) {
cc = cpu_emulate_exception (opnd, cc, opc, acc);
break;
}
#endif
cc = op_cmpc (opnd, opc & 4, acc);
break;
@ -3095,6 +3130,10 @@ for ( ;; ) {
/* Octaword or reserved instructions */
case PUSHAO: case MOVAO: case CLRO: case MOVO:
#if defined(VAX_610)
cc = cpu_emulate_exception (opnd, cc, opc, acc);
break;
#endif
case TSTH: case MOVH: case MNEGH: case CMPH:
case CVTBH: case CVTWH: case CVTLH:
case CVTHB: case CVTHW: case CVTHL: case CVTRHL:
@ -3112,7 +3151,7 @@ for ( ;; ) {
break;
default:
RSVD_INST_FAULT;
RSVD_INST_FAULT(opc);
break;
} /* end case op */
} /* end for */
@ -3185,6 +3224,59 @@ opnd[j++] = Read (va + 12, L_LONG, acc);
return j;
}
/* CIS instructions - invoke emulator interface
opnd[0:5] = six operands to be pushed (if PSL<fpd> = 0)
cc = condition codes
opc = opcode
If FPD is set, push old PC and PSL on stack, vector thru SCB.
If FPD is clear, push opcode, old PC, operands, new PC, and PSL
on stack, vector thru SCB.
In both cases, the exception occurs in the current mode.
*/
int32 cpu_emulate_exception (int32 *opnd, int32 cc, int32 opc, int32 acc)
{
int32 vec;
if (PSL & PSL_FPD) { /* FPD set? */
Read (SP - 1, L_BYTE, WA); /* wchk stack */
Write (SP - 8, fault_PC, L_LONG, WA); /* push old PC */
Write (SP - 4, PSL | cc, L_LONG, WA); /* push PSL */
SP = SP - 8; /* decr stk ptr */
vec = ReadLP ((SCBB + SCB_EMULFPD) & PAMASK);
sim_debug (LOG_CPU_FAULT_EMUL, &cpu_dev, "FPD OP=%s, fault_PC=%08x, PC=%08x, PSL=%08x, SP=%08x, nPC=%08x ",
opcode[opc], fault_PC, PC, PSL, SP, vec);
sim_debug_bits(LOG_CPU_FAULT_EMUL, &cpu_dev, cpu_psl_bits, PSL, PSL, 1);
}
else {
if (opc == CVTPL) /* CVTPL? .wl */
opnd[2] = (opnd[2] >= 0)? ~opnd[2]: opnd[3];
Read (SP - 1, L_BYTE, WA); /* wchk stack */
Write (SP - 48, opc, L_LONG, WA); /* push opcode */
Write (SP - 44, fault_PC, L_LONG, WA); /* push old PC */
Write (SP - 40, opnd[0], L_LONG, WA); /* push operands */
Write (SP - 36, opnd[1], L_LONG, WA);
Write (SP - 32, opnd[2], L_LONG, WA);
Write (SP - 28, opnd[3], L_LONG, WA);
Write (SP - 24, opnd[4], L_LONG, WA);
Write (SP - 20, opnd[5], L_LONG, WA);
Write (SP - 8, PC, L_LONG, WA); /* push cur PC */
Write (SP - 4, PSL | cc, L_LONG, WA); /* push PSL */
SP = SP - 48; /* decr stk ptr */
vec = ReadLP ((SCBB + SCB_EMULATE) & PAMASK);
sim_debug (LOG_CPU_FAULT_EMUL, &cpu_dev, "OP=%s, fault_PC=%08x, PC=%08x, PSL=%08x, SP=%08x, nPC=%08x ",
opcode[opc], fault_PC, PC, PSL, SP, vec);
sim_debug_bits(LOG_CPU_FAULT_EMUL, &cpu_dev, cpu_psl_bits, PSL, PSL, 1);
}
PSL = PSL & ~(PSL_TP | PSL_FPD | PSW_DV | PSW_FU | PSW_IV | PSW_T);
JUMP (vec & ~03); /* set new PC */
return 0; /* set new cc's */
}
/* Idle before the next instruction */
void cpu_idle (void)
@ -3651,6 +3743,143 @@ sim_show_idle (st, uptr, val, desc);
return SCPE_OK;
}
static struct {
int32 mask;
const char *match;
const char *desc;
} inst_groups[] = {
{0, "", ""}, /* Reserved Opcode */
{VAX_BASE, "BASE", "Base Group"}, /* Base Instruction Group */
{VAX_GFLOAT, "G-FLOAT", "G-Float"}, /* Base subgroup G-Float */
{VAX_DFLOAT, "D-FLOAT", "D-Float"}, /* Base subgroup D-Float */
{VAX_PACKED, "PACKED", "Packed-Decimal-String-Group"}, /* packed-decimal-string group */
{VAX_EXTAC, "EXTENDED", "Extended-Accuracy-Group"}, /* extended-accuracy group */
{VAX_EMONL, "EMULATED", "Emulated-Only-Group"}, /* emulated only instructions */
// {VAX_VECTR, "VECTOR", "Vector-Processing-Group"}, /* vector-processing group */
{0, NULL, NULL}
};
t_stat cpu_set_instruction_set (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
{
if (!cptr || !*cptr)
return SCPE_ARG;
while (1) {
int i;
t_bool invert = FALSE;
char gbuf[CBUFSIZE];
cptr = get_glyph (cptr, gbuf, ';');
if (!gbuf[0])
break;
if (0 == strncmp (gbuf, "NO", 2)) {
invert = TRUE;
memmove (gbuf, gbuf + 2, 1 + strlen (gbuf + 2));
}
for (i=0; inst_groups[i].match != NULL; i++)
if (MATCH_CMD (gbuf, inst_groups[i].match) == 0)
break;
if (inst_groups[i].match == NULL)
return sim_messagef (SCPE_ARG, "unknown instruction set group: %s\n", gbuf);
if (invert)
cpu_instruction_set &= ~inst_groups[i].mask;
else
cpu_instruction_set |= inst_groups[i].mask;
}
return SCPE_OK;
}
/* Used when sorting a list of opcode names */
static int _opc_name_compare (const void *pa, const void *pb)
{
const char **a = (const char **)pa;
const char **b = (const char **)pb;
return strcmp (*a, *b);
}
t_stat cpu_show_instruction_group (FILE *st, int32 groupmask)
{
int opc;
int group;
int matches;
char const *opcd_tmp[NUM_INST];
for (opc=matches=0; opc<NUM_INST; opc++) {
t_bool match = FALSE;
for (group=0; (!match) && (group<=IG_MAX_GRP); group++) {
if ((1 << group) & groupmask)
match = (DR_GETIGRP(drom[opc][0]) == group);
}
if (match)
opcd_tmp[matches++] = opcode[opc];
}
qsort ((void *)opcd_tmp, matches, sizeof (opcd_tmp[0]), _opc_name_compare);
for (opc=0; opc<matches; opc++)
fprintf (st, "%s\t%s", (0 == opc%8) ? "\n" : "", opcd_tmp[opc]);
fprintf (st, "\n");
return SCPE_OK;
}
t_stat cpu_show_instruction_set (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
{
int i;
fprintf (st, "Implementing: ");
if ((cpu_instruction_set & FULL_INSTRUCTION_SET) == FULL_INSTRUCTION_SET) {
fprintf (st, "All standard VAX instructions");
#if defined(CMPM_VAX)
fprintf (st, "and Compatibility mode");
#endif
if (sim_switches & SWMASK ('V'))
cpu_show_instruction_group (st, cpu_instruction_set);
// if (cpu_instruction_set & ~VAX_VECTR)
// fprintf (st, ",\n\tEmulating: Vector-Group");
}
else {
if ((cpu_instruction_set & VAX_FULL_BASE) == VAX_FULL_BASE) {
fprintf (st, "Base Instruction Group");
if (sim_switches & SWMASK ('V'))
cpu_show_instruction_group (st, VAX_FULL_BASE);
}
else {
if ((cpu_instruction_set & VAX_BASE) == VAX_BASE) {
fprintf (st, "Base Instruction Group");
if (!(cpu_instruction_set & VAX_GFLOAT)) {
fprintf (st, " without G-Float");
if (!(cpu_instruction_set & VAX_DFLOAT))
fprintf (st, " and D-Float");
}
else {
if (!(cpu_instruction_set & VAX_DFLOAT))
fprintf (st, " without D-Float");
}
}
else {
if (!(cpu_instruction_set & VAX_DFLOAT))
fprintf (st, " without D-Float");
}
if (sim_switches & SWMASK ('V'))
cpu_show_instruction_group (st, cpu_instruction_set);
}
for (i=4; inst_groups[i].match; i++) {
if (cpu_instruction_set & inst_groups[i].mask) {
fprintf (st, " %s", inst_groups[i].desc);
if (sim_switches & SWMASK ('V'))
cpu_show_instruction_group (st, inst_groups[i].mask);
}
}
fprintf (st, "\n%sEmulating:", (sim_switches & SWMASK ('V')) ? "" : "\t");
for (i=1; inst_groups[i].match; i++) {
if (!(cpu_instruction_set & inst_groups[i].mask)) {
fprintf (st, " %s", inst_groups[i].desc);
if (sim_switches & SWMASK ('V'))
cpu_show_instruction_group (st, inst_groups[i].mask);
}
}
}
return SCPE_OK;
}
t_stat cpu_load_bootcode (const char *filename, const unsigned char *builtin_code, size_t size, t_bool rom, t_addr offset)
{
@ -3737,5 +3966,13 @@ fprintf (st, "with each history entry.\n");
fprintf (st, "When writing history to a file (SET CPU HISTORY=n:file), 'n' specifies\n");
fprintf (st, "the buffer flush frequency. Warning: prodigious amounts of disk space\n");
fprintf (st, "may be comsumed. The maximum length for the history is %d entries.\n\n", HIST_MAX);
fprintf (st, "Different VAX systems implemented different VAX architecture instructions\n");
fprintf (st, "in hardware with other instructions possibly emulated by software in the\n");
fprintf (st, "system. The instructions that a particular simulator implements can be\n");
fprintf (st, "displayed with:\n\n");
fprintf (st, " sim> SHOW CPU INSTRUCTIONS display the instructoin groups that are\n");
fprintf (st, " implemented and emulated\n");
fprintf (st, " sim> SHOW CPU -V INSTRUCTIONS disable the list of instructions implemented\n");
fprintf (st, " and emulated\n\n");
return SCPE_OK;
}

70
VAX/vax_cpu1.c
View file

@ -109,7 +109,7 @@ int32 by;
if (rn != OP_MEM) { /* register? */
if (((uint32) pos) > 31) /* pos > 31? fault */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_bb_n);
return (R[rn] >> pos) & 1; /* get bit */
}
ea = opnd[2] + (pos >> 3); /* base byte addr */
@ -127,7 +127,7 @@ int32 by, bit;
if (rn != OP_MEM) { /* register? */
if (((uint32) pos) > 31) /* pos > 31? fault */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_bb_x);
bit = (R[rn] >> pos) & 1; /* get bit */
R[rn] = newb? (R[rn] | (1u << pos)): (R[rn] & ~(1u << pos));
return bit;
@ -162,10 +162,10 @@ int32 ba, wd1 = 0;
if (size == 0) /* size 0? field = 0 */
return 0;
if (size > 32) /* size > 32? fault */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_extv);
if (rn != OP_MEM) { /* register? */
if (((uint32) pos) > 31) /* pos > 31? fault */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_extv);
if (((pos + size) > 32) && (rn >= nSP)) /* span 2 reg, PC? */
RSVD_ADDR_FAULT; /* fault */
if (pos)
@ -206,10 +206,10 @@ int32 val, mask, ba, wd, wd1;
if (size == 0) /* size = 0? done */
return;
if (size > 32) /* size > 32? fault */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_insv);
if (rn != OP_MEM) { /* in registers? */
if (((uint32) pos) > 31) /* pos > 31? fault */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_insv);
if ((pos + size) > 32) { /* span two reg? */
if (rn >= nSP) /* if PC, fault */
RSVD_ADDR_FAULT;
@ -341,7 +341,7 @@ int32 mask, stklen, tsp, wd;
mask = Read (addr, L_WORD, RA); /* get proc mask */
if (mask & CALL_MBZ) /* test mbz */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_call);
stklen = rcnt[mask & 077] + rcnt[(mask >> 6) & 077] + (gs? 24: 20);
Read (SP - stklen, L_BYTE, WA); /* wchk stk */
if (gs) {
@ -386,7 +386,7 @@ int32 tsp = FP;
spamask = Read (tsp + 4, L_LONG, RA); /* spa/s/mask/psw */
if (spamask & PSW_MBZ) /* test mbz */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_ret);
stklen = rcnt[(spamask >> CALL_V_MASK) & 077] +
rcnt[(spamask >> (CALL_V_MASK + 6)) & 077] + ((spamask & CALL_S)? 23: 19);
Read (tsp + stklen, L_BYTE, RA); /* rchk stk end */
@ -603,11 +603,11 @@ int32 a;
int32 t;
if ((h == d) || ((h | d) & 07)) /* h, d quad align? */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_insqhi);
Read (d, L_BYTE, WA); /* wchk ent */
a = Read (h, L_LONG, WA); /* a <- (h), wchk */
if (a & 06) /* chk quad align */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_insqhi);
if (a & 01) /* busy, cc = 0001 */
return CC_C;
Write (h, a | 1, L_LONG, WA); /* get interlock */
@ -629,20 +629,20 @@ int32 a, c;
int32 t;
if ((h == d) || ((h | d) & 07)) /* h, d quad align? */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_insqti);
Read (d, L_BYTE, WA); /* wchk ent */
a = Read (h, L_LONG, WA); /* a <- (h), wchk */
if (a == 0) /* if empty, ins hd */
return op_insqhi (opnd, acc);
if (a & 06) /* chk quad align */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_insqti);
if (a & 01) /* busy, cc = 0001 */
return CC_C;
Write (h, a | 1, L_LONG, WA); /* acquire interlock */
c = Read (h + 4, L_LONG, RA) + h; /* c <- (h+4) + h */
if (c & 07) { /* c quad aligned? */
Write (h, a, L_LONG, WA); /* release interlock */
RSVD_OPND_FAULT; /* fault */
RSVD_OPND_FAULT(op_insqti); /* fault */
}
if (Test (c, WA, &t) < 0) /* wtst c, rls if err */
Write (h, a, L_LONG, WA);
@ -687,15 +687,15 @@ int32 ar, a, b;
int32 t;
if (h & 07) /* h quad aligned? */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_remqhi);
if (opnd[1] == OP_MEM) { /* mem destination? */
if (h == opnd[2]) /* hdr = dst? */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_remqhi);
Read (opnd[2], L_LONG, WA); /* wchk dst */
}
ar = Read (h, L_LONG, WA); /* ar <- (h) */
if (ar & 06) /* a quad aligned? */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_remqhi);
if (ar & 01) /* busy, cc = 0011 */
return CC_V | CC_C;
a = ar + h; /* abs addr of a */
@ -706,7 +706,7 @@ if (ar) { /* queue not empty? */
b = Read (a, L_LONG, RA) + a; /* b <- (a)+a, flt ok */
if (b & 07) { /* b quad aligned? */
Write (h, ar, L_LONG, WA); /* release interlock */
RSVD_OPND_FAULT; /* fault */
RSVD_OPND_FAULT(op_remqhi); /* fault */
}
if (Test (b, WA, &t) < 0) /* write test b */
Write (h, ar, L_LONG, WA); /* release if err */
@ -728,15 +728,15 @@ int32 ar, b, c;
int32 t;
if (h & 07) /* h quad aligned? */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_remqti);
if (opnd[1] == OP_MEM) { /* mem destination? */
if (h == opnd[2]) /* hdr = dst? */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_remqti);
Read (opnd[2], L_LONG, WA); /* wchk dst */
}
ar = Read (h, L_LONG, WA); /* a <- (h) */
if (ar & 06) /* a quad aligned? */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_remqti);
if (ar & 01) /* busy, cc = 0011 */
return CC_V | CC_C;
if (ar) { /* queue not empty */
@ -748,7 +748,7 @@ if (ar) { /* queue not empty */
}
if (c & 07) { /* c quad aligned? */
Write (h, ar, L_LONG, WA); /* release interlock */
RSVD_OPND_FAULT; /* fault */
RSVD_OPND_FAULT(op_remqti); /* fault */
}
c = c + h; /* abs addr of c */
if (Test (c + 4, RA, &t) < 0) /* read test c+4 */
@ -756,7 +756,7 @@ if (ar) { /* queue not empty */
b = Read (c + 4, L_LONG, RA) + c; /* b <- (c+4)+c, flt ok */
if (b & 07) { /* b quad aligned? */
Write (h, ar, L_LONG, WA); /* release interlock */
RSVD_OPND_FAULT; /* fault */
RSVD_OPND_FAULT(op_remqti); /* fault */
}
if (Test (b, WA, &t) < 0) /* write test b */
Write (h, ar, L_LONG, WA); /* release if error */
@ -919,7 +919,7 @@ switch (R[5] & MVC_M_STATE) { /* case on state */
break;
default: /* bad state */
RSVD_OPND_FAULT; /* you lose */
RSVD_OPND_FAULT(op_movc); /* you lose */
}
PSL = PSL & ~PSL_FPD; /* clear FPD */
@ -1131,8 +1131,9 @@ if (ei > 0) { /* if int, new IPL */
else
PSL = newpsl | /* exc, old IPL/1F */
((newpc & 1)? PSL_IPL1F: (oldpsl & PSL_IPL)) | (oldcur << PSL_V_PRV);
sim_debug (LOG_CPU_I, &cpu_dev, "PC=%08x, PSL=%08x, SP=%08x, VEC=%08x, nPSL=%08x, nSP=%08x\n",
sim_debug (LOG_CPU_I, &cpu_dev, "PC=%08x, PSL=%08x, SP=%08x, VEC=%08x, nPSL=%08x, nSP=%08x ",
PC, oldpsl, oldsp, vec, PSL, SP);
sim_debug_bits(LOG_CPU_I, &cpu_dev, cpu_psl_bits, oldpsl, PSL, 1);
acc = ACC_MASK (KERN); /* new mode is kernel */
Write (SP - 4, oldpsl, L_LONG, WA); /* push old PSL */
Write (SP - 8, PC, L_LONG, WA); /* push old PC */
@ -1202,9 +1203,9 @@ Rule SRM formulation Comment
*/
#define REI_RSVD_FAULT(desc) do { \
sim_debug (LOG_CPU_FAULT_RSVD, &cpu_dev, "PC=%08x, PSL=%08x, SP=%08x, nPC=%08x, nPSL=%08x, nSP=%08x - %s\n",\
sim_debug (LOG_CPU_FAULT_RSVD, &cpu_dev, "REI Operand: PC=%08x, PSL=%08x, SP=%08x, nPC=%08x, nPSL=%08x, nSP=%08x - %s\n",\
PC, PSL, SP - 8, newpc, newpsl, ((newpsl & IS)? IS: STK[newcur]), desc); \
RSVD_OPND_FAULT; } while (0)
RSVD_OPND_FAULT(REI); } while (0)
int32 op_rei (int32 acc)
{
@ -1242,8 +1243,9 @@ if (PSL & PSL_IS) /* save stack */
IS = SP;
else
STK[oldcur] = SP;
sim_debug (LOG_CPU_R, &cpu_dev, "PC=%08x, PSL=%08x, SP=%08x, nPC=%08x, nPSL=%08x, nSP=%08x\n",
sim_debug (LOG_CPU_R, &cpu_dev, "PC=%08x, PSL=%08x, SP=%08x, nPC=%08x, nPSL=%08x, nSP=%08x ",
PC, PSL, SP - 8, newpc, newpsl, ((newpsl & IS)? IS: STK[newcur]));
sim_debug_bits(LOG_CPU_R, &cpu_dev, cpu_psl_bits, PSL, newpsl, 1);
PSL = (PSL & PSL_TP) | (newpsl & ~CC_MASK); /* set PSL */
if (PSL & PSL_IS) /* set new stack */
SP = IS;
@ -1265,7 +1267,7 @@ void op_ldpctx (int32 acc)
uint32 newpc, newpsl, pcbpa, t;
if (PSL & PSL_CUR) /* must be kernel */
RSVD_INST_FAULT;
RSVD_INST_FAULT(LDPCTX);
pcbpa = PCBB & PAMASK; /* phys address */
KSP = ReadLP (pcbpa); /* restore stk ptrs */
ESP = ReadLP (pcbpa + 4);
@ -1327,7 +1329,7 @@ void op_svpctx (int32 acc)
int32 savpc, savpsl, pcbpa;
if (PSL & PSL_CUR) /* must be kernel */
RSVD_INST_FAULT;
RSVD_INST_FAULT(SVPCTX);
savpc = Read (SP, L_LONG, RA); /* pop PC, PSL */
savpsl = Read (SP + 4, L_LONG, RA);
sim_debug (LOG_CPU_P, &cpu_dev, ">>SVP: PC=%08x, PSL=%08x, SP=%08x, oPC=%08x, oPSL=%08x\n",
@ -1429,9 +1431,9 @@ uint32 prn = (uint32)opnd[1];
int32 cc;
if (PSL & PSL_CUR) /* must be kernel */
RSVD_INST_FAULT;
RSVD_INST_FAULT(MTPR);
if (prn > MT_MAX) /* reg# > max? fault */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_mtpr);
CC_IIZZ_L (val); /* set cc's */
switch (prn) { /* case on reg # */
@ -1560,9 +1562,9 @@ uint32 prn = (uint32)opnd[0];
int32 val;
if (PSL & PSL_CUR) /* must be kernel */
RSVD_INST_FAULT;
RSVD_INST_FAULT(MFPR);
if (prn > MT_MAX) /* reg# > max? fault */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_mtpr);
switch (prn) { /* case on reg# */
case MT_KSP: /* KSP */
@ -1633,7 +1635,7 @@ switch (prn) { /* case on reg# */
case MT_TBIA:
case MT_TBIS:
case MT_TBCHK:
RSVD_OPND_FAULT; /* write only */
RSVD_OPND_FAULT(op_mfpr); /* write only */
default: /* others */
val = ReadIPR (prn); /* read from SSC */

86
VAX/vax_defs.h
View file

@ -79,24 +79,47 @@
#define ABORT_TNV (-SCB_TNV) /* transl not vaid */
#define ABORT(x) longjmp (save_env, (x)) /* abort */
extern jmp_buf save_env;
#define RSVD_INST_FAULT ABORT (ABORT_RESIN)
#define RSVD_INST_FAULT(opc) do { \
char op_num[20]; \
char const *opcd = opcode[opc]; \
\
if (sim_deb && !opcd) { \
opcd = op_num; \
sprintf (op_num, "Opcode 0x%X", opc); \
sim_debug (LOG_CPU_FAULT_RSVD, &cpu_dev, "%s fault_PC=%08x, PSL=%08x, SP=%08x, PC=%08x\n", \
opcd, fault_PC, PSL, SP, PC); \
} \
ABORT (ABORT_RESIN); } while (0)
#define RSVD_ADDR_FAULT ABORT (ABORT_RESAD)
#define RSVD_OPND_FAULT ABORT (ABORT_RESOP)
#define RSVD_OPND_FAULT(opc) do { \
sim_debug (LOG_CPU_FAULT_RSVD, &cpu_dev, #opc " fault_PC=%08x, PSL=%08x, SP=%08x, PC=%08x\n", \
fault_PC, PSL, SP, PC); \
ABORT (ABORT_RESOP); } while (0)
#define FLT_OVFL_FAULT p1 = FLT_OVRFLO, ABORT (ABORT_ARITH)
#define FLT_DZRO_FAULT p1 = FLT_DIVZRO, ABORT (ABORT_ARITH)
#define FLT_UNFL_FAULT p1 = FLT_UNDFLO, ABORT (ABORT_ARITH)
#define CMODE_FAULT(cd) p1 = (cd), ABORT (ABORT_CMODE)
#define MACH_CHECK(cd) p1 = (cd), ABORT (ABORT_MCHK)
#define CMODE_FAULT(cd) do { \
sim_debug (LOG_CPU_FAULT_CMODE, &cpu_dev, #cd " fault_PC=%08x, PSL=%08x, SP=%08x, PC=%08x\n", \
fault_PC, PSL, SP, PC); \
p1 = (cd); \
ABORT (ABORT_CMODE); } while (0)
#define MACH_CHECK(cd) do { \
sim_debug (LOG_CPU_FAULT_MCHK, &cpu_dev, #cd " fault_PC=%08x, PSL=%08x, SP=%08x, PC=%08x\n", \
fault_PC, PSL, SP, PC); \
p1 = (cd); \
ABORT (ABORT_MCHK); } while (0)
/* Logging */
#define LOG_CPU_I 0x001 /* intexc */
#define LOG_CPU_R 0x002 /* REI */
#define LOG_CPU_P 0x004 /* process context */
#define LOG_CPU_FAULT_RSVD 0x008 /* reserved faults */
#define LOG_CPU_FAULT_FLT 0x010 /* floating faults*/
#define LOG_CPU_FAULT_CMODE 0x020 /* cmode faults */
#define LOG_CPU_FAULT_MCHK 0x040 /* machine check faults */
#define LOG_CPU_A 0x004 /* Abort */
#define LOG_CPU_P 0x008 /* process context */
#define LOG_CPU_FAULT_RSVD 0x010 /* reserved faults */
#define LOG_CPU_FAULT_FLT 0x020 /* floating faults*/
#define LOG_CPU_FAULT_CMODE 0x040 /* cmode faults */
#define LOG_CPU_FAULT_MCHK 0x080 /* machine check faults */
#define LOG_CPU_FAULT_EMUL 0x100 /* emulated instruction fault */
/* Recovery queue */
@ -425,6 +448,37 @@ extern jmp_buf save_env;
#define RB_SP (14 << DR_V_RESMASK) /* @SP */
#define DR_GETRES(x) (((x) >> DR_V_RESMASK) & DR_M_RESMASK)
/* Extra bits in the opcode flag word of the Decode ROM array
to identify instruction group */
#define DR_V_IGMASK 12
#define DR_M_IGMASK 0x0007
#define IG_RSVD (0 << DR_V_IGMASK) /* Reserved Opcode */
#define IG_BASE (1 << DR_V_IGMASK) /* Base Instruction Group */
#define IG_BSGFL (2 << DR_V_IGMASK) /* Base subgroup G-Float */
#define IG_BSDFL (3 << DR_V_IGMASK) /* Base subgroup D-Float */
#define IG_PACKD (4 << DR_V_IGMASK) /* packed-decimal-string group */
#define IG_EXTAC (5 << DR_V_IGMASK) /* extended-accuracy group */
#define IG_EMONL (6 << DR_V_IGMASK) /* emulated-only group */
#define IG_VECTR (7 << DR_V_IGMASK) /* vector-processing group */
#define IG_MAX_GRP 7 /* Maximum Instruction groups */
#define DR_GETIGRP(x) (((x) >> DR_V_IGMASK) & DR_M_IGMASK)
#define VAX_FULL_BASE ((1 << DR_GETIGRP(IG_BASE)) | \
(1 << DR_GETIGRP(IG_BSGFL)) | \
(1 << DR_GETIGRP(IG_BSDFL)))
#define VAX_BASE (1 << DR_GETIGRP(IG_BASE))
#define VAX_GFLOAT (1 << DR_GETIGRP(IG_BSGFL))
#define VAX_DFLOAT (1 << DR_GETIGRP(IG_BSDFL))
#define VAX_PACKED (1 << DR_GETIGRP(IG_PACKD))
#define VAX_EXTAC (1 << DR_GETIGRP(IG_EXTAC))
#define VAX_EMONL (1 << DR_GETIGRP(IG_EMONL))
#define VAX_VECTR (1 << DR_GETIGRP(IG_VECTR))
#define FULL_INSTRUCTION_SET (VAX_BASE | \
(1 << DR_GETIGRP(IG_PACKD)) | \
(1 << DR_GETIGRP(IG_EXTAC)) | \
(1 << DR_GETIGRP(IG_EMONL)))
/* Decode ROM: specifier entry */
#define DR_ACMASK 0x300 /* type */
@ -785,6 +839,9 @@ enum opcodes {
#define VAX_IDLE_ELN 0x40 /* VAXELN */
extern uint32 cpu_idle_mask; /* idle mask */
extern int32 extra_bytes; /* bytes referenced by current string instruction */
extern BITFIELD cpu_psl_bits[];
extern char const * const opcode[];
extern const uint16 drom[NUM_INST][MAX_SPEC + 1];
void cpu_idle (void);
/* Instruction History */
@ -941,9 +998,20 @@ extern void rom_wr_B (int32 pa, int32 val);
#else /* VAX 3900 */
#include "vaxmod_defs.h"
#endif
#ifndef CPU_INSTRUCTION_SET
#if defined (FULL_VAX)
#define CPU_INSTRUCTION_SET FULL_INSTRUCTION_SET
#else
#define CPU_INSTRUCTION_SET VAX_FULL_BASE
#endif
#endif
#ifndef CPU_MODEL_MODIFIERS
#define CPU_MODEL_MODIFIERS /* No model specific CPU modifiers */
#endif
#ifndef CPU_INST_MODIFIERS
#define CPU_INST_MODIFIERS { MTAB_XTD|MTAB_VDV, 0, "INSTRUCTIONS", "INSTRUCTIONS={F-FLOAT|D-FLOAT}", \
&cpu_set_instruction_set, &cpu_show_instruction_set, NULL, "Set/Show the CPU Instruction Set" },
#endif
#ifndef IDX_IMM_TEST
#define IDX_IMM_TEST RSVD_ADDR_FAULT
#endif

28
VAX/vax_fpa.c
View file

@ -196,12 +196,12 @@ t_uint64 n1, n2;
if ((h1 & FD_EXP) == 0) {
if (h1 & FPSIGN)
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_cmpfd);
h1 = l1 = 0;
}
if ((h2 & FD_EXP) == 0) {
if (h2 & FPSIGN)
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_cmpfd);
h2 = l2 = 0;
}
if ((h1 ^ h2) & FPSIGN)
@ -219,12 +219,12 @@ t_uint64 n1, n2;
if ((h1 & G_EXP) == 0) {
if (h1 & FPSIGN)
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_cmpg);
h1 = l1 = 0;
}
if ((h2 & G_EXP) == 0) {
if (h2 & FPSIGN)
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_cmpg);
h2 = l2 = 0;
}
if ((h1 ^ h2) & FPSIGN)
@ -508,7 +508,7 @@ r->sign = hi & FPSIGN; /* get sign */
r->exp = FD_GETEXP (hi); /* get exponent */
if (r->exp == 0) { /* exp = 0? */
if (r->sign) /* if -, rsvd op */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(unpackf);
r->frac = 0; /* else 0 */
return;
}
@ -523,7 +523,7 @@ r->sign = hi & FPSIGN; /* get sign */
r->exp = FD_GETEXP (hi); /* get exponent */
if (r->exp == 0) { /* exp = 0? */
if (r->sign) /* if -, rsvd op */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(unpackd);
r->frac = 0; /* else 0 */
return;
}
@ -538,7 +538,7 @@ r->sign = hi & FPSIGN; /* get sign */
r->exp = G_GETEXP (hi); /* get exponent */
if (r->exp == 0) { /* exp = 0? */
if (r->sign) /* if -, rsvd op */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(unpackg);
r->frac = 0; /* else 0 */
return;
}
@ -1327,7 +1327,7 @@ int32 op_movfd (int32 val)
if (val & FD_EXP)
return val;
if (val & FPSIGN)
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_movfd);
return 0;
}
@ -1336,7 +1336,7 @@ int32 op_mnegfd (int32 val)
if (val & FD_EXP)
return (val ^ FPSIGN);
if (val & FPSIGN)
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_mnegfd);
return 0;
}
@ -1345,7 +1345,7 @@ int32 op_movg (int32 val)
if (val & G_EXP)
return val;
if (val & FPSIGN)
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_movg);
return 0;
}
@ -1354,7 +1354,7 @@ int32 op_mnegg (int32 val)
if (val & G_EXP)
return (val ^ FPSIGN);
if (val & FPSIGN)
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_mnegg);
return 0;
}
@ -1504,7 +1504,7 @@ int32 ptr = opnd[2];
int32 i, wd, res;
if (deg > 31) /* degree > 31? fault */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_polyf);
unpackf (opnd[0], &a); /* unpack arg */
wd = Read (ptr, L_LONG, RD); /* get C0 */
ptr = ptr + 4;
@ -1533,7 +1533,7 @@ int32 ptr = opnd[3];
int32 i, wd, wd1, res, resh;
if (deg > 31) /* degree > 31? fault */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_polyd);
unpackd (opnd[0], opnd[1], &a); /* unpack arg */
wd = Read (ptr, L_LONG, RD); /* get C0 */
wd1 = Read (ptr + 4, L_LONG, RD);
@ -1567,7 +1567,7 @@ int32 ptr = opnd[3];
int32 i, wd, wd1, res, resh;
if (deg > 31) /* degree > 31? fault */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_polyg);
unpackg (opnd[0], opnd[1], &a); /* unpack arg */
wd = Read (ptr, L_LONG, RD); /* get C0 */
wd1 = Read (ptr + 4, L_LONG, RD);

14
VAX/vax_octa.c
View file

@ -433,7 +433,7 @@ switch (opc) {
break;
default:
RSVD_INST_FAULT;
RSVD_INST_FAULT(opc);
}
return cc;
@ -449,7 +449,7 @@ int32 op_tsth (int32 val)
if (val & H_EXP) /* non-zero? */
return val;
if (val & FPSIGN) /* reserved? */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_tsth);
return 0; /* clean 0 */
}
@ -620,7 +620,7 @@ int32 ptr = opnd[5];
int32 i, wd[4], res[4];
if (deg > 31) /* deg > 31? fault */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(op_polyh);
h_unpackh (&opnd[0], &a); /* unpack arg */
wd[0] = Read (ptr, L_LONG, RD); /* get C0 */
wd[1] = Read (ptr + 4, L_LONG, RD);
@ -1013,7 +1013,7 @@ r->exp = FD_GETEXP (hi); /* get exponent */
r->frac.f0 = r->frac.f1 = 0; /* low bits 0 */
if (r->exp == 0) { /* exp = 0? */
if (r->sign) /* if -, rsvd op */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(h_unpackfd);
r->frac.f2 = r->frac.f3 = 0; /* else 0 */
return;
}
@ -1030,7 +1030,7 @@ r->exp = G_GETEXP (hi); /* get exponent */
r->frac.f0 = r->frac.f1 = 0; /* low bits 0 */
if (r->exp == 0) { /* exp = 0? */
if (r->sign) /* if -, rsvd op */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(h_unpackg);
r->frac.f2 = r->frac.f3 = 0; /* else 0 */
return;
}
@ -1046,7 +1046,7 @@ r->sign = hflt[0] & FPSIGN; /* get sign */
r->exp = H_GETEXP (hflt[0]); /* get exponent */
if (r->exp == 0) { /* exp = 0? */
if (r->sign) /* if -, rsvd op */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(h_unpackh);
r->frac.f0 = r->frac.f1 = 0; /* else 0 */
r->frac.f2 = r->frac.f3 = 0;
return;
@ -1261,7 +1261,7 @@ return;
int32 op_octa (int32 *opnd, int32 cc, int32 opc, int32 acc, int32 spec, int32 va, InstHistory *hst)
{
RSVD_INST_FAULT;
RSVD_INST_FAULT(opc);
return cc;
}

1037
VAX/vax_sys.c
View file

File diff suppressed because it is too large Load diff

34
VAX/vax_syscm.c
View file

@ -72,7 +72,7 @@ static const int32 masks[] = {
0177000
};
static const char *opcode[] = {
static const char *cm_opcode[] = {
"HALT","WAIT","RTI","BPT",
"IOT","RESET","RTT","MFPT",
"JMP","RTS","SPL",
@ -303,55 +303,55 @@ for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
switch (j) { /* case on class */
case I_V_NPN: case I_V_CCC: case I_V_CCS: /* no operands */
fprintf (of, "%s", opcode[i]);
fprintf (of, "%s", cm_opcode[i]);
break;
case I_V_REG: /* reg */
fprintf (of, "%s %-s", opcode[i], rname[dstr]);
fprintf (of, "%s %-s", cm_opcode[i], rname[dstr]);
break;
case I_V_SOP: /* sop */
fprintf (of, "%s ", opcode[i]);
fprintf (of, "%s ", cm_opcode[i]);
wd1 = fprint_spec (of, addr, dstm, val[1]);
break;
case I_V_3B: /* 3b */
fprintf (of, "%s %-X", opcode[i], dstr);
fprintf (of, "%s %-X", cm_opcode[i], dstr);
break;
case I_V_6B: /* 6b */
fprintf (of, "%s %-X", opcode[i], dstm);
fprintf (of, "%s %-X", cm_opcode[i], dstm);
break;
case I_V_BR: /* cond branch */
fprintf (of, "%s ", opcode[i]);
fprintf (of, "%s ", cm_opcode[i]);
brdisp = (l8b + l8b + ((l8b & 0200)? 0177002: 2)) & 0177777;
fprintf (of, "%-X", (int32)((addr + brdisp) & 0177777));
break;
case I_V_8B: /* 8b */
fprintf (of, "%s %-X", opcode[i], l8b);
fprintf (of, "%s %-X", cm_opcode[i], l8b);
break;
case I_V_SOB: /* sob */
fprintf (of, "%s %s,", opcode[i], rname[srcr]);
fprintf (of, "%s %s,", cm_opcode[i], rname[srcr]);
brdisp = (dstm * 2) - 2;
fprintf (of, "%-X", (int32)((addr - brdisp) & 0177777));
break;
case I_V_RSOP: /* rsop */
fprintf (of, "%s %s,", opcode[i], rname[srcr]);
fprintf (of, "%s %s,", cm_opcode[i], rname[srcr]);
wd1 = fprint_spec (of, addr, dstm, val[1]);
break;
case I_V_SOPR: /* sopr */
fprintf (of, "%s ", opcode[i]);
fprintf (of, "%s ", cm_opcode[i]);
wd1 = fprint_spec (of, addr, dstm, val[1]);
fprintf (of, ",%s", rname[srcr]);
break;
case I_V_DOP: /* dop */
fprintf (of, "%s ", opcode[i]);
fprintf (of, "%s ", cm_opcode[i]);
wd1 = fprint_spec (of, addr, srcm, val[1]);
fprintf (of, ",");
wd1 += fprint_spec (of, addr - wd1 - wd1, dstm,
@ -575,8 +575,8 @@ if (!(sw & SWMASK ('P')) || (ad32 & 1) || (ad32 > WMASK))
cptr = get_glyph (cptr, gbuf, 0); /* get opcode */
n1 = n2 = pflag = 0;
for (i = 0; (opcode[i] != NULL) && (strcmp (opcode[i], gbuf) != 0) ; i++) ;
if (opcode[i] == NULL)
for (i = 0; (cm_opcode[i] != NULL) && (strcmp (cm_opcode[i], gbuf) != 0) ; i++) ;
if (cm_opcode[i] == NULL)
return SCPE_ARG;
val[0] = opc_val[i] & 0177777; /* get value */
j = (opc_val[i] >> I_V_CL) & I_M_CL; /* get class */
@ -666,10 +666,10 @@ switch (j) { /* case on class */
case I_V_CCC: case I_V_CCS: /* cond code oper */
for (cptr = get_glyph (cptr, gbuf, 0); gbuf[0] != 0;
cptr = get_glyph (cptr, gbuf, 0)) {
for (i = 0; (opcode[i] != NULL) &&
(strcmp (opcode[i], gbuf) != 0) ; i++) ;
for (i = 0; (cm_opcode[i] != NULL) &&
(strcmp (cm_opcode[i], gbuf) != 0) ; i++) ;
if ((((opc_val[i] >> I_V_CL) & I_M_CL) != j) ||
(opcode[i] == NULL))
(cm_opcode[i] == NULL))
return SCPE_ARG;
val[0] = val[0] | (opc_val[i] & 0177777);
}

2
VAX/vax_sysdev.c
View file

@ -979,7 +979,7 @@ switch (rg) {
case MT_SID:
case MT_CONPC:
case MT_CONPSL: /* halt reg */
RSVD_OPND_FAULT;
RSVD_OPND_FAULT(WriteIPR);
default:
ssc_bto = ssc_bto | SSCBTO_BTO; /* set BTO */

4
VAX/vaxmod_defs.h
View file

@ -138,7 +138,7 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc
{ MTAB_XTD|MTAB_VDV, 0, "AUTOBOOT", "AUTOBOOT", \
&sysd_set_halt, &sysd_show_halt, NULL, "Enable autoboot (Disable Halt)" }, \
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 1, "NOAUTOBOOT", "NOAUTOBOOT", \
&sysd_set_halt, &sysd_show_halt, NULL, "Disable autoboot (Enable Halt)" }
&sysd_set_halt, &sysd_show_halt, NULL, "Disable autoboot (Enable Halt)" },
/* Cache diagnostic space */
@ -247,7 +247,7 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc
#define LP_MBZ84_TEST(r)
#define LP_MBZ92_TEST(r)
#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST)
/* Qbus I/O modes */