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sigma: Fix breakpoint state restore

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Ken Rector 2022-07-12 13:54:58 -07:00 • committed by Mark Pizzolato
parent 2a69f1bdfa
commit 677e89bab0
2 changed files with 4 additions and 0 deletions
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1
sigma/sigma_bugs.txt
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@ -120,6 +120,7 @@
114: RAD: device address must include unit identifier everywhere, for interrupt generation. 114: RAD: device address must include unit identifier everywhere, for interrupt generation.
115. MT: error handling not consistent. 115. MT: error handling not consistent.
116: IO: dangling else in write direct mode 1 code causes incorrect behavior. 116: IO: dangling else in write direct mode 1 code causes incorrect behavior.
117: CPU: sim_interval is decremented before breakpoint test, which is incorrect.
Diagnostic Notes Diagnostic Notes

3
sigma/sigma_cpu.c
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@ -25,6 +25,8 @@
cpu central processor cpu central processor
12-Jul-22 RMS Fix incorrect decrement on breakpoint (Ken Rector)
The system state for the Sigma CPU is as follows: The system state for the Sigma CPU is as follows:
RF[0:15][0:31]<0:31> register blocks RF[0:15][0:31]<0:31> register blocks
@ -476,6 +478,7 @@ while (reason == 0) { /* loop until stop */
if (sim_brk_summ && if (sim_brk_summ &&
sim_brk_test (PC, SWMASK ('E'))) { /* breakpoint? */ sim_brk_test (PC, SWMASK ('E'))) { /* breakpoint? */
reason = STOP_IBKPT; /* stop simulation */ reason = STOP_IBKPT; /* stop simulation */
sim_interval++; /* undo decrement */
break; break;
} }
if (PSW_QRX9 && (PC & PSW1_XA)) /* S9 real ext && ext? */ if (PSW_QRX9 && (PC & PSW1_XA)) /* S9 real ext && ext? */