3b2: Gracefully handle clock reset
Clock reset was not being handled gracefully at all, leading some diagnostic tests not to pass, or not to pass consistently. This change will "kick" the system clock whenever the timer divider is reset, so the new divider is picked up immediately.
This commit is contained in:
Seth Morabito
Mark Pizzolato
parent
b23ebbe312
commit
690c30b6f4
8 changed files with 82 additions and 59 deletions
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@ -48,6 +48,9 @@ volatile uint32 abort_context;
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/* Pointer to the last decoded instruction */
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instr *cpu_instr;
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/* The instruction to use if there is no history storage */
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instr inst;
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/* Circular buffer of instructions */
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instr *INST = NULL;
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uint32 cpu_hist_size = 0;
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@ -1311,6 +1314,10 @@ t_bool cpu_on_interrupt(uint8 ipl)
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uint32 new_pcbp;
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uint16 id = ipl; /* TODO: Does this need to be uint16? */
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sim_debug(IRQ_MSG, &cpu_dev,
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"[%08x] [cpu_on_interrupt] ipl=%d\n",
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R[NUM_PC], ipl);
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/*
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* "If a nonmaskable interrupt request is received, an auto-vector
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* interrupt acknowledge cycle is performed (as if an autovector
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@ -1368,8 +1375,6 @@ t_stat sim_instr(void)
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uint32 width, offset;
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t_uint64 mask;
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instr inst;
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operand *src1, *src2, *src3, *dst;
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stop_reason = 0;
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@ -295,8 +295,10 @@ noret __libc_longjmp (jmp_buf buf, int val);
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#define TMR_CLK 0 /* The clock responsible for IPL 15 interrupts */
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#define TMR_TOD 1 /* The Time-of-Day clock */
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#define TPS_CLK 100
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#define TPS_TOD 10
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#define CLK_MIN_TICKS 500 /* No fewer than 500 sim steps between ticks */
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#define TPS_CLK 100 /* 100 ticks per second */
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#define TPS_TOD 10 /* 10 ticks per second */
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/* TIMING SECTION */
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@ -304,7 +306,7 @@ noret __libc_longjmp (jmp_buf buf, int val);
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/* Calculate delays (in simulator steps) for times */
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/* System clock runs at 10MHz; 100ns period. */
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#define US_PER_INST 0.9
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#define US_PER_INST 1.0
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#define INST_PER_MS (1000.0 / US_PER_INST)
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22
3B2/3b2_iu.c
22
3B2/3b2_iu.c
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@ -250,28 +250,6 @@ void iu_txrdy_b_irq() {
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}
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}
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t_stat iu_reset()
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{
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t_stat result;
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result = tti_a_reset(&tti_a_dev);
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if (result != SCPE_OK) {
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return result;
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}
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result = tti_b_reset(&tti_b_dev);
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if (result != SCPE_OK) {
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return result;
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}
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result = iu_timer_reset(&iu_timer_dev);
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if (result != SCPE_OK) {
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return result;
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}
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return SCPE_OK;
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}
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t_stat tti_a_reset(DEVICE *dptr)
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{
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memset(&iu_state, 0, sizeof(IU_STATE));
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@ -180,9 +180,6 @@ typedef struct iu_timer_state {
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extern IU_PORT iu_port_a;
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extern IU_PORT iu_port_b;
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/* Global reset */
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extern t_stat iu_reset();
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/* Function prototypes */
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t_stat tti_a_reset(DEVICE *dptr);
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t_stat tti_b_reset(DEVICE *dptr);
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@ -76,6 +76,18 @@ const char *sim_stop_messages[] = {
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"Unimplemented MMU Feature"
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};
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void full_reset()
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{
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cpu_reset(&cpu_dev);
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tti_a_reset(&tti_a_dev);
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tti_b_reset(&tti_b_dev);
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iu_timer_reset(&iu_timer_dev);
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timer_reset(&timer_dev);
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if_reset(&if_dev);
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id_reset(&id_dev);
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csr_reset(&csr_dev);
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}
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t_stat sim_load(FILE *fileref, CONST char *cptr, CONST char *fnam, int flag)
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{
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int32 i;
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@ -39,6 +39,7 @@ extern REG *sim_PC;
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extern int32 sim_emax;
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extern DEVICE *sim_devices[];
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void full_reset();
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t_stat sim_load (FILE *fileref, CONST char *cptr, CONST char *fnam, int flag);
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t_stat parse_sym (CONST char *cptr, t_addr addr, UNIT *uptr, t_value *val,
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int32 sw);
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@ -51,6 +51,8 @@ DEBTAB sys_deb_tab[] = {
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{ NULL, 0 }
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};
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struct timer_ctr TIMERS[3];
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uint32 *NVRAM = NULL;
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extern DEVICE cpu_dev;
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@ -151,8 +153,7 @@ void csr_write(uint32 pa, uint32 val, size_t size)
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csr_data &= ~CSRPARE;
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break;
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case 0x0b: /* Set System Reset Request */
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iu_reset();
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cpu_reset(&cpu_dev);
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full_reset();
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cpu_boot(0, &cpu_dev);
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break;
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case 0x0f: /* Clear Memory Alignment Fault */
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@ -171,9 +172,32 @@ void csr_write(uint32 pa, uint32 val, size_t size)
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csr_data &= ~CSRFLOP;
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break;
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case 0x23: /* Set Inhibit Timers */
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sim_debug(WRITE_MSG, &csr_dev,
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"[%08x] SET INHIBIT TIMERS\n", R[NUM_PC]);
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csr_data |= CSRITIM;
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break;
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case 0x27: /* Clear Inhibit Timers */
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sim_debug(WRITE_MSG, &csr_dev,
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"[%08x] CLEAR INHIBIT TIMERS\n", R[NUM_PC]);
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/* A side effect of clearing the timer inhibit bit is to cause
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* a simulated "tick" of any active timers. This is a hack to
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* make diagnostics pass. This is not 100% accurate, but it
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* makes SVR3 and DGMON tests happy.
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*/
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if (TIMERS[0].gate && TIMERS[0].enabled) {
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TIMERS[0].val = TIMERS[0].divider - 1;
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}
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if (TIMERS[1].gate && TIMERS[1].enabled) {
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TIMERS[1].val = TIMERS[1].divider - 1;
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}
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if (TIMERS[2].gate && TIMERS[2].enabled) {
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TIMERS[2].val = TIMERS[2].divider - 1;
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}
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csr_data &= ~CSRITIM;
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break;
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case 0x2b: /* Set Inhibit Faults */
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@ -368,8 +392,6 @@ void nvram_write(uint32 pa, uint32 val, size_t size)
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*
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*/
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struct timer_ctr TIMERS[3];
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/*
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* The three timers, (A, B, C) run at different
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* programmatially controlled frequencies, so each must be
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@ -383,6 +405,8 @@ UNIT timer_unit[] = {
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{ NULL }
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};
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UNIT *timer_clk_unit = &timer_unit[1];
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REG timer_reg[] = {
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{ HRDATAD(DIVA, TIMERS[0].divider, 16, "Divider A") },
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{ HRDATAD(STA, TIMERS[0].mode, 16, "Mode A") },
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@ -401,27 +425,11 @@ DEVICE timer_dev = {
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DEV_DEBUG, 0, sys_deb_tab
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};
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#define TIMER_STP_US 10 /* 10 us delay per timer step */
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#define TIMER_STP_US 10 /* 10 us delay per timer step */
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#define tmrnum u3
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#define tmr up7
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#define DECR_STEPS 400
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/*
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* This is a hack to make diagnostics pass. If read immediately after
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* being set, a counter should always return the initial value. If a
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* certain number of steps have passed, it should have decremented a
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* little bit, so we return a value one less than the initial value.
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* This is not 100% accurate, but it makes SVR3 and DGMON tests happy.
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*/
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static SIM_INLINE uint16 timer_current_val(struct timer_ctr *ctr)
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{
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if ((sim_gtime() - ctr->stime) > DECR_STEPS) {
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return ctr->divider - 1;
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} else {
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return ctr->divider;
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}
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}
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t_stat timer_reset(DEVICE *dptr) {
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int32 i, t;
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@ -437,8 +445,8 @@ t_stat timer_reset(DEVICE *dptr) {
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TIMERS[1].gate = 1;
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if (!sim_is_running) {
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t = sim_rtcn_init_unit(&timer_unit[1], TPS_CLK, TMR_CLK);
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sim_activate_after(&timer_unit[1], 1000000 / t);
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t = sim_rtcn_init_unit(timer_clk_unit, TPS_CLK, TMR_CLK);
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sim_activate_after(timer_clk_unit, 1000000 / t);
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}
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return SCPE_OK;
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@ -475,9 +483,11 @@ t_stat timer1_svc(UNIT *uptr)
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}
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ticks = ctr->divider / TIMER_STP_US;
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if (ticks == 0) {
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if (ticks < CLK_MIN_TICKS) {
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ticks = TPS_CLK;
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}
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t = sim_rtcn_calb(ticks, TMR_CLK);
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sim_activate_after(uptr, (uint32) (1000000 / ticks));
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@ -517,10 +527,12 @@ uint32 timer_read(uint32 pa, size_t size)
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case TIMER_REG_DIVA:
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case TIMER_REG_DIVB:
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case TIMER_REG_DIVC:
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if (ctr->enabled && ctr->gate) {
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ctr_val = timer_current_val(ctr);
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} else {
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ctr_val = ctr->divider;
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ctr_val = ctr->val;
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if (ctr_val != ctr->divider) {
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sim_debug(READ_MSG, &timer_dev,
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"[%08x] >>> ctr_val = %04x, ctr->divider = %04x\n",
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R[NUM_PC], ctr_val, ctr->divider);
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}
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switch (ctr->mode & CLK_RW) {
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@ -565,24 +577,39 @@ void handle_timer_write(uint8 ctrnum, uint32 val)
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case 0x10:
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ctr->divider &= 0xff00;
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ctr->divider |= val & 0xff;
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ctr->val = ctr->divider;
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ctr->enabled = TRUE;
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ctr->stime = sim_gtime();
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sim_cancel(timer_clk_unit);
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sim_activate_abs(timer_clk_unit, ctr->divider * TIMER_STP_US);
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break;
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case 0x20:
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ctr->divider &= 0x00ff;
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ctr->divider |= (val & 0xff) << 8;
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ctr->val = ctr->divider;
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ctr->enabled = TRUE;
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ctr->stime = sim_gtime();
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/* Kick the timer to get the new divider value */
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sim_cancel(timer_clk_unit);
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sim_activate_abs(timer_clk_unit, ctr->divider * TIMER_STP_US);
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break;
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case 0x30:
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if (ctr->lmb) {
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ctr->lmb = FALSE;
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ctr->divider = (uint16) ((ctr->divider & 0x00ff) | ((val & 0xff) << 8));
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ctr->val = ctr->divider;
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ctr->enabled = TRUE;
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ctr->stime = sim_gtime();
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sim_debug(READ_MSG, &timer_dev,
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"[%08x] Write timer %d val LMB (MSB): %02x\n",
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R[NUM_PC], ctrnum, val & 0xff);
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/* Kick the timer to get the new divider value */
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sim_cancel(timer_clk_unit);
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sim_activate_abs(timer_clk_unit, ctr->divider * TIMER_STP_US);
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} else {
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ctr->lmb = TRUE;
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ctr->divider = (ctr->divider & 0xff00) | (val & 0xff);
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ctr->val = ctr->divider;
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}
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break;
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default:
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@ -652,7 +679,7 @@ t_stat tod_reset(DEVICE *dptr)
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if (!sim_is_running) {
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t = sim_rtcn_init_unit(&tod_unit, TPS_TOD, TMR_TOD);
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sim_activate_after(&tod_unit, 1000000 / TPS_TOD);
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sim_activate_after(&tod_unit, 1000000 / t);
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}
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return SCPE_OK;
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@ -43,6 +43,7 @@ extern DEBTAB sys_deb_tab[];
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struct timer_ctr {
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uint16 divider;
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uint16 val;
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uint8 mode;
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t_bool lmb;
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t_bool enabled;
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