690c30b6f4
Clock reset was not being handled gracefully at all, leading some diagnostic tests not to pass, or not to pass consistently. This change will "kick" the system clock whenever the timer divider is reset, so the new divider is picked up immediately.
85 lines
3 KiB
C
85 lines
3 KiB
C
/* 3b2_cpu.h: AT&T 3B2 Model 400 System Devices (Header)
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Copyright (c) 2017, Seth J. Morabito
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Permission is hereby granted, free of charge, to any person
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obtaining a copy of this software and associated documentation
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files (the "Software"), to deal in the Software without
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restriction, including without limitation the rights to use, copy,
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modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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Except as contained in this notice, the name of the author shall
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not be used in advertising or otherwise to promote the sale, use or
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other dealings in this Software without prior written authorization
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from the author.
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*/
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#ifndef _3B2_SYSDEV_H_
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#define _3B2_SYSDEV_H_
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#include "3b2_defs.h"
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#include "3b2_sys.h"
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#include "3b2_cpu.h"
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extern DEVICE nvram_dev;
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extern DEVICE timer_dev;
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extern DEVICE csr_dev;
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extern DEVICE tod_dev;
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extern DEBTAB sys_deb_tab[];
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struct timer_ctr {
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uint16 divider;
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uint16 val;
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uint8 mode;
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t_bool lmb;
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t_bool enabled;
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t_bool gate;
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double stime; /* Most recent start time of counter */
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};
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/* NVRAM */
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t_stat nvram_ex(t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
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t_stat nvram_dep(t_value val, t_addr exta, UNIT *uptr, int32 sw);
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t_stat nvram_reset(DEVICE *dptr);
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uint32 nvram_read(uint32 pa, size_t size);
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t_stat nvram_attach(UNIT *uptr, CONST char *cptr);
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t_stat nvram_detach(UNIT *uptr);
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const char *nvram_description(DEVICE *dptr);
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void nvram_write(uint32 pa, uint32 val, size_t size);
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/* 8253 Timer */
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t_stat timer_reset(DEVICE *dptr);
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uint32 timer_read(uint32 pa, size_t size);
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void timer_write(uint32 pa, uint32 val, size_t size);
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t_stat timer0_svc(UNIT *uptr);
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t_stat timer1_svc(UNIT *uptr);
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t_stat timer2_svc(UNIT *uptr);
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/* CSR */
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t_stat csr_svc(UNIT *uptr);
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t_stat csr_ex(t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
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t_stat csr_dep(t_value val, t_addr exta, UNIT *uptr, int32 sw);
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t_stat csr_reset(DEVICE *dptr);
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uint32 csr_read(uint32 pa, size_t size);
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void csr_write(uint32 pa, uint32 val, size_t size);
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/* TOD */
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t_stat tod_svc(UNIT *uptr);
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t_stat tod_reset(DEVICE *dptr);
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uint32 tod_read(uint32 pa, size_t size);
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void tod_write(uint32, uint32 val, size_t size);
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#endif
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