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ND100: Fix CLK device setup and calibration

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Original logic mixed up parameters and calibrated for 20000 ticks
per second rather than 50.
This commit is contained in:
Mark Pizzolato 2023-04-01 20:23:23 -10:00 • committed by Paul Koning
parent 0bc7f09edf
commit 75e79a4da8
1 changed files with 14 additions and 9 deletions
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23
ND100/nd100_stddev.c
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@ -219,13 +219,14 @@ iox_tty(int addr)
/* /*
* Real-time clock. * Real-time clock.
*/ */
#define US_PER_CLK 20000
#define CLK_PER_SEC 50 #define CLK_PER_SEC 50
int int_enabled, dev_ready; int int_enabled, dev_ready;
struct intr rtc_int = { 0, 1 }; struct intr rtc_int = { 0, 1 };
t_stat clk_reset(DEVICE *dptr);
t_stat clk_svc(UNIT *uptr); t_stat clk_svc(UNIT *uptr);
UNIT clk_unit = { UDATA (&clk_svc, 0, 0) }; UNIT clk_unit = { UDATA (&clk_svc, 0, 0) };
@ -243,7 +244,7 @@ MTAB clk_mod[] = {
DEVICE clk_dev = { DEVICE clk_dev = {
"RTC", &clk_unit, clk_reg, clk_mod, "RTC", &clk_unit, clk_reg, clk_mod,
1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
NULL, NULL, NULL, NULL, NULL, &clk_reset,
NULL, NULL, NULL, NULL, NULL, NULL,
0, 0 0, 0
}; };
@ -258,18 +259,14 @@ iox_clk(int addr)
regA = 0; regA = 0;
break; break;
case 1: /* Reset counter */ case 1: /* Reset counter */
sim_cancel(&clk_unit); sim_activate_after_abs(&clk_unit, 1000000/CLK_PER_SEC);
if (!sim_is_active(&clk_unit))
sim_activate(&clk_unit, sim_rtc_init(US_PER_CLK));
break; break;
case 2: /* read status */ case 2: /* read status */
regA = (dev_ready << 3) | int_enabled; regA = (dev_ready << 3) | int_enabled;
break; break;
case 3: /* set status */ case 3: /* set status */
sim_cancel(&clk_unit); sim_activate_after_abs(&clk_unit, 1000000/CLK_PER_SEC);
if (!sim_is_active(&clk_unit))
sim_activate(&clk_unit, sim_rtc_init(US_PER_CLK));
int_enabled = regA & 1; int_enabled = regA & 1;
if (BIT13(regA)) if (BIT13(regA))
dev_ready = 0; dev_ready = 0;
@ -281,10 +278,18 @@ iox_clk(int addr)
return rv; return rv;
} }
t_stat
clk_reset (DEVICE *dptr)
{
sim_rtc_init(1000000/CLK_PER_SEC);
return SCPE_OK;
}
t_stat t_stat
clk_svc(UNIT *uptr) clk_svc(UNIT *uptr)
{ {
sim_activate(&clk_unit, sim_rtc_calb(US_PER_CLK)); sim_rtc_calb(CLK_PER_SEC);
sim_activate_after(&clk_unit, 1000000/CLK_PER_SEC);
dev_ready = 1; dev_ready = 1;
if (int_enabled) if (int_enabled)
extint(13, &rtc_int); extint(13, &rtc_int);