ND100: Fix CLK device setup and calibration
Original logic mixed up parameters and calibrated for 20000 ticks per second rather than 50.
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parent
0bc7f09edf
commit
75e79a4da8
1 changed files with 14 additions and 9 deletions
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@ -219,13 +219,14 @@ iox_tty(int addr)
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/*
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/*
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* Real-time clock.
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* Real-time clock.
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*/
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*/
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#define US_PER_CLK 20000
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#define CLK_PER_SEC 50
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#define CLK_PER_SEC 50
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int int_enabled, dev_ready;
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int int_enabled, dev_ready;
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struct intr rtc_int = { 0, 1 };
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struct intr rtc_int = { 0, 1 };
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t_stat clk_reset(DEVICE *dptr);
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t_stat clk_svc(UNIT *uptr);
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t_stat clk_svc(UNIT *uptr);
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UNIT clk_unit = { UDATA (&clk_svc, 0, 0) };
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UNIT clk_unit = { UDATA (&clk_svc, 0, 0) };
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@ -243,7 +244,7 @@ MTAB clk_mod[] = {
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DEVICE clk_dev = {
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DEVICE clk_dev = {
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"RTC", &clk_unit, clk_reg, clk_mod,
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"RTC", &clk_unit, clk_reg, clk_mod,
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1, 0, 0, 0, 0, 0,
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1, 0, 0, 0, 0, 0,
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NULL, NULL, NULL,
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NULL, NULL, &clk_reset,
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NULL, NULL, NULL,
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NULL, NULL, NULL,
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0, 0
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0, 0
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};
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};
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@ -258,18 +259,14 @@ iox_clk(int addr)
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regA = 0;
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regA = 0;
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break;
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break;
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case 1: /* Reset counter */
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case 1: /* Reset counter */
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sim_cancel(&clk_unit);
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sim_activate_after_abs(&clk_unit, 1000000/CLK_PER_SEC);
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if (!sim_is_active(&clk_unit))
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sim_activate(&clk_unit, sim_rtc_init(US_PER_CLK));
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break;
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break;
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case 2: /* read status */
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case 2: /* read status */
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regA = (dev_ready << 3) | int_enabled;
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regA = (dev_ready << 3) | int_enabled;
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break;
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break;
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case 3: /* set status */
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case 3: /* set status */
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sim_cancel(&clk_unit);
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sim_activate_after_abs(&clk_unit, 1000000/CLK_PER_SEC);
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if (!sim_is_active(&clk_unit))
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sim_activate(&clk_unit, sim_rtc_init(US_PER_CLK));
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int_enabled = regA & 1;
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int_enabled = regA & 1;
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if (BIT13(regA))
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if (BIT13(regA))
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dev_ready = 0;
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dev_ready = 0;
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@ -281,10 +278,18 @@ iox_clk(int addr)
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return rv;
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return rv;
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}
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}
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t_stat
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clk_reset (DEVICE *dptr)
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{
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sim_rtc_init(1000000/CLK_PER_SEC);
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return SCPE_OK;
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}
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t_stat
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t_stat
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clk_svc(UNIT *uptr)
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clk_svc(UNIT *uptr)
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{
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{
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sim_activate(&clk_unit, sim_rtc_calb(US_PER_CLK));
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sim_rtc_calb(CLK_PER_SEC);
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sim_activate_after(&clk_unit, 1000000/CLK_PER_SEC);
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dev_ready = 1;
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dev_ready = 1;
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if (int_enabled)
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if (int_enabled)
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extint(13, &rtc_int);
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extint(13, &rtc_int);
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