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Merge branch 'master' into AsyncTmxr

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Conflicts merged and missing changes in new modules added as needed for clock co-scheduling.
This commit is contained in:
Mark Pizzolato 2013-01-21 16:52:42 -08:00
commit 83c1d80194
344 changed files with 64292 additions and 11863 deletions
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2
.gitignore vendored
View file

@ -1,3 +1,4 @@
.git-commit-id
#ignore thumbnails created by windows
Thumbs.db
#Ignore files built by Visual Studio
@ -41,3 +42,4 @@ ipch/
Visual Studio Projects/*

31
0readmeAsynchIO.txt
View file

@ -155,7 +155,10 @@ The pdp11_rq.c module has been refactored to leverage the asynch I/O
features of the sim_disk library. The impact to this code to adopt the
asynch I/O paradigm was quite minimal.
The pdp11_rp.c module has also been refactored to leverage the asynch I/O
features of the sim_disk library.
features of the sim_disk library. The impact to this code to adopt the
asynch I/O paradigm was also quite minimal. After conversion a latent
bug in the VAX Massbus adapter implementation was illuminated due to the
more realistic delays to perform I/O operations.
The pdp11_tq.c module has been refactored to leverage the asynch I/O
features of the sim_tape library. The impact to this code to adopt the
asynch I/O paradigm was very significant. This was due to the two facts:
@ -195,15 +198,8 @@ particular device emulation which isn't capable of asynch operation, or
it can be defined globally on the compile command line for the simulator.
Alternatively, if a specific Multiplexer device doesn't function correctly
under the multiplexer asynchronous environment and it will never be
revised to operate correctly, it may set the TMUF_NOASYNCH bit in its
unit flags field.
Console I/O can operate asynchronously if the simulator notifies the
tmxr/console subsystem which device unit is used by the simulator to poll
for console input. This is done by including sim_tmxr.h in the source
module which contains the console input device definition and calling
tmxr_set_console_input_unit(). tmxr_set_console_input_unit would usually
be called in a device reset routine.
revised to operate correctly, it may statically set the TMUF_NOASYNCH bit
in its unit flags field.
Some devices will need a small amount of extra coding to leverage the
Multiplexer Asynch I/O capabilties. Devices which require extra coding
@ -215,7 +211,17 @@ have one or more of the following characteristics:
The extra coding required for proper operation is to call
tmxr_set_line_unit() to associate the appropriate input polling unit to
the respective multiplexer line.
the respective multiplexer line (ONLY if input polling is done by a unit
different than the unit specified when the MUX was attached). If output
polling is done on a different unit, then tmxr_set_line_output_unit()
should be called to describe that fact.
Console I/O can operate asynchronously if the simulator notifies the
tmxr/console subsystem which device unit is used by the simulator to poll
for console input and output units. This is done by including sim_tmxr.h
in the source module which contains the console input device definition
and calling tmxr_set_console_units(). tmxr_set_console_units would usually
be called in a device reset routine.
sim_tmxr consumers:
- Altair Z80 SIO devices = 1, units = 1, lines = 4, flagbits = 8, Untested Asynch
@ -288,7 +294,8 @@ happen under a combination of conditions:
2) the multiplexor device is NOT attached, and thus is not being managed by
the asynchronous multiplexer support
3) the multiplexer device schedules polling (co-scheduled) when not
attached (such polling will never produce anything input).
attached (such polling will never produce any input, so this is probably
a bug).
In prior simh versions support for clock co-scheduling was implmented
separately by each simulator, and usually was expressed by code of the form:
sim_activate (uptr, clk_cosched (tmxr_poll));

32
0readme_39.txt
View file

@ -34,25 +34,25 @@ components and build network capable simulators if they are available.
1.1.4 PDP11 and VAX (Mark Pizzolato)
- Added DELQA-Plus device.
- added DELQA-Plus device
1.1.5 IA64 VMS Ethernet Support
- Identified compiler version issues and added IA64 support (Matt Burke)
- identified compiler version issues and added IA64 support (Matt Burke)
1.1.6 Visual Studio Projects (Mark Pizzolato)
2. Bugs Fixed
Please see the revision history on http://simh.trailing-edge.com or
in the source module sim_rev.h.
3. Status Report
This is the last release of SimH for which I will be sole editor. After this
This is the last release of SimH for which I will be lead editor. After this
release, the source is moving to a public repository:
https://github.com/markpizz/simh
under the general editorship of Dave Hittner and Mark Pizzolato. The status
of the individual simulators is as follows:
@ -113,7 +113,7 @@ Stable and working; runs available software.
3.13 IBM 1620
Hand debug only. No software for it has been found or tested.
Hand debug only. No software for it has been found or tested.
3.14 IBM 7094
@ -126,7 +126,7 @@ Stable and working, but not really supported. Runs available software.
3.16 IBM 1130
Stable and working; runs available software. Supported and edited by
Stable and working; runs available software. Supported and edited by
Brian Knittel.
3.17 HP 2100/1000
@ -140,7 +140,7 @@ Stable and working; runs available software.
3.19 GRI-909/99
Hand debug only. No software for it has been found or tested.
Hand debug only. No software for it has been found or tested.
3.20 SDS-940
@ -168,10 +168,23 @@ Bill Beech
3.25 Sigma 32b
Incomplete; more work is needed on the peripherals for accuracy.
Included in the beta simulators package.
3.26 Alpha
Incomplete; essentially just an EV-5 (21164) chip emulator.
Incomplete; essentially just an EV-5 (21164) chip emulator. Included
in the beta simulators package.
3.27 SAGE
Incomplete. Included in the beta simulators package.
3.28 SC1
Internal simulator for SiCortex supercomputer; intended as an example
of implementing an SMP system in the current SimH structure. Included
in the beta simulators package.
4. Suggestions for Future Work
@ -198,4 +211,3 @@ Incomplete; essentially just an EV-5 (21164) chip emulator.
- Data General MV8000 (if a hobbyist license can be obtained for AOS)
- Alpha simulator
- HP 3000 (16b) simulator with MPE

6
0readme_ethernet.txt
View file

@ -156,9 +156,9 @@ Note 2: Root access will likely be needed to configure or start the vde
Note 3: Simulators running using VDE networking can run without root
privilege.
Linux (Ubuntu 10.04):
Linux (Ubuntu 11.10):
apt-get install make
apt-get install libvdeplug-dev
apt-get install libvdeplug2-dev
apt-get install vde2
vde_switch -s /tmp/switch1 -tap tap0 -m 666
@ -207,7 +207,7 @@ Building on Windows:
The contents of the windows-build directory can be downloaded from:
https://github.com/downloads/markpizz/simh/windows-build.zip
https://github.com/downloads/simh/simh/windows-build.zip
There are Windows batch files provided to initiate compiles using the MinGW

8
ALTAIR/altair_cpu.c
View file

@ -107,9 +107,6 @@ int32 chip = 0; /* 0 = 8080 chip, 1 = z8
int32 PCX; /* External view of PC */
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ;/* breakpoint info */
/* function prototypes */
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
@ -300,9 +297,8 @@ DEVICE cpu_dev = {
NULL, NULL, NULL
};
int32 sim_instr (void)
t_stat sim_instr (void)
{
extern int32 sim_interval;
int32 PC, IR, OP, DAR, reason, hi, lo, carry, i;
PC = saved_PC & ADDRMASK; /* load local PC */
@ -366,7 +362,7 @@ int32 sim_instr (void)
if ((OP & 0xCF) == 0x01) { /* LXI */
DAR = M[PC] & 0x00ff;
PC++;
DAR = DAR | (M[PC] <<8) & 0xFF00;;
DAR = DAR | ((M[PC] <<8) & 0xFF00);
putpair((OP >> 4) & 0x03, DAR);
PC++;
continue;

6
ALTAIR/altair_sys.c
View file

@ -153,7 +153,7 @@ int32 oplen[256] = {
load starts at the current value of the PC.
*/
int32 sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
{
int32 i, addr = 0, cnt = 0;
@ -180,7 +180,7 @@ return (SCPE_OK);
status = error code
*/
int32 fprint_sym (FILE *of, int32 addr, uint32 *val,
t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
UNIT *uptr, int32 sw)
{
int32 cflag, c1, c2, inst, adr;
@ -229,7 +229,7 @@ return -(oplen[inst] - 1);
status = error status
*/
int32 parse_sym (char *cptr, int32 addr, UNIT *uptr, uint32 *val, int32 sw)
t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
{
int32 cflag, i = 0, j, r;
char gbuf[CBUFSIZE];

10
AltairZ80/altairz80_cpu.c
View file

@ -128,7 +128,6 @@
} \
}
extern int32 sim_int_char;
extern int32 sio0s (const int32 port, const int32 io, const int32 data);
extern int32 sio0d (const int32 port, const int32 io, const int32 data);
extern int32 sio1s (const int32 port, const int32 io, const int32 data);
@ -147,8 +146,6 @@ extern void do_SIMH_sleep(void);
extern void prepareMemoryAccessMessage(const t_addr loc);
extern void prepareInstructionMessage(const t_addr loc, const uint32 op);
extern FILE *sim_deb;
extern t_stat sim_instr_nommu(void);
extern uint8 MOPT[MAXBANKSIZE];
extern t_stat sim_instr_8086(void);
@ -194,7 +191,6 @@ void setBankSelect(const int32 b);
uint32 getClockFrequency(void);
void setClockFrequency(const uint32 Value);
uint32 getCommon(void);
t_stat sim_load(FILE *fileref, char *cptr, char *fnam, int32 flag);
uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
@ -1882,15 +1878,12 @@ void setClockFrequency(const uint32 Value) {
}
static t_stat sim_instr_mmu (void) {
extern int32 sim_interval;
extern t_bool sim_brk_pend[SIM_BKPT_N_SPC];
extern int32 timerInterrupt;
extern int32 timerInterruptHandler;
extern int32 keyboardInterrupt;
extern uint32 keyboardInterruptHandler;
extern uint32 sim_os_msec(void);
extern const t_bool rtc_avail;
extern uint32 sim_brk_summ;
int32 reason = SCPE_OK;
register uint32 specialProcessing;
register uint32 AF;
@ -6287,7 +6280,6 @@ static t_stat sim_instr_mmu (void) {
/* reset routine */
static t_stat cpu_reset(DEVICE *dptr) {
extern uint32 sim_brk_types, sim_brk_dflt; /* breakpoint info */
int32 i;
AF_S = AF1_S = 0;
BC_S = DE_S = HL_S = 0;
@ -6817,7 +6809,7 @@ void (*sim_vm_init) (void) = &altairz80_init;
#define PLURAL(x) (x), (x) == 1 ? "" : "s"
t_stat sim_load(FILE *fileref, char *cptr, char *fnam, int32 flag) {
t_stat sim_load(FILE *fileref, char *cptr, char *fnam, int flag) {
int32 i;
uint32 addr, cnt = 0, org, pagesModified = 0, makeROM = FALSE;
t_addr j, lo, hi;

2
AltairZ80/altairz80_cpu_nommu.c
View file

@ -985,8 +985,6 @@ static uint16 GET_WORD(register uint32 a) {
INOUTFLAGS((HIGH_REGISTER(BC) & 0xa8) | ((HIGH_REGISTER(BC) == 0) << 6), x)
t_stat sim_instr_nommu(void) {
extern int32 sim_interval;
extern uint32 sim_brk_summ;
int32 reason = SCPE_OK;
register uint32 AF;
register uint32 BC;

23
AltairZ80/altairz80_net.c
View file

@ -150,36 +150,33 @@ static t_stat net_reset(DEVICE *dptr) {
}
static t_stat net_attach(UNIT *uptr, char *cptr) {
uint32 i, ipa, ipp;
t_stat r = get_ipaddr(cptr, &ipa, &ipp);
uint32 i;
char host[CBUFSIZE], port[CBUFSIZE];
t_stat r;
r = sim_parse_addr (cptr, host, sizeof(host), "localhost", port, sizeof(port), "3000", NULL);
if (r != SCPE_OK)
return SCPE_ARG;
if (ipa == 0)
ipa = 0x7F000001; /* localhost = 127.0.0.1 */
if (ipp == 0)
ipp = 3000;
net_unit.u3 = ipp;
net_unit.u4 = ipa;
net_reset(&net_dev);
for (i = 0; i <= MAX_CONNECTIONS; i++)
serviceDescriptor[i].ioSocket = 0;
if (net_unit.flags & UNIT_SERVER) {
net_unit.wait = NET_INIT_POLL_SERVER;
serviceDescriptor[1].masterSocket = sim_master_sock(ipp);
serviceDescriptor[1].masterSocket = sim_master_sock(cptr, NULL);
if (serviceDescriptor[1].masterSocket == INVALID_SOCKET)
return SCPE_IOERR;
}
else {
net_unit.wait = NET_INIT_POLL_CLIENT;
serviceDescriptor[0].ioSocket = sim_connect_sock(ipa, ipp);
serviceDescriptor[0].ioSocket = sim_connect_sock(cptr, "localhost", "3000");
if (serviceDescriptor[0].ioSocket == INVALID_SOCKET)
return SCPE_IOERR;
}
net_unit.flags |= UNIT_ATT;
net_unit.filename = (char *) calloc(CBUFSIZE, sizeof (char)); /* alloc name buf */
net_unit.filename = (char *) calloc(1, strlen(cptr)+1); /* alloc name buf */
if (net_unit.filename == NULL)
return SCPE_MEM;
strncpy(net_unit.filename, cptr, CBUFSIZE); /* save name */
strcpy(net_unit.filename, cptr); /* save name */
return SCPE_OK;
}
@ -216,7 +213,7 @@ static t_stat net_svc(UNIT *uptr) {
}
}
else if (serviceDescriptor[0].ioSocket == 0) {
serviceDescriptor[0].ioSocket = sim_connect_sock(net_unit.u4, net_unit.u3);
serviceDescriptor[0].ioSocket = sim_connect_sock(net_unit.filename, "localhost", "3000");
if (serviceDescriptor[0].ioSocket == INVALID_SOCKET)
return SCPE_IOERR;
printf("\rWaiting for server ... Type g<return> (possibly twice) when ready" NLP);

5
AltairZ80/altairz80_sio.c
View file

@ -166,12 +166,9 @@ extern void setClockFrequency(const uint32 Value);
extern int32 chiptype;
extern const t_bool rtc_avail;
extern uint32 PCX;
extern int32 sim_switches;
extern int32 sim_quiet;
extern int32 SR;
extern UNIT cpu_unit;
extern volatile int32 stop_cpu;
extern int32 sim_interval;
/* Debug Flags */
static DEBTAB generic_dt[] = {
@ -324,7 +321,7 @@ DEVICE sio_dev = {
1, 10, 31, 1, 8, 8,
NULL, NULL, &sio_reset,
NULL, &sio_attach, &sio_detach,
NULL, DEV_DEBUG, 0,
NULL, DEV_DEBUG | DEV_MUX, 0,
generic_dt, NULL, "Serial Input Output SIO"
};

2
AltairZ80/i86_decode.c
View file

@ -41,9 +41,7 @@ extern int32 SPX_S; /* SP register (8086) */
extern int32 IP_S; /* IP register (8086) */
extern int32 FLAGS_S; /* flags register (8086) */
extern int32 PCX_S; /* PC register (8086), 20 bit */
extern int32 sim_interval;
extern uint32 PCX; /* external view of PC */
extern uint32 sim_brk_summ;
extern UNIT cpu_unit;
void i86_intr_raise(PC_ENV *m,uint8 intrnum);

4
GRI/gri_cpu.c
View file

@ -187,10 +187,6 @@ int16 scq[SCQ_SIZE] = { 0 }; /* PC queue */
int32 scq_p = 0; /* PC queue ptr */
REG *scq_r = NULL; /* PC queue reg ptr */
extern int32 sim_interval;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_reset (DEVICE *dptr);

2
GRI/gri_stddev.c
View file

@ -39,6 +39,7 @@
*/
#include "gri_defs.h"
#include "sim_tmxr.h"
#include <ctype.h>
uint32 hsr_stopioe = 1, hsp_stopioe = 1;
@ -277,6 +278,7 @@ return SCPE_OK;
t_stat tti_reset (DEVICE *dptr)
{
tmxr_set_console_units (&tti_unit, &tto_unit);
tti_unit.buf = 0; /* clear buffer */
dev_done = dev_done & ~INT_TTI; /* clear ready */
sim_activate (&tti_unit, tti_unit.wait); /* activate unit */

1
GRI/gri_sys.c
View file

@ -37,7 +37,6 @@ extern DEVICE hsr_dev, hsp_dev;
extern DEVICE rtc_dev;
extern REG cpu_reg[];
extern uint16 M[];
extern int32 sim_switches;
void fprint_addr (FILE *of, uint32 val, uint32 mod, uint32 dst);

11
H316/h316_cpu.c
View file

@ -276,12 +276,6 @@ int32 hst_p = 0; /* history pointer */
int32 hst_lnt = 0; /* history length */
InstHistory *hst = NULL; /* instruction history */
extern int32 sim_int_char;
extern int32 sim_interval;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern FILE *sim_log;
extern DEVICE *sim_devices[];
t_bool devtab_init (void);
int32 dmaio (int32 inst, int32 fnc, int32 dat, int32 dev);
int32 undio (int32 inst, int32 fnc, int32 dat, int32 dev);
@ -296,9 +290,6 @@ t_stat cpu_show_dma (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat cpu_set_nchan (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat cpu_show_nchan (FILE *st, UNIT *uptr, int32 val, void *desc);
extern t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
/* CPU data structures
cpu_dev CPU device descriptor
@ -1592,8 +1583,6 @@ char *cptr = (char *) desc;
t_value sim_eval;
t_stat r;
InstHistory *h;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
static uint8 has_opnd[16] = {
0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1
};

1
H316/h316_dp.c
View file

@ -220,7 +220,6 @@ extern int32 dev_int, dev_enb;
extern uint32 chan_req;
extern int32 stop_inst;
extern uint32 dma_ad[DMA_MAX];
extern int32 sim_switches;
uint32 dp_cw1 = 0; /* cmd word 1 */
uint32 dp_cw2 = 0; /* cmd word 2 */

3
H316/h316_stddev.c
View file

@ -68,6 +68,7 @@
*/
#include "h316_defs.h"
#include "sim_tmxr.h"
#include <ctype.h>
#define UNIT_V_ASC (TTUF_V_UF + 0) /* ASCII */
@ -88,7 +89,6 @@ extern int32 PC;
extern int32 stop_inst;
extern int32 C, dp, ext, extoff_pending, sc;
extern int32 dev_int, dev_enb;
extern int32 sim_switches;
extern UNIT cpu_unit;
uint32 ptr_motion = 0; /* read motion */
@ -534,6 +534,7 @@ return SCPE_OK;
t_stat ptp_reset (DEVICE *dptr)
{
tmxr_set_console_units (&tty_unit[TTR], &tty_unit[TTO]);
CLR_INT (INT_PTP); /* clear ready, enb */
CLR_ENB (INT_PTP);
ptp_power = 0; /* power off */

1
H316/h316_sys.c
View file

@ -43,7 +43,6 @@ extern DEVICE fhd_dev;
extern DEVICE mt_dev;
extern REG cpu_reg[];
extern uint16 M[];
extern int32 sim_switches;
/* SCP data structures and interface routines

26
HP2100/hp2100_baci.c
View file

@ -26,6 +26,7 @@
BACI 12966A BACI card
10-Feb-12 JDB Deprecated DEVNO in favor of SC
Removed DEV_NET to allow restoration of listening port
28-Mar-11 JDB Tidied up signal handling
26-Oct-10 JDB Changed I/O signal handler for revised signal model
25-Nov-08 JDB Revised for new multiplexer library SHOW routines
@ -502,11 +503,14 @@ DEVICE baci_dev = {
&baci_attach, /* attach routine */
&baci_detach, /* detach routine */
&baci_dib, /* device information block */
DEV_DEBUG | DEV_DISABLE, /* device flags */
DEV_DEBUG | DEV_DISABLE | DEV_MUX, /* device flags */
0, /* debug control flags */
baci_deb, /* debug flag name table */
NULL, /* memory size change routine */
NULL }; /* logical device name */
NULL, /* logical device name */
NULL, /* help routine */
NULL, /* help attach routine*/
(void*)&baci_desc }; /* help context */
/* I/O signal handler.
@ -1157,11 +1161,11 @@ if (baci_edsiw & (baci_status ^ baci_dsrw) & IN_MODEM) /* device interrupt? */
baci_status = baci_status | IN_DEVINT; /* set flag */
if ((baci_status & IN_STDIRQ) || /* standard interrupt? */
(!(baci_icw & OUT_DCPC) && /* or under program control */
(baci_status & IN_FIFOIRQ)) || /* and FIFO interrupt? */
((IO_MODE == RECV) && /* or receiving */
!(baci_icw & OUT_DCPC) && /* or under program control */
(baci_status & IN_FIFOIRQ) || /* and FIFO interrupt? */
(IO_MODE == RECV) && /* or receiving */
(baci_edsiw & OUT_ENCM) && /* and char mode */
(baci_fget != baci_fput))) { /* and FIFO not empty? */
(baci_fget != baci_fput)) { /* and FIFO not empty? */
if (baci.lockout) { /* interrupt lockout? */
if (DEBUG_PRI (baci_dev, DEB_CMDS))
@ -1185,8 +1189,8 @@ if ((baci_status & IN_STDIRQ) || /* standard interrupt? *
}
if ((baci_icw & OUT_DCPC) && /* DCPC enabled? */
(((IO_MODE == XMIT) && (baci_fcount < 128)) || /* and xmit and room in FIFO */
((IO_MODE == RECV) && (baci_fcount > 0)))) { /* or recv and data in FIFO? */
((IO_MODE == XMIT) && (baci_fcount < 128) || /* and xmit and room in FIFO */
(IO_MODE == RECV) && (baci_fcount > 0))) { /* or recv and data in FIFO? */
if (baci.lockout) { /* interrupt lockout? */
if (DEBUG_PRI (baci_dev, DEB_CMDS))
@ -1472,9 +1476,9 @@ if (baci_uart_clk > 0) { /* transfer in progress?
if ((IO_MODE == XMIT) && /* transmit mode? */
((baci_uart_clk == 0) || /* and end of character? */
((baci_uart_clk == 8) && /* or last stop bit */
(baci_cfcw & OUT_STBITS) && /* and extra stop bit requested */
((baci_cfcw & OUT_CHARSIZE) == 0)))) { /* and 1.5 stop bits used? */
(baci_uart_clk == 8) && /* or last stop bit */
(baci_cfcw & OUT_STBITS) && /* and extra stop bit requested */
((baci_cfcw & OUT_CHARSIZE) == 0))) { /* and 1.5 stop bits used? */
baci_uart_clk = 0; /* clear clock count */

113
HP2100/hp2100_bugfixes.txt
View file

@ -1,6 +1,6 @@
HP 2100 SIMULATOR BUG FIX WRITEUPS
==================================
Last update: 2012-03-25
Last update: 2012-12-28
1. PROBLEM: Booting from magnetic tape reports "HALT instruction, P: 77756
@ -6280,3 +6280,114 @@
(hp2100_mt.c).
STATUS: Fixed in version 3.9-0.
247. PROBLEM: The ICD disc read end-of-track delay is not optimal.
VERSION: 3.9-0
OBSERVATION: To avoid End of Cylinder errors when reading the last sector
of a track, the ICD controller must delay more than the usual intersector
time to allow the OS driver to send an Untalk if a read is to be
terminated. Currently, the longer delay is used if an end-of-cylinder
condition is present. However, the delay is needed only if the resulting
seek attempt would cause an error if the read is continued; the normal
delay should be used if the seek is permitted and would succeed.
Also, if the host does send an Untalk during this time, the longer delay
should be cancelled, and command termination should be scheduled for
immediate processing.
CAUSE: Suboptimal implementation.
RESOLUTION: Modify "end_read" (hp_disclib.c) to use the longer time only
if the seek would fail, and modify "complete_read" (hp2100_di_da.c) to
cancel the intersector delay and schedule the completion phase immediately.
STATUS: Fixed in version 4.0-0.
248. PROBLEM: Calling a VMA routine from a non-VMA program does not MP abort.
VERSION: 3.9-0
OBSERVATION: If a virtual memory routine, such as .LBP, is called from a
non-VMA program, it should be aborted with a memory protect error.
Instead, a dynamic mapping error occurs instead:
ASMB,R
NAM MAPPR
EXT EXEC,.LBP
START CLA
CLB
JSB .LBP
NOP
JSB EXEC
DEF *+2
DEF *+1
DEC 6
END START
DM VIOL = 160377
DM INST = 105257
ABE 0 0 0
XYO 0 0 0
DM MAPPR 2014
MAPPR ABORTED
CAUSE: The page mapping routine, "cpu_vma_mapte", returns TRUE if the page
table is set up and valid and FALSE if not. If a program is not a VMA
program, then it has no page table, but "cpu_vma_mapte" is returning TRUE
erroneously. That results in a DM error when the invalid page entry is
used.
The microcode explicitly tests for a non-VMA program, i.e., one with no ID
extension, and generates an MP error in this case.
RESOLUTION: Modify "cpu_vma_mapte" (hp2100_cpu5.c) to return FALSE if
called for a non-VMA program.
STATUS: Fixed in version 4.0-0.
249. PROBLEM: RESTORing a previously SAVEd session fails if the 12792C
multiplexer is attached.
VERSION: 3.9-0
OBSERVATION: If the MPX device has a listening port attached when a
session is saved, attempting to restore that session results in a "Unit not
attachable" error.
CAUSE: The MPX attach routine only allows attachment to unit 0, i.e.,
ATTACH MPX <port>, but the actual attachment is made to the Telnet poll
unit (unit 9). As SAVE finds the port attached to unit 9, RESTORE attempts
to reattach it to unit 9.
RESOLUTION: Modify "mpx_attach" (hp2100_mpx.c) to allow attachment to unit
9 only during a RESTORE.
STATUS: Fixed in version 4.0-0.
250. PROBLEM: DEASSIGNing the TBG device generates a debug warning.
VERSION: 3.9-0
OBSERVATION: When running the simulator under a debugger, entering the
command DEASSIGN TBG prints "warning: Invalid Address specified to
RtlFreeHeap."
CAUSE: The TBG logical name is specified statically in the DEVICE
structure, but "deassign_device" calls "free" on the pointer. The
developer's manual does not state that the logical name must be dynamically
allocated, but deassigning assumes that it was.
RESOLUTION: Modify "clk_reset" (hp2100_stddev.c) to allocate the logical
name during a power-on reset.
STATUS: Fixed in version 4.0-0.

51
HP2100/hp2100_cpu.c
View file

@ -29,6 +29,7 @@
DMA1,DMA2 12607B/12578A/12895A direct memory access controller
DCPC1,DCPC2 12897B dual channel port controller
09-May-12 JDB Separated assignments from conditional expressions
13-Jan-12 JDB Minor speedup in "is_mapped"
Added casts to cpu_mod, dmasio, dmapio, cpu_reset, dma_reset
07-Apr-11 JDB Fixed I/O return status bug for DMA cycles
@ -560,14 +561,7 @@ uint16 dms_map[MAP_NUM * MAP_LNT] = { 0 }; /* dms maps */
/* External data */
extern int32 sim_interval;
extern int32 sim_int_char;
extern int32 sim_brk_char;
extern int32 sim_del_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern DEVICE *sim_devices[];
extern char halt_msg[];
extern t_bool sim_idle_enab;
extern DIB clk_dib; /* CLK DIB for idle check */
/* CPU local routines */
@ -1054,7 +1048,8 @@ for (i = OPTDEV; i <= MAXDEV; i++) /* default optional devi
dtab [PWR] = &pwrf_dib; /* for now, powerfail is always present */
for (i = 0; (dptr = sim_devices [i]); i++) { /* loop thru dev */
for (i = 0; sim_devices [i] != NULL; i++) { /* loop thru dev */
dptr = sim_devices [i];
dibptr = (DIB *) dptr->ctxt; /* get DIB */
if (dibptr && !(dptr->flags & DEV_DIS)) { /* handler exists and device is enabled? */
@ -1464,17 +1459,17 @@ while (reason == SCPE_OK) { /* loop until halted */
*/
if ((sim_idle_enab) && (intrq == 0)) /* idle enabled w/o pending irq? */
if ((((PC == err_PC) || /* RTE through RTE-IVB */
((PC == (err_PC - 1)) && /* RTE-6/VM */
((ReadW (PC) & I_MRG) == I_ISZ))) && /* RTE jump target */
(mp_fence == CLEAR) && (M [xeqt] == 0) && /* RTE idle indications */
(M [tbg] == clk_dib.select_code)) || /* RTE verification */
if (((PC == err_PC) || /* RTE through RTE-IVB */
((PC == (err_PC - 1)) && /* RTE-6/VM */
((ReadW (PC) & I_MRG) == I_ISZ))) && /* RTE jump target */
(mp_fence == CLEAR) && (M [xeqt] == 0) && /* RTE idle indications */
(M [tbg] == clk_dib.select_code) || /* RTE verification */
((PC == (err_PC - 3)) && /* DOS through DOS-III */
(ReadW (PC) == I_STF) && /* DOS jump target */
(AR == 0177777) && (BR == 0177777) && /* DOS idle indication */
(M [m64] == 0177700) && /* DOS verification */
(M [p64] == 0000100))) /* DOS verification */
(PC == (err_PC - 3)) && /* DOS through DOS-III */
(ReadW (PC) == I_STF) && /* DOS jump target */
(AR == 0177777) && (BR == 0177777) && /* DOS idle indication */
(M [m64] == 0177700) && /* DOS verification */
(M [p64] == 0000100)) /* DOS verification */
sim_idle (TMR_POLL, FALSE); /* idle the simulator */
break;
@ -3351,7 +3346,7 @@ t_stat status;
uint32 ioresult;
IOCYCLE signals;
if ((bytes && !even) || (dma [ch].cw3 != DMASK)) { /* normal cycle? */
if (bytes && !even || dma [ch].cw3 != DMASK) { /* normal cycle? */
if (input) /* input cycle? */
signals = ioIOI | ioCLF; /* assert IOI and CLF */
else /* output cycle */
@ -3609,30 +3604,32 @@ DEVICE *dptr;
DIB *dibptr;
uint32 i, j, k;
t_bool is_conflict = FALSE;
uint32 conflicts[MAXDEV + 1] = { 0 };
uint32 conflicts [MAXDEV + 1] = { 0 };
for (i = 0; (dptr = sim_devices[i]); i++) {
for (i = 0; sim_devices [i] != NULL; i++) {
dptr = sim_devices [i];
dibptr = (DIB *) dptr->ctxt;
if (dibptr && !(dptr->flags & DEV_DIS))
if (++conflicts[dibptr->select_code] > 1)
if (++conflicts [dibptr->select_code] > 1)
is_conflict = TRUE;
}
if (is_conflict) {
sim_ttcmd();
for (i = 0; i <= MAXDEV; i++) {
if (conflicts[i] > 1) {
k = conflicts[i];
if (conflicts [i] > 1) {
k = conflicts [i];
printf ("Select code %o conflict:", i);
if (sim_log)
fprintf (sim_log, "Select code %o conflict:", i);
for (j = 0; (dptr = sim_devices[j]); j++) {
for (j = 0; sim_devices [j] != NULL; j++) {
dptr = sim_devices [j];
dibptr = (DIB *) dptr->ctxt;
if (dibptr && !(dptr->flags & DEV_DIS) && (i == dibptr->select_code)) {
if (k < conflicts[i]) {
if (dibptr && !(dptr->flags & DEV_DIS) && i == dibptr->select_code) {
if (k < conflicts [i]) {
printf (" and");
if (sim_log)

47
HP2100/hp2100_cpu0.c
View file

@ -1,6 +1,6 @@
/* hp2100_cpu0.c: HP 1000 user microcode and unimplemented instruction set stubs
Copyright (c) 2006-2010, J. David Bryan
Copyright (c) 2006-2012, J. David Bryan
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -25,6 +25,7 @@
CPU0 User microcode and unimplemented firmware options
09-May-12 JDB Separated assignments from conditional expressions
04-Nov-10 JDB Removed DS note regarding PIF card (is now implemented)
18-Sep-08 JDB .FLUN and self-tests for VIS and SIGNAL are NOP if not present
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
@ -129,9 +130,11 @@ uint32 entry;
entry = IR & 017; /* mask to entry point */
if (op_ds[entry] != OP_N)
if ((reason = cpu_ops (op_ds[entry], op, intrq))) /* get instruction operands */
return reason;
if (op_ds [entry] != OP_N) {
reason = cpu_ops (op_ds[entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* did the evaluation fail? */
return reason; /* return the reason for failure */
}
switch (entry) { /* decode IR<3:0> */
@ -191,23 +194,23 @@ switch (IR) {
switch ((IR >> 4) & 037) { /* decode IR<8:4> */
/* case 000: *//* 105000-105017 */
/* return cpu_user_00 (IR, intrq); *//* uncomment to handle instruction */
/* case 000: ** 105000-105017 */
/* return cpu_user_00 (IR, intrq); ** uncomment to handle instruction */
/* case 001: *//* 105020-105037 */
/* return cpu_user_01 (IR, intrq); *//* uncomment to handle instruction */
/* case 001: ** 105020-105037 */
/* return cpu_user_01 (IR, intrq); ** uncomment to handle instruction */
/* case 0nn: *//* other cases as needed */
/* return cpu_user_nn (IR, intrq); *//* uncomment to handle instruction */
/* case 0nn: ** other cases as needed */
/* return cpu_user_nn (IR, intrq); ** uncomment to handle instruction */
case 020: /* 10x400-10x417 */
return cpu_user_20 (IR, intrq); /* call sample dispatcher */
/* case 021: *//* 10x420-10x437 */
/* return cpu_user_21 (IR, intrq); *//* uncomment to handle instruction */
/* case 021: ** 10x420-10x437 */
/* return cpu_user_21 (IR, intrq); ** uncomment to handle instruction */
/* case 0nn: *//* other cases as needed */
/* return cpu_user_nn (IR, intrq); *//* uncomment to handle instruction */
/* case 0nn: ** other cases as needed */
/* return cpu_user_nn (IR, intrq); ** uncomment to handle instruction */
default: /* others undefined */
reason = stop_inst;
@ -243,20 +246,22 @@ uint32 entry;
entry = IR & 017; /* mask to entry point */
if (op_user_20 [entry] != OP_N)
if ((reason = cpu_ops (op_user_20 [entry], op, intrq))) /* get instruction operands */
return reason;
if (op_user_20 [entry] != OP_N) {
reason = cpu_ops (op_user_20 [entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* did the evaluation fail? */
return reason; /* return the reason for failure */
}
switch (entry) { /* decode IR<4:0> */
case 000: /* 10x400 */
/* break; *//* uncomment to handle instruction */
/* break; ** uncomment to handle instruction */
case 001: /* 10x401 */
/* break; *//* uncomment to handle instruction */
/* break; ** uncomment to handle instruction */
/* case 0nn: *//* other cases as needed */
/* break; *//* uncomment to handle instruction */
/* case 0nn: ** other cases as needed */
/* break; ** uncomment to handle instruction */
default: /* others undefined */
reason = stop_inst;

50
HP2100/hp2100_cpu1.c
View file

@ -1,6 +1,6 @@
/* hp2100_cpu1.c: HP 2100/1000 EAU simulator and UIG dispatcher
Copyright (c) 2005-2008, Robert M. Supnik
Copyright (c) 2005-2012, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -25,6 +25,7 @@
CPU1 Extended arithmetic and optional microcode dispatchers
09-May-12 JDB Separated assignments from conditional expressions
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
05-Sep-08 JDB Moved option-present tests to UIG dispatchers
Call "user microcode" dispatcher for unclaimed UIG instructions
@ -245,14 +246,15 @@ switch ((IR >> 8) & 0377) { /* decode IR<15:8> */
case 010: /* MPY 100200 (OP_K) */
MPY:
if ((reason = cpu_ops (OP_K, op, intrq))) /* get operand */
break;
sop1 = SEXT (AR); /* sext AR */
sop2 = SEXT (op[0].word); /* sext mem */
sop1 = sop1 * sop2; /* signed mpy */
BR = (sop1 >> 16) & DMASK; /* to BR'AR */
AR = sop1 & DMASK;
O = 0; /* no overflow */
reason = cpu_ops (OP_K, op, intrq); /* get operand */
if (reason == SCPE_OK) { /* successful eval? */
sop1 = SEXT (AR); /* sext AR */
sop2 = SEXT (op[0].word); /* sext mem */
sop1 = sop1 * sop2; /* signed mpy */
BR = (sop1 >> 16) & DMASK; /* to BR'AR */
AR = sop1 & DMASK;
O = 0; /* no overflow */
}
break;
default: /* others undefined */
@ -262,9 +264,11 @@ switch ((IR >> 8) & 0377) { /* decode IR<15:8> */
break;
case 0201: /* DIV 100400 (OP_K) */
if ((reason = cpu_ops (OP_K, op, intrq))) /* get operand */
reason = cpu_ops (OP_K, op, intrq); /* get operand */
if (reason != SCPE_OK) /* eval failed? */
break;
if ((rs = qs = BR & SIGN)) { /* save divd sign, neg? */
rs = qs = BR & SIGN; /* save divd sign */
if (rs) { /* neg? */
AR = (~AR + 1) & DMASK; /* make B'A pos */
BR = (~BR + (AR == 0)) & DMASK; /* make divd pos */
}
@ -317,17 +321,19 @@ switch ((IR >> 8) & 0377) { /* decode IR<15:8> */
break;
case 0210: /* DLD 104200 (OP_D) */
if ((reason = cpu_ops (OP_D, op, intrq))) /* get operand */
break;
AR = (op[0].dword >> 16) & DMASK; /* load AR */
BR = op[0].dword & DMASK; /* load BR */
reason = cpu_ops (OP_D, op, intrq); /* get operand */
if (reason == SCPE_OK) { /* successful eval? */
AR = (op[0].dword >> 16) & DMASK; /* load AR */
BR = op[0].dword & DMASK; /* load BR */
}
break;
case 0211: /* DST 104400 (OP_A) */
if ((reason = cpu_ops (OP_A, op, intrq))) /* get operand */
break;
WriteW (op[0].word, AR); /* store AR */
WriteW ((op[0].word + 1) & VAMASK, BR); /* store BR */
reason = cpu_ops (OP_A, op, intrq); /* get operand */
if (reason == SCPE_OK) { /* successful eval? */
WriteW (op[0].word, AR); /* store AR */
WriteW ((op[0].word + 1) & VAMASK, BR); /* store BR */
}
break;
default: /* should never get here */
@ -733,9 +739,11 @@ uint32 i, MA;
for (i = 0; i < OP_N_F; i++) {
flags = pattern & OP_M_FLAGS; /* get operand pattern */
if (flags >= OP_ADR) /* address operand? */
if ((reason = resolve (ReadW (PC), &MA, irq))) /* resolve indirects */
if (flags >= OP_ADR) { /* address operand? */
reason = resolve (ReadW (PC), &MA, irq); /* resolve indirects */
if (reason != SCPE_OK) /* resolution failed? */
return reason;
}
switch (flags) {
case OP_NUL: /* null operand */

30
HP2100/hp2100_cpu2.c
View file

@ -1,6 +1,6 @@
/* hp2100_cpu2.c: HP 2100/1000 FP/DMS/EIG/IOP instructions
Copyright (c) 2005-2008, Robert M. Supnik
Copyright (c) 2005-2012, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -26,6 +26,7 @@
CPU2 Floating-point, dynamic mapping, extended, and I/O processor
instructions
09-May-12 JDB Separated assignments from conditional expressions
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers)
05-Aug-08 JDB Updated mp_dms_jmp calling sequence
@ -243,9 +244,12 @@ uint32 i, t, mapi, mapj;
absel = (IR & I_AB)? 1: 0; /* get A/B select */
entry = IR & 037; /* mask to entry point */
if (op_dms[entry] != OP_N)
if ((reason = cpu_ops (op_dms[entry], op, intrq))) /* get instruction operands */
return reason;
if (op_dms [entry] != OP_N) {
reason = cpu_ops (op_dms [entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
switch (entry) { /* decode IR<3:0> */
@ -609,9 +613,12 @@ int32 sop1, sop2;
absel = (IR & I_AB)? 1: 0; /* get A/B select */
entry = IR & 037; /* mask to entry point */
if (op_eig[entry] != OP_N)
if ((reason = cpu_ops (op_eig[entry], op, intrq))) /* get instruction operands */
return reason;
if (op_eig [entry] != OP_N) {
reason = cpu_ops (op_eig [entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
switch (entry) { /* decode IR<4:0> */
@ -988,9 +995,12 @@ else if (entry <= 057) /* IR = 10x440-457? */
entry = entry - 060; /* offset 10x460-477 */
if (op_iop[entry] != OP_N)
if ((reason = cpu_ops (op_iop[entry], op, intrq))) /* get instruction operands */
return reason;
if (op_iop [entry] != OP_N) {
reason = cpu_ops (op_iop [entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
switch (entry) { /* decode IR<5:0> */

36
HP2100/hp2100_cpu3.c
View file

@ -25,6 +25,7 @@
CPU3 Fast FORTRAN and Double Integer instructions
09-May-12 JDB Separated assignments from conditional expressions
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers)
05-Aug-08 JDB Updated mp_dms_jmp calling sequence
@ -185,17 +186,23 @@ int32 i;
entry = IR & 037; /* mask to entry point */
if (UNIT_CPU_MODEL != UNIT_1000_F) { /* 2100/M/E-Series? */
if (op_ffp_e[entry] != OP_N)
if ((reason = cpu_ops (op_ffp_e[entry], op, intrq)))/* get instruction operands */
return reason;
if (op_ffp_e [entry] != OP_N) {
reason = cpu_ops (op_ffp_e [entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
}
#if defined (HAVE_INT64) /* int64 support available */
else { /* F-Series */
if (op_ffp_f[entry] != OP_N)
if ((reason = cpu_ops (op_ffp_f[entry], op, intrq)))/* get instruction operands */
return reason;
if (op_ffp_f [entry] != OP_N) {
reason = cpu_ops (op_ffp_f [entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
switch (entry) { /* decode IR<4:0> */
@ -417,7 +424,8 @@ switch (entry) { /* decode IR<4:0> */
sa = op[0].word - 1;
da = ReadW (sa); /* get jump target */
if ((reason = resolve (da, &MA, intrq))) { /* resolve indirects */
reason = resolve (da, &MA, intrq); /* resolve indirects */
if (reason != SCPE_OK) { /* resolution failed? */
PC = err_PC; /* irq restarts instruction */
break;
}
@ -435,7 +443,8 @@ switch (entry) { /* decode IR<4:0> */
op[1].word = op[1].word + /* compute element offset */
(op[2].word - 1) * op[3].word;
else { /* 3-dim access */
if ((reason = cpu_ops (OP_KK, op2, intrq))) {/* get 1st, 2nd ranges */
reason = cpu_ops (OP_KK, op2, intrq); /* get 1st, 2nd ranges */
if (reason != SCPE_OK) { /* evaluation failed? */
PC = err_PC; /* irq restarts instruction */
break;
}
@ -461,7 +470,8 @@ switch (entry) { /* decode IR<4:0> */
for (j = 0; j < sc; j++) {
MA = ReadW (sa++); /* get addr of actual */
if ((reason = resolve (MA, &MA, intrq))) { /* resolve indirect */
reason = resolve (MA, &MA, intrq); /* resolve indirect */
if (reason != SCPE_OK) { /* resolution failed? */
PC = err_PC; /* irq restarts instruction */
break;
}
@ -643,9 +653,11 @@ t_stat reason = SCPE_OK;
entry = IR & 017; /* mask to entry point */
if (op_dbi[entry] != OP_N)
if ((reason = cpu_ops (op_dbi[entry], op, intrq))) /* get instruction operands */
return reason;
if (op_dbi[entry] != OP_N) {
reason = cpu_ops (op_dbi [entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
switch (entry) { /* decode IR<3:0> */

19
HP2100/hp2100_cpu4.c
View file

@ -25,6 +25,7 @@
CPU4 Floating Point Processor and Scientific Instruction Set
09-May-12 JDB Separated assignments from conditional expressions
06-Feb-12 JDB Added OPSIZE casts to fp_accum calls in .FPWR/.TPWR
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers)
@ -260,9 +261,12 @@ else
entry = opcode & 0177; /* map to <6:0> */
if (op_fpp[entry] != OP_N)
if ((reason = cpu_ops (op_fpp[entry], op, intrq))) /* get instruction operands */
return reason;
if (op_fpp [entry] != OP_N) {
reason = cpu_ops (op_fpp [entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
switch (entry) { /* decode IR<6:0> */
case 0000: /* FAD 105000 (OP_RF) */
@ -599,9 +603,12 @@ static const OP t_one = { { 0040000, 0000000, 0000000, 0000002 } }; /* DEY 1.
entry = IR & 017; /* mask to entry point */
if (op_sis[entry] != OP_N)
if ((reason = cpu_ops (op_sis[entry], op, intrq))) /* get instruction operands */
return reason;
if (op_sis [entry] != OP_N) {
reason = cpu_ops (op_sis [entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
switch (entry) { /* decode IR<3:0> */

29
HP2100/hp2100_cpu5.c
View file

@ -26,6 +26,8 @@
CPU5 RTE-6/VM and RTE-IV firmware option instructions
17-Dec-12 JDB Fixed cpu_vma_mapte to return FALSE if not a VMA program
09-May-12 JDB Separated assignments from conditional expressions
23-Mar-12 JDB Added sign extension for dim count in "cpu_ema_resolve"
28-Dec-11 JDB Eliminated unused variable in "cpu_ema_vset"
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
@ -332,8 +334,13 @@ uint32 dispatch = ReadIO(vswp,UMAP) & 01777; /* get fresh dispatch flag *
t_bool swapflag = TRUE;
if (dispatch == 0) { /* not yet set */
idext = ReadIO(idx,UMAP); /* go into IDsegment extent */
if (idext != 0) { /* is ema/vma program? */
idext = ReadIO(idx,UMAP); /* go into ID segment extent */
if (idext == 0) { /* is ema/vma program? */
swapflag = FALSE; /* no, so mark PTE as invalid */
*ptepg = (uint32) -1; /* and return an invalid page number */
}
else { /* is an EMA/VMA program */
dispatch = ReadWA(idext+1) & 01777; /* get 1st ema page: new vswp */
WriteIO(vswp,dispatch,UMAP); /* move into $VSWP */
idext2 = ReadWA(idext+2); /* get swap bit */
@ -346,7 +353,7 @@ if (dispatch) { /* some page is defined */
*ptepg = dispatch; /* return PTEPG# for later */
}
return swapflag; /* true for swap bit set */
return swapflag; /* true for valid PTE */
}
/* .LBP
@ -649,9 +656,11 @@ t_bool debug = DEBUG_PRI (cpu_dev, DEB_VMA);
entry = IR & 017; /* mask to entry point */
pattern = op_vma[entry]; /* get operand pattern */
if (pattern != OP_N)
if ((reason = cpu_ops (pattern, op, intrq))) /* get instruction operands */
return reason;
if (pattern != OP_N) {
reason = cpu_ops (pattern, op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
if (debug) { /* debugging? */
fprintf (sim_deb, ">>CPU VMA: IR = %06o (", IR); /* print preamble and IR */
@ -1360,9 +1369,11 @@ t_bool debug = DEBUG_PRI (cpu_dev, DEB_EMA);
entry = IR & 017; /* mask to entry point */
pattern = op_ema[entry]; /* get operand pattern */
if (pattern != OP_N)
if ((reason = cpu_ops (pattern, op, intrq))) /* get instruction operands */
return reason;
if (pattern != OP_N) {
reason = cpu_ops (pattern, op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
if (debug) { /* debugging? */
fprintf (sim_deb, ">>CPU EMA: PC = %06o, IR = %06o (", err_PC,IR); /* print preamble and IR */

28
HP2100/hp2100_cpu6.c
View file

@ -1,6 +1,6 @@
/* hp2100_cpu6.c: HP 1000 RTE-6/VM OS instructions
Copyright (c) 2006-2010, J. David Bryan
Copyright (c) 2006-2012, J. David Bryan
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -25,6 +25,7 @@
CPU6 RTE-6/VM OS instructions
09-May-12 JDB Separated assignments from conditional expressions
29-Oct-10 JDB DMA channels renamed from 0,1 to 1,2 to match documentation
18-Sep-08 JDB Corrected .SIP debug formatting
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
@ -393,11 +394,14 @@ static t_bool tbg_tick = FALSE; /* set if processing TBG
entry = IR & 017; /* mask to entry point */
pattern = op_os[entry]; /* get operand pattern */
if (pattern != OP_N)
if ((reason = cpu_ops (pattern, op, intrq))) /* get instruction operands */
return reason;
if (pattern != OP_N) {
reason = cpu_ops (pattern, op, intrq); /* get instruction operands */
tbg_tick = tbg_tick || ((IR == 0105357) && iotrap); /* set TBG interrupting flag */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
tbg_tick = tbg_tick || (IR == 0105357) && iotrap; /* set TBG interrupting flag */
debug_print = (DEBUG_PRI (cpu_dev, DEB_OS) && !tbg_tick) ||
(DEBUG_PRI (cpu_dev, DEB_OSTBG) && tbg_tick);
@ -544,7 +548,9 @@ switch (entry) { /* decode IR<3:0> */
for (i = 0; i < count; i++) {
ma = ReadW (PC); /* get operand address */
if ((reason = resolve (ma, &ma, intrq))) { /* resolve indirect */
reason = resolve (ma, &ma, intrq); /* resolve indirect */
if (reason != SCPE_OK) { /* resolution failed? */
PC = err_PC; /* IRQ restarts instruction */
break;
}
@ -620,8 +626,8 @@ switch (entry) { /* decode IR<3:0> */
while ((AR != 0) && ((AR & SIGN) == 0)) { /* end of list or bad list? */
key = ReadW ((AR + op[1].word) & VAMASK); /* get key value */
if (((E == 0) && (key == op[0].word)) || /* for E = 0, key = arg? */
((E != 0) && (key > op[0].word))) /* for E = 1, key > arg? */
if ((E == 0) && (key == op[0].word) || /* for E = 0, key = arg? */
(E != 0) && (key > op[0].word)) /* for E = 1, key > arg? */
break; /* search is done */
BR = AR; /* B = last link */
@ -710,8 +716,10 @@ switch (entry) { /* decode IR<3:0> */
ma = ReadW (sa); /* get addr of actual */
sa = (sa + 1) & VAMASK; /* increment address */
if ((reason = resolve (ma, &ma, intrq))) { /* resolve indirect */
PC = err_PC; /* irq restarts instruction */
reason = resolve (ma, &ma, intrq); /* resolve indirect */
if (reason != SCPE_OK) { /* resolution failed? */
PC = err_PC; /* irq restarts instruction */
break;
}

19
HP2100/hp2100_cpu7.c
View file

@ -26,6 +26,7 @@
CPU7 Vector Instruction Set and SIGNAL firmware
09-May-12 JDB Separated assignments from conditional expressions
06-Feb-12 JDB Corrected "opsize" parameter type in vis_abs
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers)
@ -383,16 +384,18 @@ if (entry==0) { /* retrieve sub opcode
subcode = AR; /* for reentry */
PC = (PC + 1) & VAMASK; /* bump to real argument list */
pattern = (subcode & 0400) ? OP_AAKAKK : OP_AKAKAKK; /* scalar or vector operation */
}
}
if (pattern != OP_N)
if (pattern != OP_N) {
if (op_ftnret[entry]) { /* most VIS instrs ignore RTN addr */
ret = ReadOp(PC, in_s);
rtn = rtn1 = ret.word; /* but save it just in case */
PC = (PC + 1) & VAMASK; /* move to next argument */
}
reason = cpu_ops (pattern, op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
if ((reason = cpu_ops (pattern, op, intrq))) /* get instruction operands */
return reason;
if (debug) { /* debugging? */
fprintf (sim_deb, ">>CPU VIS: IR = %06o/%06o (", /* print preamble and IR */
@ -652,9 +655,11 @@ t_bool debug = DEBUG_PRI (cpu_dev, DEB_SIG);
entry = IR & 017; /* mask to entry point */
if (op_signal[entry] != OP_N)
if ((reason = cpu_ops (op_signal[entry], op, intrq)))/* get instruction operands */
return reason;
if (op_signal [entry] != OP_N) {
reason = cpu_ops (op_signal [entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
if (debug) { /* debugging? */
fprintf (sim_deb, ">>CPU SIG: IR = %06o (", IR); /* print preamble and IR */

13
HP2100/hp2100_defs.h
View file

@ -23,6 +23,8 @@
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
14-Dec-12 JDB Added "-Wbitwise-op-parentheses" to the suppression pragmas
12-May-12 JDB Added pragmas to suppress logical operator precedence warnings
10-Feb-12 JDB Added hp_setsc, hp_showsc functions to support SC modifier
28-Mar-11 JDB Tidied up signal handling
29-Oct-10 JDB DMA channels renamed from 0,1 to 1,2 to match documentation
@ -72,6 +74,16 @@
#include "sim_defs.h" /* simulator defns */
/* Required to quell clang precedence warnings */
#if defined (__GNUC__)
#pragma GCC diagnostic ignored "-Wunknown-pragmas"
#pragma GCC diagnostic ignored "-Wpragmas"
#pragma GCC diagnostic ignored "-Wlogical-op-parentheses"
#pragma GCC diagnostic ignored "-Wbitwise-op-parentheses"
#endif
/* Simulator stop and notification codes */
#define STOP_RSRV 1 /* must be 1 */
@ -455,7 +467,6 @@ extern void hp_enbdis_pair (DEVICE *ccp, DEVICE *dcp);
/* System functions */
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val, UNIT *uptr, int32 sw);
extern const char *fmt_char (uint8 ch);
extern t_stat hp_setsc (UNIT *uptr, int32 val, char *cptr, void *desc);
extern t_stat hp_showsc (FILE *st, UNIT *uptr, int32 val, void *desc);

38
HP2100/hp2100_di.c
View file

@ -1466,10 +1466,10 @@ if (assert != deny) /* was there any change
previous_state = di_card->srq; /* save the current SRQ state */
if (((di_card->cntl_register & CNTL_LSTN) && /* if the card is a listener */
(di_card->status_register & STAT_IRL)) || /* and the input register is loaded, */
((di_card->cntl_register & CNTL_TALK) && /* or the card is a talker */
! FIFO_FULL)) /* and the FIFO is not full */
if (di_card->cntl_register & CNTL_LSTN /* if the card is a listener */
&& di_card->status_register & STAT_IRL /* and the input register is loaded, */
|| di_card->cntl_register & CNTL_TALK /* or the card is a talker */
&& ! FIFO_FULL) /* and the FIFO is not full */
di_card->srq = SET; /* then request a DCPC cycle */
else
di_card->srq = CLEAR; /* otherwise, DCPC service is not needed */
@ -1481,21 +1481,21 @@ if (DEBUG_PRJ (dptrs [card], DEB_CMDS)
dptrs [card]->name, di_card->srq == SET ? "set" : "cleared");
if (((di_card->status_register & STAT_IRL) && /* is the input register loaded */
(di_card->cntl_register & CNTL_IRL)) || /* and notification is wanted? */
((di_card->status_register & STAT_LBO) && /* or is the last byte out */
(di_card->cntl_register & CNTL_LBO)) || /* and notification is wanted? */
((di_card->eor == SET) && /* or was the end of record seen */
!(di_card->status_register & STAT_IRL)) || /* and the input register was unloaded? */
((di_card->bus_cntl & BUS_SRQ) && /* or is SRQ asserted on the bus */
(di_card->cntl_register & CNTL_SRQ) && /* and notification is wanted */
(di_card->cntl_register & CNTL_CIC)) || /* and the card is not controller? */
(!SW8_SYSCTL && /* or is the card not the system controller */
(di_card->bus_cntl & BUS_REN) && /* and REN is asserted on the bus */
(di_card->cntl_register & CNTL_REN)) || /* and notification is wanted? */
(!SW8_SYSCTL && /* or is the card not the system controller */
(di_card->status_register & STAT_IFC) && /* and IFC is asserted on the bus */
(di_card->cntl_register & CNTL_IFC))) { /* and notification is wanted? */
if (di_card->status_register & STAT_IRL /* is the input register loaded */
&& di_card->cntl_register & CNTL_IRL /* and notification is wanted? */
|| di_card->status_register & STAT_LBO /* or is the last byte out */
&& di_card->cntl_register & CNTL_LBO /* and notification is wanted? */
|| di_card->eor == SET /* or was the end of record seen */
&& !(di_card->status_register & STAT_IRL) /* and the input register was unloaded? */
|| di_card->bus_cntl & BUS_SRQ /* or is SRQ asserted on the bus */
&& di_card->cntl_register & CNTL_SRQ /* and notification is wanted */
&& di_card->cntl_register & CNTL_CIC /* and the card is not controller? */
|| !SW8_SYSCTL /* or is the card not the system controller */
&& di_card->bus_cntl & BUS_REN /* and REN is asserted on the bus */
&& di_card->cntl_register & CNTL_REN /* and notification is wanted? */
|| !SW8_SYSCTL /* or is the card not the system controller */
&& di_card->status_register & STAT_IFC /* and IFC is asserted on the bus */
&& di_card->cntl_register & CNTL_IFC) { /* and notification is wanted? */
if (DEBUG_PRJ (dptrs [card], DEB_CMDS))
fprintf (sim_deb, ">>%s cmds: Flag set\n",

27
HP2100/hp2100_di_da.c
View file

@ -25,6 +25,8 @@
DA 12821A Disc Interface with Amigo disc drives
24-Oct-12 JDB Changed CNTLR_OPCODE to title case to avoid name clash
07-May-12 JDB Cancel the intersector delay if an untalk is received
29-Mar-12 JDB First release
04-Nov-11 JDB Created DA device
@ -756,7 +758,7 @@ switch (if_state [unit]) { /* dispatch the inte
case disc_command: /* execute a disc command */
result = dl_service_drive (cvptr, uptr); /* service the disc unit */
if (cvptr->opcode == clear) /* is this a Clear command? */
if (cvptr->opcode == Clear) /* is this a Clear command? */
if_dsj [unit] = 2; /* indicate that the self test is complete */
if (cvptr->state != cntlr_busy) { /* has the controller stopped? */
@ -856,7 +858,7 @@ switch (if_state [unit]) { /* dispatch the inte
if (cvptr->length == 0 || cvptr->eod == SET) { /* is the data phase complete? */
uptr->PHASE = end_phase; /* set the end phase */
if (cvptr->opcode == request_status) /* is it a Request Status command? */
if (cvptr->opcode == Request_Status) /* is it a Request Status command? */
if_dsj [unit] = 0; /* clear the DSJ value */
if_state [unit] = command_exec; /* set to execute the command */
@ -980,7 +982,7 @@ if (result == SCPE_IERR && DEBUG_PRI (da_dev, DEB_RWSC)) { /* did an internal e
if (if_state [unit] == idle) { /* is the command now complete? */
if (if_command [unit] == disc_command) { /* did a disc command complete? */
if (cvptr->opcode != end) /* yes; if the command was not End, */
if (cvptr->opcode != End) /* yes; if the command was not End, */
di_poll_response (da, unit, SET); /* then enable PPR */
if (DEBUG_PRI (da_dev, DEB_RWSC))
@ -1266,7 +1268,7 @@ result = dl_load_unload (&icd_cntlr [unit], uptr, load); /* load or unload th
if (result == SCPE_OK && ! load) { /* was the unload successful? */
icd_cntlr [unit].status = drive_attention; /* set Drive Attention status */
if (uptr->OP == end) /* is the controller in idle state 2? */
if (uptr->OP == End) /* is the controller in idle state 2? */
di_poll_response (da, unit, SET); /* enable PPR */
}
@ -1594,10 +1596,10 @@ if (di [da].bus_cntl & BUS_ATN) { /* is it a bus comma
da_unit [unit].wait = icd_cntlr [unit].cmd_time; /* these are always scheduled and */
initiated = TRUE; /* logged as initiated */
if (((if_state [unit] == read_wait) && /* if we're waiting for a send data secondary */
(message_address != 0x00)) || /* but it's not there */
((if_state [unit] == status_wait) && /* or a send status secondary, */
(message_address != 0x08))) /* but it's not there */
if (if_state [unit] == read_wait /* if we're waiting for a send data secondary */
&& message_address != 0x00 /* but it's not there */
|| if_state [unit] == status_wait /* or a send status secondary, */
&& message_address != 0x08) /* but it's not there */
abort_command (unit, io_program_error, /* then abort the pending command */
idle); /* and process the new command */
@ -1962,6 +1964,11 @@ return;
2. There is no need to test if we are processing a disc command, as the
controller would not be busy otherwise.
3. If an auto-seek will be needed to continue the read, but the seek will
fail, then an extra delay is inserted before the service call to start
the next sector. Once an Untalk is received, this delay is no longer
needed, so it is cancelled before rescheduling the service routine.
*/
static void complete_read (uint32 unit)
@ -1974,7 +1981,9 @@ if ((if_state [unit] == command_exec /* is a command exec
if_state [unit] = command_exec; /* set to execute */
da_unit [unit].PHASE = end_phase; /* the completion phase */
da_unit [unit].wait = icd_cntlr [unit].data_time; /* ensure that the controller will finish */
sim_cancel (&da_unit [unit]); /* cancel the EOT delay */
da_unit [unit].wait = icd_cntlr [unit].data_time; /* reschedule for completion */
}
return;

25
HP2100/hp2100_dp.c
View file

@ -26,6 +26,8 @@
DP 12557A 2871 disk subsystem
13210A 7900 disk subsystem
18-Dec-12 MP Now calls sim_activate_time to get remaining seek time
09-May-12 JDB Separated assignments from conditional expressions
10-Feb-12 JDB Deprecated DEVNO in favor of SC
Added CNTLR_TYPE cast to dp_settype
28-Mar-11 JDB Tidied up signal handling
@ -190,7 +192,7 @@
#define STA_PROT 0002000 /* protected (13210) */
#define STA_SKI 0001000 /* incomplete NI (u) */
#define STA_SKE 0000400 /* seek error */
/* 0000200 *//* unused */
/* 0000200 (unused) */
#define STA_NRDY 0000100 /* not ready (d) */
#define STA_EOC 0000040 /* end of cylinder */
#define STA_AER 0000020 /* addr error */
@ -694,7 +696,8 @@ void dp_goc (int32 fnc, int32 drv, int32 time)
{
int32 t;
if ((t = sim_is_active (&dpc_unit[drv]))) { /* still seeking? */
t = sim_activate_time (&dpc_unit[drv]);
if (t) { /* still seeking? */
sim_cancel (&dpc_unit[drv]); /* stop seek */
dpc_sta[drv] = dpc_sta[drv] & ~STA_BSY; /* clear busy */
time = time + t; /* include seek time */
@ -906,10 +909,13 @@ switch (uptr->FNC) { /* case function */
dpc_rarh = dpc_rarh ^ 1; /* incr head */
dpc_eoc = ((dpc_rarh & 1) == 0); /* calc eoc */
}
if ((err = fseek (uptr->fileref, da * sizeof (int16),
SEEK_SET))) break;
err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET);
if (err) /* error? */
break;
fxread (dpxb, sizeof (int16), DP_NUMWD, uptr->fileref);
if ((err = ferror (uptr->fileref))) break;
err = ferror (uptr->fileref);
if (err) /* error? */
break;
}
dpd_ibuf = dpxb[dp_ptr++]; /* get word */
if (dp_ptr >= DP_NUMWD) { /* end of sector? */
@ -953,10 +959,13 @@ switch (uptr->FNC) { /* case function */
dpc_rarh = dpc_rarh ^ 1; /* incr head */
dpc_eoc = ((dpc_rarh & 1) == 0); /* calc eoc */
}
if ((err = fseek (uptr->fileref, da * sizeof (int16),
SEEK_SET))) break;
err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET);
if (err) /* error? */
break;
fxwrite (dpxb, sizeof (int16), DP_NUMWD, uptr->fileref);
if ((err = ferror (uptr->fileref))) break; /* error? */
err = ferror (uptr->fileref);
if (err) /* error? */
break;
dp_ptr = 0; /* next sector */
}
if (dpd.command && dpd_xfer) /* dch on, xfer? */

26
HP2100/hp2100_dq.c
View file

@ -26,6 +26,8 @@
DQ 12565A 2883 disk system
18-Dec-12 MP Now calls sim_activate_time to get remaining seek time
09-May-12 JDB Separated assignments from conditional expressions
10-Feb-12 JDB Deprecated DEVNO in favor of SC
28-Mar-11 JDB Tidied up signal handling
26-Oct-10 JDB Changed I/O signal handler for revised signal model
@ -100,7 +102,7 @@
#define CW_V_FNC 12 /* function */
#define CW_M_FNC 017
#define CW_GETFNC(x) (((x) >> CW_V_FNC) & CW_M_FNC)
/* 000 *//* unused */
/* 000 (unused) */
#define FNC_STA 001 /* status check */
#define FNC_RCL 002 /* recalibrate */
#define FNC_SEEK 003 /* seek */
@ -530,7 +532,9 @@ void dq_goc (int32 fnc, int32 drv, int32 time)
{
int32 t;
if ((t = sim_is_active (&dqc_unit[drv]))) { /* still seeking? */
t = sim_activate_time (&dqc_unit[drv]);
if (t) { /* still seeking? */
sim_cancel (&dqc_unit[drv]); /* cancel */
time = time + t; /* include seek time */
}
@ -740,10 +744,13 @@ switch (uptr->FNC) { /* case function */
dqc_rars = (dqc_rars + 1) % DQ_NUMSC; /* incr sector */
if (dqc_rars == 0) /* wrap? incr head */
dqc_uhed[drv] = dqc_rarh = dqc_rarh + 1;
if ((err = fseek (uptr->fileref, da * sizeof (int16),
SEEK_SET))) break;
err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET);
if (err)
break;
fxread (dqxb, sizeof (int16), DQ_NUMWD, uptr->fileref);
if ((err = ferror (uptr->fileref))) break;
err = ferror (uptr->fileref);
if (err)
break;
}
dqd_ibuf = dqxb[dq_ptr++]; /* get word */
if (dq_ptr >= DQ_NUMWD) { /* end of sector? */
@ -786,10 +793,13 @@ switch (uptr->FNC) { /* case function */
dqc_rars = (dqc_rars + 1) % DQ_NUMSC; /* incr sector */
if (dqc_rars == 0) /* wrap? incr head */
dqc_uhed[drv] = dqc_rarh = dqc_rarh + 1;
if ((err = fseek (uptr->fileref, da * sizeof (int16),
SEEK_SET))) return TRUE;
err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET);
if (err)
break;
fxwrite (dqxb, sizeof (int16), DQ_NUMWD, uptr->fileref);
if ((err = ferror (uptr->fileref))) break;
err = ferror (uptr->fileref);
if (err)
break;
dq_ptr = 0;
}
if (dqd.command && dqd_xfer) { /* dch on, xfer? */

57
HP2100/hp2100_ds.c
View file

@ -26,6 +26,7 @@
DS 13037D/13175D disc controller/interface
24-Oct-12 JDB Changed CNTLR_OPCODE to title case to avoid name clash
29-Mar-12 JDB Rewritten to use the MAC/ICD disc controller library
ioIOO now notifies controller service of parameter output
14-Feb-12 JDB Corrected SRQ generation and FIFO under/overrun detection
@ -705,10 +706,10 @@ result = dl_service_drive (&mac_cntlr, uptr); /* service the drive */
if ((CNTLR_PHASE) uptr->PHASE == data_phase) /* is the drive in the data phase? */
switch ((CNTLR_OPCODE) uptr->OP) { /* dispatch the current operation */
case read: /* read operations */
case read_full_sector:
case read_with_offset:
case read_without_verify:
case Read: /* read operations */
case Read_Full_Sector:
case Read_With_Offset:
case Read_Without_Verify:
if (mac_cntlr.length == 0 || ds.edt == SET) { /* is the data phase complete? */
mac_cntlr.eod = ds.edt; /* set EOD if DCPC is done */
uptr->PHASE = end_phase; /* set the end phase */
@ -729,9 +730,9 @@ if ((CNTLR_PHASE) uptr->PHASE == data_phase) /* is the drive in the d
break;
case write: /* write operations */
case write_full_sector:
case initialize:
case Write: /* write operations */
case Write_Full_Sector:
case Initialize:
if (entry_phase == start_phase) { /* is this the phase transition? */
ds.srq = SET; /* start the DCPC transfer */
ds_io (&ds_dib, ioSIR, 0); /* and recalculate the interrupts */
@ -850,19 +851,19 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the current
case end_phase: /* start and end on the same phase */
switch (opcode) { /* dispatch the current operation */
case request_status:
case request_sector_address:
case address_record:
case request_syndrome:
case load_tio_register:
case request_disc_address:
case end:
case Request_Status:
case Request_Sector_Address:
case Address_Record:
case Request_Syndrome:
case Load_TIO_Register:
case Request_Disc_Address:
case End:
break; /* complete the operation without setting the flag */
case clear:
case set_file_mask:
case wakeup:
case Clear:
case Set_File_Mask:
case Wakeup:
ds_io (&ds_dib, ioENF, 0); /* complete the operation and set the flag */
break;
@ -877,11 +878,11 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the current
case data_phase:
switch (opcode) { /* dispatch the current operation */
case seek: /* operations that accept parameters */
case verify:
case address_record:
case read_with_offset:
case load_tio_register:
case Seek: /* operations that accept parameters */
case Verify:
case Address_Record:
case Read_With_Offset:
case Load_TIO_Register:
buffer [mac_cntlr.index++] = fifo_unload (); /* unload the next word from the FIFO */
mac_cntlr.length--; /* count it */
@ -891,7 +892,7 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the current
else { /* all parameters have been received */
uptr->PHASE = end_phase; /* set the end phase */
if (opcode == read_with_offset) /* a Read With Offset command sets the flag */
if (opcode == Read_With_Offset) /* a Read With Offset command sets the flag */
ds_io (&ds_dib, ioENF, 0); /* to indicate that offsetting is complete */
start_command (); /* the command is now ready to execute */
@ -899,10 +900,10 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the current
break;
case request_status: /* operations that supply parameters */
case request_sector_address:
case request_syndrome:
case request_disc_address:
case Request_Status: /* operations that supply parameters */
case Request_Sector_Address:
case Request_Syndrome:
case Request_Disc_Address:
if (mac_cntlr.length) { /* are there more words to return? */
fifo_load (buffer [mac_cntlr.index++]); /* load the next word into the FIFO */
mac_cntlr.length--; /* count it */
@ -1258,7 +1259,7 @@ unit = GET_S1UNIT (mac_cntlr.spd_unit); /* get the (prepared) un
if (unit <= DL_MAXDRIVE) /* is the unit number valid? */
drive_command = (CNTLR_OPCODE) ds_unit [unit].OP; /* get the opcode from the unit that will be used */
else /* the unit is invalid, so the command will not start */
drive_command = end; /* but the compiler doesn't know this! */
drive_command = End; /* but the compiler doesn't know this! */
uptr = dl_start_command (&mac_cntlr, ds_unit, DL_MAXDRIVE); /* ask the controller to start the command */

49
HP2100/hp2100_ipl.c
View file

@ -25,6 +25,8 @@
IPLI, IPLO 12875A interprocessor link
25-Oct-12 JDB Removed DEV_NET to allow restoration of listening ports
09-May-12 JDB Separated assignments from conditional expressions
10-Feb-12 JDB Deprecated DEVNO in favor of SC
Added CARD_INDEX casts to dib.card_index
07-Apr-11 JDB A failed STC may now be retried
@ -187,7 +189,7 @@ DEVICE ipli_dev = {
1, 10, 31, 1, 16, 16,
&tmxr_ex, &tmxr_dep, &ipl_reset,
&ipl_boot, &ipl_attach, &ipl_detach,
&ipli_dib, DEV_NET | DEV_DISABLE | DEV_DIS | DEV_DEBUG,
&ipli_dib, DEV_DISABLE | DEV_DIS | DEV_DEBUG,
0, ipl_deb, NULL, NULL
};
@ -216,7 +218,7 @@ DEVICE iplo_dev = {
1, 10, 31, 1, 16, 16,
&tmxr_ex, &tmxr_dep, &ipl_reset,
&ipl_boot, &ipl_attach, &ipl_detach,
&iplo_dib, DEV_NET | DEV_DISABLE | DEV_DIS | DEV_DEBUG,
&iplo_dib, DEV_DISABLE | DEV_DIS | DEV_DEBUG,
0, ipl_deb, NULL, NULL
};
@ -569,61 +571,62 @@ return SCPE_OK;
t_stat ipl_attach (UNIT *uptr, char *cptr)
{
SOCKET newsock;
uint32 i, t, ipa, ipp, oldf;
char *tptr;
uint32 i, t, oldf;
char host[CBUFSIZE], port[CBUFSIZE], hostport[2*CBUFSIZE+3];
char *tptr = NULL;
t_stat r;
r = get_ipaddr (cptr, &ipa, &ipp);
if ((r != SCPE_OK) || (ipp == 0))
return SCPE_ARG;
oldf = uptr->flags;
if (oldf & UNIT_ATT)
ipl_detach (uptr);
if ((sim_switches & SWMASK ('C')) ||
((sim_switches & SIM_SW_REST) && (oldf & UNIT_ACTV))) {
if (ipa == 0)
ipa = 0x7F000001;
newsock = sim_connect_sock (ipa, ipp);
r = sim_parse_addr (cptr, host, sizeof(host), "localhost", port, sizeof(port), NULL, NULL);
if ((r != SCPE_OK) || (port[0] == '\0'))
return SCPE_ARG;
sprintf(hostport, "%s%s%s%s%s", strchr(host, ':') ? "[" : "", host, strchr(host, ':') ? "]" : "", host[0] ? ":" : "", port);
newsock = sim_connect_sock (hostport, NULL, NULL);
if (newsock == INVALID_SOCKET)
return SCPE_IOERR;
printf ("Connecting to IP address %d.%d.%d.%d, port %d\n",
(ipa >> 24) & 0xff, (ipa >> 16) & 0xff,
(ipa >> 8) & 0xff, ipa & 0xff, ipp);
printf ("Connecting to %s\n", hostport);
if (sim_log)
fprintf (sim_log,
"Connecting to IP address %d.%d.%d.%d, port %d\n",
(ipa >> 24) & 0xff, (ipa >> 16) & 0xff,
(ipa >> 8) & 0xff, ipa & 0xff, ipp);
"Connecting to %s\n", hostport);
uptr->flags = uptr->flags | UNIT_ACTV;
uptr->LSOCKET = 0;
uptr->DSOCKET = newsock;
}
else {
if (ipa != 0)
r = sim_parse_addr (cptr, host, sizeof(host), NULL, port, sizeof(port), NULL, NULL);
if (r != SCPE_OK)
return SCPE_ARG;
newsock = sim_master_sock (ipp);
sprintf(hostport, "%s%s%s%s%s", strchr(host, ':') ? "[" : "", host, strchr(host, ':') ? "]" : "", host[0] ? ":" : "", port);
newsock = sim_master_sock (hostport, &r);
if (r != SCPE_OK)
return r;
if (newsock == INVALID_SOCKET)
return SCPE_IOERR;
printf ("Listening on port %d\n", ipp);
printf ("Listening on port %s\n", hostport);
if (sim_log)
fprintf (sim_log, "Listening on port %d\n", ipp);
fprintf (sim_log, "Listening on port %s\n", hostport);
uptr->flags = uptr->flags & ~UNIT_ACTV;
uptr->LSOCKET = newsock;
uptr->DSOCKET = 0;
}
uptr->IBUF = uptr->OBUF = 0;
uptr->flags = (uptr->flags | UNIT_ATT) & ~(UNIT_ESTB | UNIT_HOLD);
tptr = (char *) malloc (strlen (cptr) + 1); /* get string buf */
tptr = (char *) malloc (strlen (hostport) + 1); /* get string buf */
if (tptr == NULL) { /* no memory? */
ipl_detach (uptr); /* close sockets */
return SCPE_MEM;
}
strcpy (tptr, cptr); /* copy ipaddr:port */
strcpy (tptr, hostport); /* copy ipaddr:port */
uptr->filename = tptr; /* save */
sim_activate (uptr, POLL_FIRST); /* activate first poll "immediately" */
if (sim_switches & SWMASK ('W')) { /* wait? */
for (i = 0; i < 30; i++) { /* check for 30 sec */
if ((t = ipl_check_conn (uptr))) /* established? */
t = ipl_check_conn (uptr);
if (t) /* established? */
break;
if ((i % 10) == 0) /* status every 10 sec */
printf ("Waiting for connnection\n");

31
HP2100/hp2100_mpx.c
View file

@ -25,7 +25,9 @@
MPX 12792C 8-channel multiplexer card
28-Dec-12 JDB Allow direct attach to the poll unit only when restoring
10-Feb-12 JDB Deprecated DEVNO in favor of SC
Removed DEV_NET to allow restoration of listening port
28-Mar-11 JDB Tidied up signal handling
26-Oct-10 JDB Changed I/O signal handler for revised signal model
25-Nov-08 JDB Revised for new multiplexer library SHOW routines
@ -743,11 +745,14 @@ DEVICE mpx_dev = {
&mpx_attach, /* attach routine */
&mpx_detach, /* detach routine */
&mpx_dib, /* device information block */
DEV_DEBUG | DEV_DISABLE, /* device flags */
DEV_DEBUG | DEV_DISABLE | DEV_MUX, /* device flags */
0, /* debug control flags */
mpx_deb, /* debug flag name table */
NULL, /* memory size change routine */
NULL }; /* logical device name */
NULL, /* logical device name */
NULL, /* help routine */
NULL, /* help attach routine*/
(void*)&mpx_desc }; /* help context */
/* I/O signal handler.
@ -1926,8 +1931,8 @@ if (fast_binary_read) { /* fast binary read
else { /* normal service */
tmxr_poll_tx (&mpx_desc); /* output any accumulated characters */
if (((buf_avail (iowrite, port) < 2) && /* more to transmit? */
!(mpx_flags [port] & (FL_WAITACK | FL_XOFF))) || /* and transmission not suspended */
if ((buf_avail (iowrite, port) < 2) && /* more to transmit? */
!(mpx_flags [port] & (FL_WAITACK | FL_XOFF)) || /* and transmission not suspended */
tmxr_rqln (&mpx_ldsc [port])) /* or more to receive? */
sim_activate (uptr, uptr->wait); /* reschedule service */
else
@ -2057,6 +2062,9 @@ return SCPE_OK;
unit is not allowed, so we first enable the unit, then attach it, then
disable it again. Attachment is reported by the "mpx_status" routine below.
A direct attach to the poll unit is only allowed when restoring a previously
saved session.
The Telnet poll service routine is synchronized with the other input polling
devices in the simulator to facilitate idling.
*/
@ -2065,16 +2073,17 @@ t_stat mpx_attach (UNIT *uptr, char *cptr)
{
t_stat status = SCPE_OK;
if (uptr != mpx_unit) /* not unit 0? */
return SCPE_NOATT; /* can't attach */
if (uptr != mpx_unit /* not unit 0? */
&& (uptr != &mpx_poll || !(sim_switches & SIM_SW_REST))) /* and not restoring the poll unit? */
return SCPE_NOATT; /* can't attach */
mpx_poll.flags = mpx_poll.flags & ~UNIT_DIS; /* enable unit */
status = tmxr_attach (&mpx_desc, &mpx_poll, cptr); /* attach to socket */
mpx_poll.flags = mpx_poll.flags | UNIT_DIS; /* disable unit */
mpx_poll.flags = mpx_poll.flags & ~UNIT_DIS; /* enable unit */
status = tmxr_attach (&mpx_desc, &mpx_poll, cptr); /* attach to socket */
mpx_poll.flags = mpx_poll.flags | UNIT_DIS; /* disable unit */
if (status == SCPE_OK) {
mpx_poll.wait = POLL_FIRST; /* set up poll */
sim_activate (&mpx_poll, mpx_poll.wait); /* start poll immediately */
mpx_poll.wait = POLL_FIRST; /* set up poll */
sim_activate (&mpx_poll, mpx_poll.wait); /* start poll immediately */
}
return status;
}

29
HP2100/hp2100_ms.c
View file

@ -26,6 +26,7 @@
MS 13181A 7970B 800bpi nine track magnetic tape
13183A 7970E 1600bpi nine track magnetic tape
09-May-12 JDB Separated assignments from conditional expressions
10-Feb-12 JDB Deprecated DEVNO in favor of SC
Added CNTLR_TYPE cast to ms_settype
28-Mar-11 JDB Tidied up signal handling
@ -374,7 +375,7 @@ DEVICE msc_dev = {
MS_NUMDR, 10, 31, 1, 8, 8,
NULL, NULL, &msc_reset,
&msc_boot, &msc_attach, &msc_detach,
&msc_dib, DEV_DISABLE | DEV_DEBUG,
&msc_dib, DEV_DISABLE | DEV_DEBUG | DEV_TAPE,
0, msc_deb, NULL, NULL
};
@ -737,7 +738,8 @@ switch (uptr->FNC) { /* case on function */
fprintf (sim_deb,
">>MSC svc: Unit %d wrote initial gap\n",
unum);
if ((st = ms_write_gap (uptr))) { /* write initial gap; error? */
st = ms_write_gap (uptr); /* write initial gap*/
if (st != MTSE_OK) { /* error? */
r = ms_map_err (uptr, st); /* map error */
break; /* terminate operation */
}
@ -747,13 +749,15 @@ switch (uptr->FNC) { /* case on function */
fprintf (sim_deb,
">>MSC svc: Unit %d wrote file mark\n",
unum);
if ((st = sim_tape_wrtmk (uptr))) /* write tmk, err? */
st = sim_tape_wrtmk (uptr); /* write tmk */
if (st != MTSE_OK) /* error? */
r = ms_map_err (uptr, st); /* map error */
msc_sta = STA_EOF; /* set EOF status */
break;
case FNC_FSR: /* space forward */
if ((st = sim_tape_sprecf (uptr, &tbc))) /* space rec fwd, err? */
st = sim_tape_sprecf (uptr, &tbc); /* space rec fwd */
if (st != MTSE_OK) /* error? */
r = ms_map_err (uptr, st); /* map error */
if (tbc & 1)
msc_sta = msc_sta | STA_ODD;
@ -761,7 +765,8 @@ switch (uptr->FNC) { /* case on function */
break;
case FNC_BSR: /* space reverse */
if ((st = sim_tape_sprecr (uptr, &tbc))) /* space rec rev, err? */
st = sim_tape_sprecr (uptr, &tbc); /* space rec rev*/
if (st != MTSE_OK) /* error? */
r = ms_map_err (uptr, st); /* map error */
if (tbc & 1)
msc_sta = msc_sta | STA_ODD;
@ -831,7 +836,8 @@ switch (uptr->FNC) { /* case on function */
fprintf (sim_deb,
">>MSC svc: Unit %d wrote initial gap\n",
unum);
if ((st = ms_write_gap (uptr))) { /* write initial gap; error? */
st = ms_write_gap (uptr); /* write initial gap */
if (st != MTSE_OK) { /* error? */
r = ms_map_err (uptr, st); /* map error */
break; /* terminate operation */
}
@ -855,7 +861,8 @@ switch (uptr->FNC) { /* case on function */
fprintf (sim_deb,
">>MSC svc: Unit %d wrote %d word record\n",
unum, ms_ptr / 2);
if ((st = sim_tape_wrrecf (uptr, msxb, ms_ptr))) { /* write, err? */
st = sim_tape_wrrecf (uptr, msxb, ms_ptr); /* write */
if (st != MTSE_OK) {
r = ms_map_err (uptr, st); /* map error */
break;
}
@ -894,7 +901,9 @@ t_stat st;
uint32 gap_len = ms_ctype ? GAP_13183 : GAP_13181; /* establish gap length */
uint32 tape_bpi = ms_ctype ? BPI_13183 : BPI_13181; /* establish nominal bpi */
if ((st = sim_tape_wrgap (uptr, gap_len, tape_bpi))) /* write gap */
st = sim_tape_wrgap (uptr, gap_len, tape_bpi); /* write gap */
if (st != MTSE_OK)
return ms_map_err (uptr, st); /* map error if failure */
else
return SCPE_OK;
@ -974,7 +983,9 @@ for (i = 0; i < MS_NUMDR; i++) { /* look for write in pro
fprintf (sim_deb,
">>MSC rws: Unit %d wrote %d word partial record\n", i, ms_ptr / 2);
if ((st = sim_tape_wrrecf (uptr, msxb, ms_ptr | MTR_ERF)))
st = sim_tape_wrrecf (uptr, msxb, ms_ptr | MTR_ERF);
if (st != MTSE_OK)
ms_map_err (uptr, st); /* discard any error */
ms_ptr = 0; /* clear partial */

18
HP2100/hp2100_mt.c
View file

@ -25,6 +25,7 @@
MT 12559A 3030 nine track magnetic tape
09-May-12 JDB Separated assignments from conditional expressions
25-Mar-12 JDB Removed redundant MTAB_VUN from "format" MTAB entry
10-Feb-12 JDB Deprecated DEVNO in favor of SC
28-Mar-11 JDB Tidied up signal handling
@ -233,7 +234,7 @@ DEVICE mtc_dev = {
1, 10, 31, 1, 8, 8,
NULL, NULL, &mt_reset,
NULL, &mtc_attach, &mtc_detach,
&mtc_dib, DEV_DISABLE | DEV_DIS
&mtc_dib, DEV_DISABLE | DEV_DIS | DEV_TAPE
};
@ -495,7 +496,8 @@ switch (mtc_fnc) { /* case on function */
return sim_tape_detach (uptr); /* don't set cch flg */
case FNC_WFM: /* write file mark */
if ((st = sim_tape_wrtmk (uptr))) /* write tmk, err? */
st = sim_tape_wrtmk (uptr); /* write tmk */
if (st != MTSE_OK) /* error? */
r = mt_map_err (uptr, st); /* map error */
mtc_sta = STA_EOF; /* set EOF status */
break;
@ -504,12 +506,14 @@ switch (mtc_fnc) { /* case on function */
break;
case FNC_FSR: /* space forward */
if ((st = sim_tape_sprecf (uptr, &tbc))) /* space rec fwd, err? */
st = sim_tape_sprecf (uptr, &tbc); /* space rec fwd */
if (st != MTSE_OK) /* error? */
r = mt_map_err (uptr, st); /* map error */
break;
case FNC_BSR: /* space reverse */
if ((st = sim_tape_sprecr (uptr, &tbc))) /* space rec rev, err? */
st = sim_tape_sprecr (uptr, &tbc); /* space rec rev */
if (st != MTSE_OK) /* error? */
r = mt_map_err (uptr, st); /* map error */
break;
@ -558,7 +562,8 @@ switch (mtc_fnc) { /* case on function */
return SCPE_OK;
}
if (mt_ptr) { /* write buffer */
if ((st = sim_tape_wrrecf (uptr, mtxb, mt_ptr))) { /* write, err? */
st = sim_tape_wrrecf (uptr, mtxb, mt_ptr); /* write */
if (st != MTSE_OK) { /* error? */
r = mt_map_err (uptr, st); /* map error */
break; /* done */
}
@ -627,7 +632,8 @@ t_stat st;
if (sim_is_active (&mtc_unit) && /* write in prog? */
(mtc_fnc == FNC_WC) && (mt_ptr > 0)) { /* yes, bad rec */
if ((st = sim_tape_wrrecf (&mtc_unit, mtxb, mt_ptr | MTR_ERF)))
st = sim_tape_wrrecf (&mtc_unit, mtxb, mt_ptr | MTR_ERF);
if (st != MTSE_OK)
mt_map_err (&mtc_unit, st);
}

18
HP2100/hp2100_mux.c
View file

@ -26,6 +26,7 @@
MUX,MUXL,MUXM 12920A terminal multiplexor
10-Feb-12 JDB Deprecated DEVNO in favor of SC
Removed DEV_NET to allow restoration of listening port
28-Mar-11 JDB Tidied up signal handling
26-Oct-10 JDB Changed I/O signal handler for revised signal model
25-Nov-08 JDB Revised for new multiplexer library SHOW routines
@ -437,7 +438,10 @@ DEVICE muxl_dev = {
0, /* debug control flags */
NULL, /* debug flag name table */
NULL, /* memory size change routine */
NULL }; /* logical device name */
NULL, /* logical device name */
NULL, /* help routine */
NULL, /* help attach routine*/
NULL }; /* help context */
/* MUXU data structures
@ -511,11 +515,14 @@ DEVICE muxu_dev = {
&mux_attach, /* attach routine */
&mux_detach, /* detach routine */
&muxu_dib, /* device information block */
DEV_DISABLE | DEV_DEBUG, /* device flags */
DEV_DISABLE | DEV_DEBUG | DEV_MUX, /* device flags */
0, /* debug control flags */
muxu_deb, /* debug flag name table */
NULL, /* memory size change routine */
NULL }; /* logical device name */
NULL, /* logical device name */
NULL, /* help routine */
NULL, /* help attach routine*/
(void*)&mux_desc }; /* help context */
/* MUXC data structures.
@ -574,7 +581,10 @@ DEVICE muxc_dev = {
0, /* debug control flags */
NULL, /* debug flag name table */
NULL, /* memory size change routine */
NULL }; /* logical device name */
NULL, /* logical device name */
NULL, /* help routine */
NULL, /* help attach routine*/
NULL }; /* help context */
/* Lower data card I/O signal handler.

20
HP2100/hp2100_stddev.c
View file

@ -26,8 +26,11 @@
PTR 12597A-002 paper tape reader interface
PTP 12597A-005 paper tape punch interface
TTY 12531C buffered teleprinter interface
CLK 12539C time base generator
TBG 12539C time base generator
28-Dec-12 JDB Allocate the TBG logical name during power-on reset
18-Dec-12 MP Now calls sim_activate_time to get remaining poll time
09-May-12 JDB Separated assignments from conditional expressions
12-Feb-12 JDB Add TBG as a logical name for the CLK device
10-Feb-12 JDB Deprecated DEVNO in favor of SC
28-Mar-11 JDB Tidied up signal handling
@ -96,7 +99,7 @@
idle time. The console poll is guaranteed to run, as the TTY device cannot
be disabled.
The clock (time base generator) autocalibrates. If the CLK is set to a ten
The clock (time base generator) autocalibrates. If the TBG is set to a ten
millisecond period (e.g., as under RTE), it is synchronized to the console
poll. Otherwise (e.g., as under DOS or TSB, which use 100 millisecond
periods), it runs asynchronously. If the specified clock frequency is below
@ -391,7 +394,7 @@ DEVICE clk_dev = {
NULL, NULL, &clk_reset,
NULL, NULL, NULL,
&clk_dib, DEV_DISABLE,
0, NULL, NULL, "TBG"
0, NULL, NULL, NULL
};
@ -942,7 +945,9 @@ t_stat r;
if (tty_mode & TM_PRI) { /* printing? */
c = sim_tt_outcvt (c, TT_GET_MODE (tty_unit[TTO].flags));
if (c >= 0) { /* valid? */
if ((r = sim_putchar_s (c))) return r; /* output char */
r = sim_putchar_s (c); /* output char */
if (r != SCPE_OK)
return r;
tty_unit[TTO].pos = tty_unit[TTO].pos + 1;
}
}
@ -1018,7 +1023,7 @@ int32 sync_poll (POLLMODE poll_mode)
int32 poll_time;
if (poll_mode == INITIAL) {
poll_time = sim_is_active (&tty_unit[TTI]);
poll_time = sim_activate_time (&tty_unit[TTI]);
if (poll_time)
return poll_time;
@ -1114,7 +1119,7 @@ while (working_set) {
if ((clk_unit.flags & UNIT_DIAG) == 0) /* calibrated? */
if (clk_select == 2) /* 10 msec. interval? */
clk_tick = sync_poll (INITIAL); /* sync poll */
clk_tick = sync_poll (INITIAL); /* sync poll */
else
sim_rtcn_init (clk_tick, TMR_CLK); /* initialize timer */
@ -1187,6 +1192,9 @@ if (sim_switches & SWMASK ('P')) { /* initialization reset?
clk_error = 0; /* clear error */
clk_select = 0; /* clear select */
clk_ctr = 0; /* clear counter */
if (clk_dev.lname == NULL) /* logical name unassigned? */
clk_dev.lname = strdup ("TBG"); /* allocate and initialize the name */
}
IOPRESET (&clk_dib); /* PRESET device (does not use PON) */

1
HP2100/hp2100_sys.c
View file

@ -23,6 +23,7 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
09-May-12 JDB Quieted warnings for assignments in conditional expressions
10-Feb-12 JDB Deprecated DEVNO in favor of SC
Added hp_setsc, hp_showsc functions to support SC modifier
15-Dec-11 JDB Added DA and dummy DC devices

272
HP2100/hp_disclib.c
View file

@ -24,7 +24,10 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from the authors.
28-Mar-12 JDB First release
20-Dec-12 JDB sim_is_active() now returns t_bool
24-Oct-12 JDB Changed CNTLR_OPCODE to title case to avoid name clash
07-May-12 JDB Corrected end-of-track delay time logic
02-May-12 JDB First release
09-Nov-11 JDB Created disc controller common library from DS simulator
References:
@ -593,8 +596,8 @@ set_timer (cvptr, CLEAR); /* stop the command wait
opcode = GET_OPCODE (cvptr->buffer [0]); /* get the opcode from the command */
if (opcode > last_opcode) /* is the opcode invalid? */
props = &cmd_props [invalid_opcode]; /* undefined commands clear prior status */
if (opcode > Last_Opcode) /* is the opcode invalid? */
props = &cmd_props [Invalid_Opcode]; /* undefined commands clear prior status */
else /* the opcode is potentially valid */
props = &cmd_props [opcode]; /* get the command properties */
@ -761,8 +764,8 @@ else { /* for an ICD controller
uptr = units + unit_limit; /* and we use the indicated unit */
}
if ((props->unit_check && !uptr) || /* if the unit number is checked and is invalid */
(props->seek_wait && (drive_status (uptr) & DL_S2STOPS))) { /* or if we're waiting for an offline drive */
if (props->unit_check && !uptr /* if the unit number is checked and is invalid */
|| props->seek_wait && (drive_status (uptr) & DL_S2STOPS)) { /* or if we're waiting for an offline drive */
dl_end_command (cvptr, status_2_error); /* then the command ends with a Status-2 error */
uptr = NULL; /* prevent the command from starting */
}
@ -771,7 +774,7 @@ else if (uptr) { /* otherwise, we have a
uptr->wait = cvptr->cmd_time; /* most commands use the command delay */
if (props->unit_access) { /* does the command access the unit? */
is_seeking = sim_is_active (uptr) != 0; /* see if the unit is busy */
is_seeking = sim_is_active (uptr); /* see if the unit is busy */
if (is_seeking) /* if a seek is in progress, */
uptr->wait = 0; /* set for no unit activation */
@ -793,7 +796,7 @@ cvptr->eod = CLEAR; /* clear the end of data
switch (cvptr->opcode) { /* dispatch the command */
case cold_load_read:
case Cold_Load_Read:
cvptr->cylinder = 0; /* set the cylinder address to 0 */
cvptr->head = GET_CHEAD (cvptr->buffer [0]); /* set the head */
cvptr->sector = GET_CSECT (cvptr->buffer [0]); /* and sector from the command */
@ -801,7 +804,7 @@ switch (cvptr->opcode) { /* dispatch the command
if (is_seeking) { /* if a seek is in progress, */
uptr->STAT |= DL_S2SC; /* a Seek Check occurs */
cvptr->file_mask = DL_FSPEN; /* enable sparing */
uptr->OP = read; /* start the read on the seek completion */
uptr->OP = Read; /* start the read on the seek completion */
uptr->PHASE = start_phase; /* and reset the command phase */
return uptr; /* to allow the seek to complete normally */
}
@ -812,7 +815,7 @@ switch (cvptr->opcode) { /* dispatch the command
break;
case seek:
case Seek:
cvptr->cylinder = cvptr->buffer [1]; /* get the supplied cylinder */
cvptr->head = GET_HEAD (cvptr->buffer [2]); /* and head */
cvptr->sector = GET_SECTOR (cvptr->buffer [2]); /* and sector addresses */
@ -826,7 +829,7 @@ switch (cvptr->opcode) { /* dispatch the command
break;
case request_status:
case Request_Status:
cvptr->buffer [0] = /* set the Status-1 value */
cvptr->spd_unit | SET_S1STAT (cvptr->status); /* into the buffer */
@ -853,12 +856,12 @@ switch (cvptr->opcode) { /* dispatch the command
break;
case request_disc_address:
case Request_Disc_Address:
set_address (cvptr, 0); /* return the CHS values in buffer 0-1 */
break;
case request_sector_address:
case Request_Sector_Address:
if (unit > unit_limit) /* if the unit number is invalid */
rptr = NULL; /* it does not correspond to a unit */
else /* otherwise, the unit is valid */
@ -871,7 +874,7 @@ switch (cvptr->opcode) { /* dispatch the command
break;
case request_syndrome:
case Request_Syndrome:
cvptr->buffer [0] = /* return the Status-1 value in buffer 0 */
cvptr->spd_unit | SET_S1STAT (cvptr->status);
@ -884,7 +887,7 @@ switch (cvptr->opcode) { /* dispatch the command
break;
case address_record:
case Address_Record:
cvptr->cylinder = cvptr->buffer [1]; /* get the supplied cylinder */
cvptr->head = GET_HEAD (cvptr->buffer [2]); /* and head */
cvptr->sector = GET_SECTOR (cvptr->buffer [2]); /* and sector addresses */
@ -892,7 +895,7 @@ switch (cvptr->opcode) { /* dispatch the command
break;
case set_file_mask:
case Set_File_Mask:
cvptr->file_mask = GET_FMASK (cvptr->buffer [0]); /* get the supplied file mask */
if (cvptr->type == MAC) /* if this is a MAC controller, */
@ -900,14 +903,14 @@ switch (cvptr->opcode) { /* dispatch the command
break;
case initialize:
case Initialize:
if (uptr) /* if the unit is valid, */
cvptr->spd_unit |= /* merge the SPD flags */
SET_S1SPD (GET_SPD (cvptr->buffer [0])); /* from the command word */
break;
case verify:
case Verify:
cvptr->verify_count = cvptr->buffer [1]; /* get the supplied sector count */
break;
@ -1077,35 +1080,35 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */
case start_phase:
switch (opcode) { /* dispatch the current operation */
case recalibrate:
case seek:
case Recalibrate:
case Seek:
if (start_seek (cvptr, uptr, opcode, end_phase) /* start the seek; if it succeeded, */
&& (cvptr->type == MAC)) /* and this a MAC controller, */
dl_idle_controller (cvptr); /* then go idle until it completes */
break;
case cold_load_read:
if (start_seek (cvptr, uptr, read, start_phase)) /* start the seek; did it succeed? */
case Cold_Load_Read:
if (start_seek (cvptr, uptr, Read, start_phase)) /* start the seek; did it succeed? */
cvptr->file_mask = DL_FSPEN; /* set sparing enabled now */
break;
case read:
case read_with_offset:
case read_without_verify:
case Read:
case Read_With_Offset:
case Read_Without_Verify:
cvptr->length = DL_WPSEC; /* transfer just the data */
result = start_read (cvptr, uptr); /* start the sector read */
break;
case read_full_sector:
case Read_Full_Sector:
cvptr->length = DL_WPFSEC; /* transfer the header/data/trailer */
result = start_read (cvptr, uptr); /* start the sector read */
break;
case verify:
case Verify:
cvptr->length = 0; /* no data transfer needed */
result = start_read (cvptr, uptr); /* start the sector read */
@ -1117,29 +1120,29 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */
break;
case write:
case initialize:
case Write:
case Initialize:
cvptr->length = DL_WPSEC; /* transfer just the data */
start_write (cvptr, uptr); /* start the sector write */
break;
case write_full_sector:
case Write_Full_Sector:
cvptr->length = DL_WPFSEC; /* transfer the header/data/trailer */
start_write (cvptr, uptr); /* start the sector write */
break;
case request_status:
case request_sector_address:
case clear:
case address_record:
case request_syndrome:
case set_file_mask:
case load_tio_register:
case request_disc_address:
case end:
case wakeup:
case Request_Status:
case Request_Sector_Address:
case Clear:
case Address_Record:
case Request_Syndrome:
case Set_File_Mask:
case Load_TIO_Register:
case Request_Disc_Address:
case End:
case Wakeup:
dl_service_controller (cvptr, uptr); /* the controller service handles these */
break;
@ -1153,13 +1156,13 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */
case data_phase:
switch (opcode) { /* dispatch the current operation */
case read:
case read_full_sector:
case read_with_offset:
case read_without_verify:
case write:
case write_full_sector:
case initialize:
case Read:
case Read_Full_Sector:
case Read_With_Offset:
case Read_Without_Verify:
case Write:
case Write_Full_Sector:
case Initialize:
break; /* data transfers are handled by the caller */
@ -1173,8 +1176,8 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */
case end_phase:
switch (opcode) { /* dispatch the operation command */
case recalibrate:
case seek:
case Recalibrate:
case Seek:
if (cvptr->type == ICD) /* is this an ICD controller? */
dl_end_command (cvptr, drive_attention); /* seeks end with Drive Attention status */
else /* if not an ICD controller, */
@ -1182,22 +1185,22 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */
break;
case read:
case read_full_sector:
case read_with_offset:
case Read:
case Read_Full_Sector:
case Read_With_Offset:
end_read (cvptr, uptr); /* end the sector read */
break;
case read_without_verify:
case Read_Without_Verify:
if (cvptr->sector == 0) /* have we reached the end of the track? */
uptr->OP = read; /* begin verifying the next time */
uptr->OP = Read; /* begin verifying the next time */
end_read (cvptr, uptr); /* end the sector read */
break;
case verify:
case Verify:
cvptr->verify_count = /* decrement the count */
(cvptr->verify_count - 1) & DMASK; /* modulo 65536 */
@ -1208,16 +1211,16 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */
break;
case write:
case write_full_sector:
case initialize:
case Write:
case Write_Full_Sector:
case Initialize:
result = end_write (cvptr, uptr); /* end the sector write */
break;
case request_status:
case request_sector_address:
case request_disc_address:
case Request_Status:
case Request_Sector_Address:
case Request_Disc_Address:
dl_service_controller (cvptr, uptr); /* the controller service handles these */
break;
@ -1277,33 +1280,33 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */
case start_phase:
case end_phase:
switch (opcode) { /* dispatch the current operation */
case request_status:
case Request_Status:
dl_end_command (cvptr, cvptr->status); /* the command completes with no status change */
break;
case clear:
case Clear:
dl_clear_controller (cvptr, uptr, soft_clear); /* clear the controller */
dl_end_command (cvptr, normal_completion); /* the command is complete */
break;
case request_sector_address:
case address_record:
case request_syndrome:
case set_file_mask:
case load_tio_register:
case request_disc_address:
case Request_Sector_Address:
case Address_Record:
case Request_Syndrome:
case Set_File_Mask:
case Load_TIO_Register:
case Request_Disc_Address:
dl_end_command (cvptr, normal_completion); /* the command is complete */
break;
case end:
case End:
dl_idle_controller (cvptr); /* the command completes with the controller idle */
break;
case wakeup:
case Wakeup:
dl_end_command (cvptr, unit_available); /* the command completes with Unit Available status */
break;
@ -1318,11 +1321,11 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */
case data_phase:
switch (opcode) { /* dispatch the current operation */
case seek:
case verify:
case address_record:
case read_with_offset:
case load_tio_register:
case Seek:
case Verify:
case Address_Record:
case Read_With_Offset:
case Load_TIO_Register:
if (cvptr->length > 1) /* at least one more parameter to input? */
set_timer (cvptr, SET); /* restart the timer for the next parameter */
else /* this is the last one */
@ -1330,10 +1333,10 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */
break;
case request_status:
case request_sector_address:
case request_syndrome:
case request_disc_address:
case Request_Status:
case Request_Sector_Address:
case Request_Syndrome:
case Request_Disc_Address:
if (cvptr->length > 0) /* at least one more to parameter output? */
set_timer (cvptr, SET); /* restart the timer for the next parameter */
else /* this is the last one */
@ -1504,8 +1507,8 @@ for (unit = 0; unit < unit_count; unit++) { /* loop through the unit
if (!(uptr->flags & UNIT_DIS)) { /* is the unit enabled? */
if (clear_type == hard_clear /* a hard clear cancels */
&& uptr->OP != seek /* only if not seeking */
&& uptr->OP != recalibrate) /* or recalibrating */
&& uptr->OP != Seek /* only if not seeking */
&& uptr->OP != Recalibrate) /* or recalibrating */
sim_cancel (uptr); /* cancel the service */
uptr->STAT &= ~DL_S2CPS; /* do "Controller Preset" for the unit */
@ -1596,7 +1599,7 @@ return SCPE_OK;
CNTLR_CLASS dl_classify (CNTLR_VARS cntlr)
{
if (cntlr.type <= last_type /* if the controller type is legal */
&& cntlr.opcode <= last_opcode /* and the opcode is legal */
&& cntlr.opcode <= Last_Opcode /* and the opcode is legal */
&& cmd_props [cntlr.opcode].valid [cntlr.type]) /* and is defined for this controller, */
return cmd_props [cntlr.opcode].classification; /* then return the command classification */
else /* the type or opcode is illegal */
@ -1614,7 +1617,7 @@ else /* the type or opcode is
const char *dl_opcode_name (CNTLR_TYPE controller, CNTLR_OPCODE opcode)
{
if (controller <= last_type /* if the controller type is legal */
&& opcode <= last_opcode /* and the opcode is legal */
&& opcode <= Last_Opcode /* and the opcode is legal */
&& cmd_props [opcode].valid [controller]) /* and is defined for this controller, */
return opcode_name [opcode]; /* then return the opcode name */
else /* the type or opcode is illegal, */
@ -1775,7 +1778,7 @@ if (cvptr->eod == SET) { /* is the end of data in
return SCPE_OK;
}
if (opcode == read_full_sector) { /* are we starting a Read Full Sector command? */
if (opcode == Read_Full_Sector) { /* are we starting a Read Full Sector command? */
if (cvptr->type == ICD) /* is this an ICD controller? */
cvptr->buffer [0] = 0100377; /* ICD does not support ECC */
else
@ -1788,7 +1791,7 @@ if (opcode == read_full_sector) { /* are we starting a Rea
else { /* it's another read command */
offset = 0; /* data starts at the beginning */
verify = (opcode != read_without_verify); /* set for address verification unless it's a RWV */
verify = (opcode != Read_Without_Verify); /* set for address verification unless it's a RWV */
}
if (! position_sector (cvptr, uptr, verify)) /* position the sector */
@ -1817,28 +1820,61 @@ return SCPE_OK; /* the read was successf
On entry, the end-of-data flag is checked. If it is set, the current read is
completed. Otherwise, the command phase is reset to start the next sector,
and the disc service is scheduled to allow for the intersector delay.
and the disc service is set to allow for the intersector delay.
Implementation notes:
1. The intersector time is required to allow the ICD interface to set the
end-of-data flag before the next sector begins. The CPU must have enough
time to receive the last byte of the current sector and then unaddress
the disc controller before the first byte of the next sector is sent. If
the time is not long enough, the sector address will be incremented twice
(e.g., a 128-word read of sector 0 will terminate with sector 2 as the
next sector instead of sector 1).
1. The CPU indicates the end of a read data transfer to an ICD controller by
untalking the drive. The untalk is done by the driver as soon as the
DCPC completion interrupt is processed. However, the time from the final
DCPC transfer through driver entry to the point where the untalk is
asserted on the bus varies from 80 instructions (RTE-6/VM with OS
microcode and the buffer in the system map) to 152 instructions (RTE-IVB
with the buffer in the user map). The untalk must occur before the start
of the next sector, or the drive will begin the data transfer.
Normally, this is not a problem, as the driver clears the FIFO of any
received data after DCPC completion. However, if the read terminates
after the last sector of a track, and accessing the next sector would
require an intervening seek, and the file mask disables auto-seeking or
an enabled seek would move the positioner beyond the drive limits, then
the controller will indicate an End of Cylinder error if the untalk does
not arrive before the seek is initiated.
The RTE driver (DVA32) and various utilities that manage the disc
directly (e.g., SWTCH) do not appear to account for these bogus errors,
so the ICD controller hardware must avoid them in some unknown manner.
We work around the issue by extending the intersector delay to allow time
for a potential untalk whenever the next access would otherwise fail.
Note that this issue does not occur with writes because DCPC completion
asserts EOI concurrently with the final data byte to terminate the
command.
*/
static void end_read (CVPTR cvptr, UNIT *uptr)
{
uint32 limit;
if (cvptr->eod == SET) /* is the end of data indicated? */
dl_end_command (cvptr, normal_completion); /* complete the command */
else { /* reading continues */
uptr->PHASE = start_phase; /* reset to the start phase */
uptr->wait = cvptr->sector_time; /* delay for the intersector time */
if (cvptr->eoc == SET && cvptr->type == ICD) { /* seek will be required and controller is ICD? */
if (!(cvptr->file_mask & DL_FAUTSK)) /* if auto-seek is disabled */
limit = cvptr->cylinder; /* then the limit is the current cylinder */
else if (cvptr->file_mask & DL_FDECR) /* else if enabled and decremental seek */
limit = 0; /* then the limit is cylinder 0 */
else /* else the enabled limit is the last cylinder */
limit = drive_props [GET_MODEL (uptr->flags)].cylinders;
if (cvptr->cylinder == limit) /* is positioner at the limit? */
uptr->wait = cvptr->eot_time; /* seek will fail; delay to allow CPU to untalk */
}
}
return;
@ -1877,10 +1913,10 @@ return;
static void start_write (CVPTR cvptr, UNIT *uptr)
{
const t_bool verify = (CNTLR_OPCODE) uptr->OP == write; /* only Write verifies the sector address */
const t_bool verify = (CNTLR_OPCODE) uptr->OP == Write; /* only Write verifies the sector address */
if ((uptr->flags & UNIT_WPROT) || /* is the unit write protected, */
(!verify && !(uptr->flags & UNIT_FMT))) /* or is formatting required but not enabled? */
if ((uptr->flags & UNIT_WPROT) /* is the unit write protected, */
|| !verify && !(uptr->flags & UNIT_FMT)) /* or is formatting required but not enabled? */
dl_end_command (cvptr, status_2_error); /* terminate the write with an error */
else if (position_sector (cvptr, uptr, verify)) { /* writing is permitted; position the sector */
@ -1925,7 +1961,7 @@ static t_stat end_write (CVPTR cvptr, UNIT *uptr)
uint32 count;
uint16 pad;
const CNTLR_OPCODE opcode = (CNTLR_OPCODE) uptr->OP;
const uint32 offset = (opcode == write_full_sector ? 3 : 0);
const uint32 offset = (opcode == Write_Full_Sector ? 3 : 0);
if (uptr->flags & UNIT_UNLOAD) { /* if the drive is not ready, */
dl_end_command (cvptr, access_not_ready); /* terminate the command with an error */
@ -1964,12 +2000,12 @@ return SCPE_OK;
/* Position the disc image file at the current sector.
The image file is positioned at the byte address corresponding to the
controller's current cylinder, head, and sector address. Positioning may
involve an auto-seek if a prior read or write addressed the final sector in a
cylinder. If a seek is initiated or an error is detected, the routine
returns FALSE to indicate that the positioning was not performed. If the
file was positioned, the routine returns TRUE.
The image file is positioned at the byte address corresponding to the drive's
current cylinder and the controller's current head and sector addresses.
Positioning may involve an auto-seek if a prior read or write addressed the
final sector of a cylinder. If a seek is initiated or an error is detected,
the routine returns FALSE to indicate that the positioning was not performed.
If the file was positioned, the routine returns TRUE.
On entry, if the controller's end-of-cylinder flag is set, a prior read or
write addressed the final sector in the current cylinder. If the file mask
@ -1983,21 +2019,23 @@ return SCPE_OK;
seek completion and the command state unchanged. When the service is
reentered, the read or write will continue on the new cylinder.
If the EOC flag was not set, the drive position is checked against the
controller position. If they are different (as may occur with an Address
Record command that specified a different location than the last Seek
command), a seek is started to the correct cylinder, and the routine returns
with the disc service scheduled for seek completion as above.
If the EOC flag was not set, the drive's position is checked against the
controller's position if address verification is requested. If they are
different (as may occur with an Address Record command that specified a
different location than the last Seek command), a seek is started to the
correct cylinder, and the routine returns with the disc service scheduled for
seek completion as above.
If the drive and controller positions agree, the controller CHS address is
validated against the drive limits. If they are invalid, Seek Check status
is set, and the command is terminated with an error.
If the drive and controller positions agree or verification is not requested,
the CHS addresses are validated against the drive limits. If they are
invalid, Seek Check status is set, and the command is terminated with an
error.
If the address is valid, the drive is checked to ensure that it is ready for
positioning. If it is, the the byte offset in the image file is calculated
from the CHS address, and the file is positioned. The disc service is
scheduled to begin the data transfer, and the routine returns TRUE to
indicate that the file position was set.
If the addresses are valid, the drive is checked to ensure that it is ready
for positioning. If it is, the the byte offset in the image file is
calculated from the CHS address, and the file is positioned. The disc
service is scheduled to begin the data transfer, and the routine returns TRUE
to indicate that the file position was set.
Implementation notes:
@ -2164,7 +2202,7 @@ if (uptr->flags & UNIT_UNLOAD) { /* are the heads unloade
return FALSE; /* as the drive was not ready */
}
if ((CNTLR_OPCODE) uptr->OP == recalibrate) /* is the unit recalibrating? */
if ((CNTLR_OPCODE) uptr->OP == Recalibrate) /* is the unit recalibrating? */
target_cylinder = 0; /* seek to cylinder 0 and don't reset the EOC flag */
else { /* it's a Seek command or an auto-seek request */

56
HP2100/hp_disclib.h
View file

@ -24,7 +24,9 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from the authors.
30-Mar-12 JDB First release
24-Oct-12 JDB Changed CNTLR_OPCODE to title case to avoid name clash
07-May-12 JDB Added end-of-track delay time as a controller variable
02-May-12 JDB First release
09-Nov-11 JDB Created disc controller common library from DS simulator
@ -53,6 +55,7 @@
/* Default controller times */
#define DL_EOT_TIME 160 /* end-of-track delay time */
#define DL_SEEK_TIME 100 /* seek delay time (per cylinder) */
#define DL_SECTOR_TIME 27 /* intersector delay time */
#define DL_CMD_TIME 3 /* command start delay time */
@ -204,29 +207,29 @@ typedef enum {
/* Controller opcodes */
typedef enum {
cold_load_read = 000,
recalibrate = 001,
seek = 002,
request_status = 003,
request_sector_address = 004,
read = 005,
read_full_sector = 006,
verify = 007,
write = 010,
write_full_sector = 011,
clear = 012,
initialize = 013,
address_record = 014,
request_syndrome = 015,
read_with_offset = 016,
set_file_mask = 017,
invalid_opcode = 020,
read_without_verify = 022,
load_tio_register = 023,
request_disc_address = 024,
end = 025,
wakeup = 026,
last_opcode = wakeup /* last valid opcode */
Cold_Load_Read = 000,
Recalibrate = 001,
Seek = 002,
Request_Status = 003,
Request_Sector_Address = 004,
Read = 005,
Read_Full_Sector = 006,
Verify = 007,
Write = 010,
Write_Full_Sector = 011,
Clear = 012,
Initialize = 013,
Address_Record = 014,
Request_Syndrome = 015,
Read_With_Offset = 016,
Set_File_Mask = 017,
Invalid_Opcode = 020,
Read_Without_Verify = 022,
Load_TIO_Register = 023,
Request_Disc_Address = 024,
End = 025,
Wakeup = 026,
Last_Opcode = Wakeup /* last valid opcode */
} CNTLR_OPCODE;
#define DL_OPCODE_MASK 037
@ -330,6 +333,7 @@ typedef struct {
uint32 index; /* data buffer current index */
uint32 length; /* data buffer valid length */
UNIT *aux; /* MAC auxiliary units (controller and timer) */
int32 eot_time; /* end-of-track read delay time */
int32 seek_time; /* per-cylinder seek delay time */
int32 sector_time; /* intersector delay time */
int32 cmd_time; /* command response time */
@ -350,11 +354,11 @@ typedef CNTLR_VARS *CVPTR; /* pointer to controller
*/
#define CNTLR_INIT(ctype,bufptr,auxptr) \
(ctype), cntlr_idle, end, normal_completion, \
(ctype), cntlr_idle, End, normal_completion, \
CLEAR, CLEAR, \
0, 0, 0, 0, 0, 0, 0, 0, \
(bufptr), 0, 0, (auxptr), \
DL_SEEK_TIME, DL_SECTOR_TIME, \
DL_EOT_TIME, DL_SEEK_TIME, DL_SECTOR_TIME, \
DL_CMD_TIME, DL_DATA_TIME, DL_WAIT_TIME

2
I1401/i1401_cd.c
View file

@ -398,7 +398,7 @@ static const unsigned char boot_rom[] = {
t_stat cdr_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 saved_IS;
for (i = 0; i < CDR_WIDTH; i++) /* clear buffer */

7
I1401/i1401_cpu.c
View file

@ -197,11 +197,8 @@ int32 hst_lnt = 0; /* history length */
InstHistory *hst = NULL; /* instruction history */
t_bool conv_old = 0; /* old conversions */
extern int32 sim_int_char;
extern int32 sim_emax;
extern t_value *sim_eval;
extern FILE *sim_deb;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
@ -229,8 +226,6 @@ extern t_stat inq_io (int32 flag, int32 mod);
extern t_stat mt_io (int32 unit, int32 flag, int32 mod);
extern t_stat dp_io (int32 fnc, int32 flag, int32 mod);
extern t_stat mt_func (int32 unit, int32 flag, int32 mod);
extern t_stat sim_activate (UNIT *uptr, int32 delay);
extern t_stat fprint_sym (FILE *of, t_addr addr, t_value *val, UNIT *uptr, int32 sw);
/* CPU data structures
@ -1904,8 +1899,6 @@ char *cptr = (char *) desc;
t_value sim_eval[MAX_L + 1];
t_stat r;
InstHistory *h;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
if (hst_lnt == 0) /* enabled? */
return SCPE_NOFNC;

2
I1401/i1401_mt.c
View file

@ -113,7 +113,6 @@ extern uint8 M[]; /* memory */
extern int32 ind[64];
extern int32 BS, iochk;
extern UNIT cpu_unit;
extern FILE *sim_deb;
t_stat mt_reset (DEVICE *dptr);
t_stat mt_boot (int32 unitno, DEVICE *dptr);
@ -469,7 +468,6 @@ return SCPE_OK;
t_stat mt_boot (int32 unitno, DEVICE *dptr)
{
extern int32 saved_IS;
extern int32 sim_switches;
if ((sim_switches & SWMASK ('N')) == 0) /* unless -n */
sim_tape_rewind (&mt_unit[unitno]); /* force rewind */

5
I1620/i1620_cpu.c
View file

@ -131,11 +131,6 @@ int32 hst_lnt = 0; /* history length */
InstHistory *hst = NULL; /* instruction history */
uint8 ind[NUM_IND] = { 0 }; /* indicators */
extern int32 sim_int_char;
extern int32 sim_interval;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern FILE *sim_log;
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_reset (DEVICE *dptr);

4
I1620/i1620_pt.c
View file

@ -348,7 +348,7 @@ return SCPE_OK;
/* Bootstrap routine */
const static uint8 boot_rom[] = {
static const uint8 boot_rom[] = {
4, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* NOP */
3, 6, 0, 0, 0, 3, 1, 0, 0, 3, 0, 0, /* RNPT 31 */
2, 5, 0, 0, 0, 7, 1, 0, 0, 0, 0, 0, /* TD 71,loc */
@ -363,7 +363,7 @@ const static uint8 boot_rom[] = {
t_stat ptr_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern uint32 saved_PC;
for (i = 0; i < BOOT_LEN; i++)

1
I7094/i7094_cd.c
View file

@ -88,7 +88,6 @@ t_stat cd_attach (UNIT *uptr, char *cptr);
t_stat cd_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc);
char colbin_to_bcd (uint32 cb);
extern int32 sim_switches;
extern uint32 PC;
extern uint32 ind_ioc;
extern char bcd_to_ascii_a[64];

8
I7094/i7094_com.c
View file

@ -183,10 +183,10 @@ uint32 com_chob_v = 0; /* valid flag */
t_uint64 com_buf[COM_BUFSIZ]; /* channel buffer */
LISTHD com_free; /* free list */
uint32 com_not_ret[COM_TLINES] = { 0 }; /* chars not returned */
LISTHD com_inpq[COM_TLINES] = { 0 }; /* input queues */
LISTHD com_outq[COM_TLINES] = { 0 }; /* output queues */
LISTHD com_inpq[COM_TLINES] = { {0} }; /* input queues */
LISTHD com_outq[COM_TLINES] = { {0} }; /* output queues */
LISTENT com_pkt[COM_PKTSIZ]; /* character packets */
TMLN com_ldsc[COM_MLINES] = { 0 }; /* line descriptors */
TMLN com_ldsc[COM_MLINES] = { {0} }; /* line descriptors */
TMXR com_desc = { COM_MLINES, 0, 0, com_ldsc }; /* mux descriptor */
/* Even parity truth table */
@ -348,7 +348,7 @@ DEVICE com_dev = {
3, 10, 31, 1, 16, 8,
&tmxr_ex, &tmxr_dep, &com_reset,
NULL, &com_attach, &com_detach,
&com_dib, DEV_NET | DEV_DIS
&com_dib, DEV_MUX | DEV_DIS
};
/* COML data structures

7
I7094/i7094_cpu.c
View file

@ -211,11 +211,6 @@ extern uint32 ch_sta[NUM_CHAN];
extern uint32 ch_flags[NUM_CHAN];
extern DEVICE mt_dev[NUM_CHAN];
extern DEVICE ch_dev[NUM_CHAN];
extern FILE *sim_deb;
extern int32 sim_int_char;
extern int32 sim_interval;
extern int32 sim_switches;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
/* Forward and external declarations */
@ -2406,8 +2401,6 @@ t_stat cpu_fprint_one_inst (FILE *st, uint32 pc, uint32 rpt, uint32 ea,
{
int32 ch;
t_value sim_eval;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
sim_eval = ir;
if (pc & HIST_PC) { /* instruction? */

2
I7094/i7094_io.c
View file

@ -88,7 +88,6 @@ extern DEVICE mt_dev[NUM_CHAN];
extern DEVICE drm_dev;
extern DEVICE dsk_dev;
extern DEVICE com_dev;
extern uint32 sim_brk_summ;
t_stat ch_reset (DEVICE *dptr);
t_stat ch6_svc (UNIT *uptr);
@ -111,7 +110,6 @@ t_stat ch9_wr_getw (uint32 ch);
void ch9_eval_int (uint32 ch, uint32 iflags);
DEVICE *ch_map_flags (uint32 ch, int32 fl);
extern CTAB *sim_vm_cmd;
extern t_stat ch_bkpt (uint32 ch, uint32 clc);
const uint32 col_masks[12] = { /* row 9,8,..,0,11,12 */

3
I7094/i7094_mt.c
View file

@ -72,7 +72,6 @@ static const char *tape_stat[] = {
extern uint32 PC;
extern uint32 cpu_model;
extern uint32 ind_ioc;
extern FILE *sim_deb;
extern const char *sel_name[];
t_stat mt_chsel (uint32 ch, uint32 sel, uint32 unit);
@ -368,7 +367,7 @@ DEVICE mt_dev[NUM_CHAN] = {
MT_NUMDR + 1, 10, 31, 1, 8, 8,
NULL, NULL, &mt_reset,
&mt_boot, &mt_attach, &sim_tape_detach,
&mt_dib, DEV_DEBUG
&mt_dib, DEV_DEBUG | DEV_TAPE
},
{
"MTB", mtb_unit, mtb_reg, mt_mod,

16
Ibm1130/ibm1130_cpu.c
View file

@ -222,9 +222,7 @@ t_stat cpu_set_type (UNIT *uptr, int32 value, char *cptr, void *desc);
void calc_ints (void);
extern t_stat ts_wr (int32 data, int32 addr, int32 access);
extern t_stat detach_cmd (int32 flags, char *cptr);
extern UNIT cr_unit;
extern int32 sim_switches;
#ifdef ENABLE_BACKTRACE
static void archive_backtrace(char *inst);
@ -466,8 +464,6 @@ static char *xio_funcs[] = {
t_stat sim_instr (void)
{
extern int32 sim_interval;
extern UNIT *sim_clock_queue;
int32 i, eaddr, INDIR, IR, F, DSPLC, word2, oldval, newval, src, src2, dst, abit, xbit;
int32 iocc_addr, iocc_op, iocc_dev, iocc_func, iocc_mod;
char msg[50];
@ -516,7 +512,7 @@ t_stat sim_instr (void)
#endif /* ifdef GUI_SUPPORT */
if (sim_interval <= 0) { /* any events timed out? */
if (sim_clock_queue != NULL) {
if (sim_clock_queue != QUEUE_LIST_END) {
if ((status = sim_process_event()) != 0)
reason = simh_status_to_stopcode(status);
@ -768,7 +764,7 @@ t_stat sim_instr (void)
CCC--;
}
C = (CCC != 0);
WriteIndex(TAG, ReadIndex(TAG) & 0xFF00 | CCC); /* put 6 bits back into low byte of index register */
WriteIndex(TAG, (ReadIndex(TAG) & 0xFF00) | CCC); /* put 6 bits back into low byte of index register */
break;
}
/* if TAG == 0, fall through and treat like normal shift SLT */
@ -814,8 +810,8 @@ t_stat sim_instr (void)
while (CCC > 0) {
xbit = (ACC & 0x0001) << 15;
abit = (ACC & 0x8000);
ACC = (ACC >> 1) & 0x7FFF | abit;
EXT = (EXT >> 1) & 0x7FFF | xbit;
ACC = ((ACC >> 1) & 0x7FFF) | abit;
EXT = ((EXT >> 1) & 0x7FFF) | xbit;
CCC--;
}
break;
@ -824,8 +820,8 @@ t_stat sim_instr (void)
while (CCC > 0) {
abit = (EXT & 0x0001) << 15;
xbit = (ACC & 0x0001) << 15;
ACC = (ACC >> 1) & 0x7FFF | abit;
EXT = (EXT >> 1) & 0x7FFF | xbit;
ACC = ((ACC >> 1) & 0x7FFF) | abit;
EXT = ((EXT >> 1) & 0x7FFF) | xbit;
CCC--;
}
break;

1
Ibm1130/ibm1130_cr.c
View file

@ -349,7 +349,6 @@ way to solve the problem, the other is to keep DSW up-to-date all the time).
#define ENABLE_PHYSICAL_CARD_READER_SUPPORT
extern int32 sim_switches;
extern UNIT cpu_unit;
static t_stat cr_svc (UNIT *uptr);

2
Ibm1130/ibm1130_disk.c
View file

@ -39,8 +39,6 @@ commands may NOT be accurate. This should probably be fixed.
#define TRACE_DMS_IO /* define to enable debug of DMS phase IO */
#ifdef TRACE_DMS_IO
extern int32 sim_switches;
extern int32 sim_quiet;
static int trace_dms = 0;
static void tracesector (int iswrite, int nwords, int addr, int sector);
static t_stat where_cmd (int32 flag, char *ptr);

6
Ibm1130/ibm1130_gui.c
View file

@ -93,8 +93,8 @@ DEVICE console_dev = {
/* reset for the "console" display device */
extern char *read_line (char *cptr, int size, FILE *stream);
extern FILE *sim_log;
extern DEVICE *find_unit (char *cptr, UNIT **uptr);
extern char *sim_prompt;
extern UNIT cr_unit; /* pointers to 1442 and 1132 (1403) printers */
extern UNIT prt_unit;
@ -1648,8 +1648,8 @@ void remark_cmd (char *remark)
if (sim_log) fprintf(sim_log, "%s\n", remark);
if (scp_reading) {
printf("sim> ");
if (sim_log) fprintf(sim_log, "sim> ");
printf("%s", sim_prompt);
if (sim_log) fprintf(sim_log, "%s", sim_prompt);
}
}

1
Ibm1130/ibm1130_plot.c
View file

@ -93,7 +93,6 @@ static void update_pen(void); /* will ensure pen action is correct
static t_stat plot_validate_change (UNIT *uptr, int32 val, char * ptr, void *desc); /* when set command issued */
static void process_cmd(void); /* does actual drawing for plotter */
extern int32 sim_switches; /* switches set on simh command */
static int16 plot_dsw = 0; /* device status word */
static int16 plot_cmd = 0; /* the command to process */
static int32 plot_wait = 1000; /* plotter movement wait */

2
Ibm1130/ibm1130_prt.c
View file

@ -202,8 +202,6 @@ cccgi[] = {
#include "ibm1130_prtwheel.h"
extern int32 sim_switches;
/* cc_format_1132 and cc_format_1403 - turn cctape bits into proper format for DSW or status read */
static int cc_format_1132 (int bits)

120
Ibm1130/ibm1130_sca.c
View file

@ -85,9 +85,6 @@
#include "ibm1130_defs.h"
#include "sim_sock.h" /* include path must include main simh directory */
#include <ctype.h>
#ifndef INADDR_NONE
#define INADDR_NONE ((unsigned long)-1)
#endif
#define DEBUG_SCA_FLUSH 0x0001 /* debugging options */
#define DEBUG_SCA_TRANSMIT 0x0002
@ -106,7 +103,7 @@
/* #define DEBUG_SCA (DEBUG_SCA_TIMERS|DEBUG_SCA_FLUSH|DEBUG_SCA_TRANSMIT|DEBUG_SCA_CHECK_INDATA|DEBUG_SCA_RECEIVE_SYNC|DEBUG_SCA_RECEIVE_DATA|DEBUG_SCA_XIO_INITR|DEBUG_SCA_XIO_INITW) */
#define DEBUG_SCA (DEBUG_SCA_TIMERS|DEBUG_SCA_FLUSH|DEBUG_SCA_CHECK_INDATA|DEBUG_SCA_XIO_INITR|DEBUG_SCA_XIO_INITW)
#define SCA_DEFAULT_PORT 2703 /* default socket, This is the number of the IBM 360's BSC device */
#define SCA_DEFAULT_PORT "2703" /* default socket, This is the number of the IBM 360's BSC device */
#define MAX_SYNS 100 /* number of consecutive syn's after which we stop buffering them */
@ -164,7 +161,7 @@ static uint32 sca_state = SCA_STATE_IDLE;
static uint8 sichar = 0; /* sync/idle character */
static uint8 rcvd_char = 0; /* most recently received character */
static uint8 sca_frame = 8;
static uint16 sca_port = SCA_DEFAULT_PORT; /* listening port number */
static char sca_port[CBUFSIZE]; /* listening port */
static int32 sca_keepalive = 0; /* keepalive SYN packet period in msec, default = 0 (disabled) */
static SCA_TIMER_STATE sca_timer_state[3]; /* current timer state */
static int sca_timer_endtime[3]; /* clocktime when timeout is to occur if state is RUNNING */
@ -205,8 +202,6 @@ static int sca_rcvptr = 0; /* index of next byte to take from rcvbuf *
#define UNIT_AUTOANSWER (1u << UNIT_V_AUTOANSWER)
#define UNIT_LISTEN (1u << UNIT_V_LISTEN)
extern int sim_switches; /* variable that gets bits set for -x switches on command lines */
t_stat sca_set_baud (UNIT *uptr, int32 value, char *cptr, void *desc);
UNIT sca_unit = { /* default settings */
@ -221,7 +216,7 @@ REG sca_reg[] = { /* DEVICE STATE/SETTABLE PARAMETERS: */
{ DRDATA (SCASTATE, sca_state, 32), PV_LEFT }, /* current state */
{ DRDATA (CTIME, sca_cwait, 32), PV_LEFT }, /* inter-character wait */
{ DRDATA (ITIME, sca_iwait, 32), PV_LEFT }, /* idle wait (polling interval for socket connects) */
{ DRDATA (SCASOCKET, sca_port, 16), PV_LEFT }, /* listening port number */
{ BRDATA (SCASOCKET, sca_port, 8, 8, sizeof(sca_port)) }, /* listening port number */
{ DRDATA (KEEPALIVE, sca_keepalive, 32), PV_LEFT }, /* keepalive packet period in msec */
{ NULL } };
@ -317,7 +312,7 @@ static void sca_socket_error (void)
free(sca_unit.filename);
if (sca_unit.flags & UNIT_LISTEN) {
sprintf(name, "(Listening on port %d)", sca_port);
sprintf(name, "(Listening on port %s)", sca_port);
sca_unit.filename = mstring(name);
printf("%s\n", name);
}
@ -454,99 +449,75 @@ static t_stat sca_reset (DEVICE *dptr)
static t_stat sca_attach (UNIT *uptr, char *cptr)
{
char host[CBUFSIZE], port[CBUFSIZE];
t_bool do_listen;
char *colon;
uint32 ipaddr;
int32 port;
struct hostent *he;
char name[256];
static SOCKET sdummy = INVALID_SOCKET;
fd_set wr_set, err_set;
char name[CBUFSIZE];
t_stat r;
do_listen = sim_switches & SWMASK('L'); /* -l means listen mode */
if (sca_unit.flags & UNIT_ATT) /* if already attached, detach */
detach_unit(&sca_unit);
if (do_listen) { /* if listen mode, string specifies socket number (only; otherwise it's a dummy argument) */
if (isdigit(*cptr)) { /* if digits specified, extract port number */
port = atoi(cptr);
if (port <= 0 || port > 65535)
return SCPE_ARG;
else
sca_port = port;
}
if (do_listen) { /* if listen mode, string specifies port number (only; otherwise it's a dummy argument) */
r = sim_parse_addr (cptr, host, sizeof(host), NULL, port, sizeof(port), SCA_DEFAULT_PORT, NULL);
if (r != SCPE_OK)
return r;
if ((0 == strcmp(port, cptr)) && (0 == strcmp(port, "dummy")))
strcpy(port, SCA_DEFAULT_PORT);
sprintf(sca_port, "%s%s%s:%s", strchr(host, ':') ? "[" : "", host, strchr(host, ':') ? "]" : "", port);
/* else if nondigits specified, ignore... but the command has to have something there otherwise the core scp */
/* attach_cmd() routine complains "too few arguments". */
if ((sca_lsock = sim_master_sock(sca_port)) == INVALID_SOCKET)
sca_lsock = sim_master_sock(sca_port, &r);
if (r != SCPE_OK)
return r;
if (sca_lsock == INVALID_SOCKET)
return SCPE_OPENERR;
SETBIT(sca_unit.flags, UNIT_LISTEN); /* note that we are listening, not yet connected */
sprintf(name, "(Listening on port %d)", sca_port);
sca_unit.filename = mstring(name);
printf("%s\n", name);
sprintf(name, "(Listening on port %s)", sca_port);
sca_unit.filename = mstring(name);
printf("%s\n", sca_unit.filename);
}
else {
while (*cptr && *cptr <= ' ')
while (*cptr && *cptr <= ' ')
cptr++;
if (! *cptr)
return SCPE_2FARG;
if ((colon = strchr(cptr, ':')) != NULL) {
*colon++ = '\0'; /* clip hostname at colon */
r = sim_parse_addr (cptr, host, sizeof(host), NULL, port, sizeof(port), SCA_DEFAULT_PORT, NULL);
if (r != SCPE_OK)
return r;
if ((0 == strcmp(cptr, port)) && (0 == strcmp(host, ""))) {
strcpy(host, port);
strcpy(port, SCA_DEFAULT_PORT);
}
port = atoi(colon); /* extract port number that follows it */
if (port <= 0 || port > 65535)
return SCPE_ARG;
else
sca_port = port;
}
sprintf(sca_port, "%s%s%s:%s", strchr(host, ':') ? "[" : "", host, strchr(host, ':') ? "]" : "", port);
if (sdummy == INVALID_SOCKET)
if ((sdummy = sim_create_sock()) == INVALID_SOCKET) /* create and keep a socket, to force initialization */
return SCPE_IERR; /* of socket library (e.g on Win32 call WSAStartup), else gethostbyname fails */
if (get_ipaddr(cptr, &ipaddr, NULL) != SCPE_OK) { /* try to parse hostname as dotted decimal nnn.nnn.nnn.nnn */
if ((he = gethostbyname(cptr)) == NULL) /* if not decimal, look up name through DNS */
return SCPE_OPENERR;
if ((ipaddr = * (unsigned long *) he->h_addr_list[0]) == INADDR_NONE)
return SCPE_OPENERR;
ipaddr = ntohl(ipaddr); /* convert to host byte order; gethostbyname() gives us network order */
}
if ((sca_sock = sim_connect_sock(ipaddr, sca_port)) == INVALID_SOCKET)
if ((sca_sock = sim_connect_sock(sca_port, NULL, NULL)) == INVALID_SOCKET)
return SCPE_OPENERR;
/* sim_connect_sock() sets socket to nonblocking before initiating the connect, so
* the connect is pending when it returns. For outgoing connections, the attach command should wait
* until the connection succeeds or fails. We use "accept" to wait and find out which way it goes...
* until the connection succeeds or fails. We use "sim_check_conn" to wait and find out which way it goes...
*/
FD_ZERO(&wr_set); /* we are only interested in info for sca_sock */
FD_ZERO(&err_set);
FD_SET(sca_sock, &wr_set);
FD_SET(sca_sock, &err_set);
while (0 == sim_check_conn(sca_sock, 0))/* wait for connection to complete or fail */
sim_os_ms_sleep(1000);
select(3, NULL, &wr_set, &err_set, NULL); /* wait for connection to complete or fail */
if (FD_ISSET(sca_sock, &wr_set)) { /* sca_sock appears in "writable" set -- connect completed */
sprintf(name, "%s:%d", cptr, sca_port);
if (1 == sim_check_conn(sca_sock, 0)) { /* sca_sock appears in "writable" set -- connect completed */
sprintf(name, "%s%s%s:%s", strchr(host, ':') ? "[" : "", host, strchr(host, ':') ? "]" : "", port);
sca_unit.filename = mstring(name);
SETBIT(sca_dsw, SCA_DSW_READY);
}
else if (FD_ISSET(sca_sock, &err_set)) { /* sca_sock appears in "error" set -- connect failed */
sim_close_sock(sca_sock, TRUE);
sca_sock = INVALID_SOCKET;
return SCPE_OPENERR;
}
else { /* if we get here my assumption about how select works is wrong */
printf("SCA_SOCK NOT FOUND IN WR_SET -OR- ERR_SET, CODING IN IBM1130_SCA IS WRONG\n");
else { /* sca_sock appears in "error" set -- connect failed */
sim_close_sock(sca_sock, TRUE);
sca_sock = INVALID_SOCKET;
return SCPE_OPENERR;
@ -610,22 +581,17 @@ static t_stat sca_detach (UNIT *uptr)
static void sca_check_connect (void)
{
uint32 ipaddr;
char name[100];
char *connectaddress;
if ((sca_sock = sim_accept_conn(sca_lsock, &ipaddr)) == INVALID_SOCKET)
if ((sca_sock = sim_accept_conn(sca_lsock, &connectaddress)) == INVALID_SOCKET)
return;
ipaddr = htonl(ipaddr); /* convert to network order so we can print it */
sprintf(name, "%d.%d.%d.%d", ipaddr & 0xFF, (ipaddr >> 8) & 0xFF, (ipaddr >> 16) & 0xFF, (ipaddr >> 24) & 0xFF);
printf("(SCA connection from %s)\n", name);
printf("(SCA connection from %s)\n", connectaddress);
if (sca_unit.filename != NULL)
free(sca_unit.filename);
sca_unit.filename = mstring(name);
sca_unit.filename = connectaddress;
SETBIT(sca_dsw, SCA_DSW_READY); /* indicate active connection */

13
Ibm1130/ibm1130_stddev.c
View file

@ -112,7 +112,6 @@ typedef struct tag_os_map { /* os_map = overstrike mapping */
unsigned char inlist[MAX_OS_CHARS]; /* inlist = overstruck ASCII characters, sorted. NOT NULL TERMINATED */
} OS_MAP;
extern UNIT *sim_clock_queue;
extern int cgi;
static int32 tti_dsw = 0; /* device status words */
@ -152,10 +151,6 @@ static char * handle_map_input_definition(char **pc);
static char * handle_map_output_definition(char **pc);
static char * handle_map_overstrike_definition(char **pc);
extern t_stat sim_poll_kbd(void);
extern t_stat sim_wait_kbd(void);
extern t_stat sim_putchar(int32 out);
#define UNIT_V_CSET (UNIT_V_UF + 0) /* user flag: character set */
#define UNIT_V_LOCKED (UNIT_V_UF + 2) /* user flag: keyboard locked */
#define UNIT_V_ANSI (UNIT_V_UF + 3)
@ -340,7 +335,7 @@ t_stat emit_conout_character (int ch)
return map_conout_character(ch);
}
static void Beep (void) /* notify user keyboard was locked or key was bad */
static void SendBeep (void) /* notify user keyboard was locked or key was bad */
{
sim_putchar(7);
}
@ -356,7 +351,7 @@ static t_stat tti_svc (UNIT *uptr)
/* otherwise, so ^E can interrupt the simulator, */
sim_activate(&tti_unit, tti_unit.wait); /* always continue polling keyboard */
assert(sim_clock_queue != NULL);
assert(sim_clock_queue != QUEUE_LIST_END);
temp = sim_poll_kbd();
@ -395,7 +390,7 @@ static t_stat tti_svc (UNIT *uptr)
}
if ((tti_unit.flags & KEYBOARD_LOCKED) || ! (tti_dsw & TT_DSW_KEYBOARD_BUSY)) {
Beep();
SendBeep();
return SCPE_OK;
}
@ -403,7 +398,7 @@ static t_stat tti_svc (UNIT *uptr)
temp = ascii_to_conin[temp];
if (temp == 0) { /* ignore invalid characters */
Beep();
SendBeep();
calc_ints();
return SCPE_OK;
}

8
Interdata/id16_cpu.c
View file

@ -223,11 +223,6 @@ InstHistory *hst = NULL; /* instruction history *
struct BlockIO blk_io; /* block I/O status */
uint32 (*dev_tab[DEVNO])(uint32 dev, uint32 op, uint32 datout) = { NULL };
extern int32 sim_interval;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern t_bool sim_idle_enab;
uint32 ReadB (uint32 loc);
uint32 ReadH (uint32 loc);
void WriteB (uint32 loc, uint32 val);
@ -651,7 +646,6 @@ while (reason == 0) { /* loop until halted */
if (PSW & PSW_WAIT) { /* wait state? */
sim_idle (TMR_LFC, TRUE); /* idling */
else sim_interval = sim_interval - 1; /* no, count cycle */
continue;
}
@ -2010,8 +2004,6 @@ char *cptr = (char *) desc;
t_value sim_eval[2];
t_stat r;
InstHistory *h;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
if (hst_lnt == 0) /* enabled? */
return SCPE_NOFNC;

11
Interdata/id32_cpu.c
View file

@ -222,7 +222,7 @@ uint32 GREG[16 * NRSETS] = { 0 }; /* general registers */
uint32 *M = NULL; /* memory */
uint32 *R = &GREG[0]; /* working reg set */
uint32 F[8] = { 0 }; /* sp fp registers */
dpr_t D[8] = { 0 }; /* dp fp registers */
dpr_t D[8] = { {0} }; /* dp fp registers */
uint32 PSW = 0; /* processor status word */
uint32 PC = 0; /* program counter */
uint32 oPC = 0; /* PC at inst start */
@ -253,12 +253,6 @@ jmp_buf save_env; /* abort handler */
struct BlockIO blk_io; /* block I/O status */
uint32 (*dev_tab[DEVNO])(uint32 dev, uint32 op, uint32 datout) = { NULL };
extern int32 sim_interval;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern t_bool sim_idle_enab;
extern FILE *sim_deb;
uint32 ReadB (uint32 loc, uint32 rel);
uint32 ReadH (uint32 loc, uint32 rel);
void WriteB (uint32 loc, uint32 val, uint32 rel);
@ -715,7 +709,6 @@ while (reason == 0) { /* loop until halted */
if (PSW & PSW_WAIT) { /* wait state? */
sim_idle (TMR_LFC, TRUE); /* idling */
else sim_interval = sim_interval - 1; /* no, count cycle */
continue;
}
@ -2399,8 +2392,6 @@ char *cptr = (char *) desc;
t_value sim_eval[3];
t_stat r;
InstHistory *h;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
if (hst_lnt == 0) /* enabled? */
return SCPE_NOFNC;

1
Interdata/id32_dboot.c
View file

@ -288,7 +288,6 @@ t_stat id_dboot (int32 u, DEVICE *dptr)
{
extern DIB ttp_dib, sch_dib;
extern uint32 PC;
extern int32 sim_switches;
uint32 i, typ, ctlno, off, add, cap, sch_dev;
UNIT *uptr;

1
Interdata/id_dp.c
View file

@ -139,7 +139,6 @@ static struct drvtyp drv_tab[] = {
};
extern uint32 int_req[INTSZ], int_enb[INTSZ];
extern FILE *sim_deb;
uint8 dpxb[DP_NUMBY]; /* xfer buffer */
uint32 dp_bptr = 0; /* buffer ptr */

2
Interdata/id_fd.c
View file

@ -115,7 +115,7 @@ uint32 fd_cmd = 0; /* command */
uint32 fd_db = 0; /* data buffer */
uint32 fd_bptr = 0; /* buffer pointer */
uint8 fdxb[FD_NUMBY] = { 0 }; /* sector buffer */
uint8 fd_es[FD_NUMDR][ES_SIZE] = { 0 }; /* ext status */
uint8 fd_es[FD_NUMDR][ES_SIZE] = { {0} }; /* ext status */
uint32 fd_lrn = 0; /* log rec # */
uint32 fd_wdv = 0; /* wd valid */
uint32 fd_stopioe = 1; /* stop on error */

2
Interdata/id_io.c
View file

@ -66,8 +66,6 @@ extern uint32 int_req[INTSZ], int_enb[INTSZ];
extern uint32 (*dev_tab[DEVNO])(uint32 dev, uint32 op, uint32 datout);
extern uint32 pawidth;
extern UNIT cpu_unit;
extern FILE *sim_log;
extern DEVICE *sim_devices[];
uint32 sch_max = 2; /* sch count */
uint32 sch_sa[SCH_NUMCH] = { 0 }; /* start addr */

2
Interdata/id_mt.c
View file

@ -168,7 +168,7 @@ DEVICE mt_dev = {
MT_NUMDR, 10, 31, 1, 16, 8,
NULL, NULL, &mt_reset,
&mt_boot, &mt_attach, &mt_detach,
&mt_dib, DEV_DISABLE
&mt_dib, DEV_DISABLE | DEV_TAPE
};
/* Magtape: IO routine */

4
Interdata/id_pas.c
View file

@ -103,7 +103,7 @@ uint8 pas_xarm[PAS_LINES]; /* xmt int armed */
uint8 pas_rchp[PAS_LINES]; /* rcvr chr pend */
uint8 pas_tplte[PAS_LINES * 2 + 1]; /* template */
TMLN pas_ldsc[PAS_LINES] = { 0 }; /* line descriptors */
TMLN pas_ldsc[PAS_LINES] = { {0} }; /* line descriptors */
TMXR pas_desc = { 8, 0, 0, pas_ldsc }; /* mux descriptor */
#define PAS_ENAB pas_desc.lines
@ -165,7 +165,7 @@ DEVICE pas_dev = {
1, 10, 31, 1, 16, 8,
&tmxr_ex, &tmxr_dep, &pas_reset,
NULL, &pas_attach, &pas_detach,
&pas_dib, DEV_NET | DEV_DISABLE
&pas_dib, DEV_MUX | DEV_DISABLE
};
/* PASL data structures

3
Interdata/id_ttp.c
View file

@ -130,7 +130,7 @@ DEVICE ttp_dev = {
uint32 ttp (uint32 dev, uint32 op, uint32 dat)
{
int32 xmt = dev & 1;
int32 t, old_cmd;
int32 t;
switch (op) { /* case IO op */
@ -160,7 +160,6 @@ switch (op) { /* case IO op */
return t;
case IO_OC: /* command */
old_cmd = ttp_cmd; /* old cmd */
if (dat & CMD_TYP) { /* type 1? */
ttp_cmd = (ttp_cmd & 0xFF) | (dat << 8);
if (ttp_cmd & CMD_WRT) /* write? */

2
Interdata/id_uvc.c
View file

@ -358,7 +358,7 @@ int32 lfc_cosched (int32 wait)
{
int32 t;
t = sim_is_active (&lfc_unit);
t = sim_activate_time (&lfc_unit);
return (t? t - 1: wait);
}

3
LGP/lgp_cpu.c
View file

@ -147,9 +147,6 @@ int16 pcq[PCQ_SIZE] = { 0 }; /* PC queue */
int32 pcq_p = 0; /* PC queue ptr */
REG *pcq_r = NULL; /* PC queue reg ptr */
extern int32 sim_interval;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern int32 sim_step;
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);

1
LGP/lgp_stddev.c
View file

@ -48,7 +48,6 @@ extern uint32 A;
extern uint32 inp_strt, inp_done;
extern uint32 out_strt, out_done;
extern UNIT cpu_unit;
extern int32 sim_switches;
t_stat tti_svc (UNIT *uptr);
t_stat ttr_svc (UNIT *uptr);

4
LGP/lgp_sys.c
View file

@ -40,12 +40,8 @@ extern REG cpu_reg[];
extern uint32 M[];
extern uint32 PC;
extern uint32 ts_flag;
extern int32 sim_switches;
extern int32 flex_to_ascii[128], ascii_to_flex[128];
extern void (*sim_vm_fprint_addr) (FILE *st, DEVICE *dptr, t_addr addr);
extern t_addr (*sim_vm_parse_addr) (DEVICE *dptr, char *cptr, char **tptr);
/* SCP data structures and interface routines
sim_name simulator name string

7
NOVA/eclipse_cpu.c
View file

@ -495,9 +495,6 @@ FILE *Trace;
t_stat reason;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern DEVICE *sim_devices[];
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
@ -516,9 +513,6 @@ int32 PutMap(int32 addr, int32 data);
int32 Debug_Entry(int32 PC, int32 inst, int32 inst2, int32 AC0, int32 AC1, int32 AC2, int32 AC3, int32 flags);
t_stat build_devtab (void);
extern t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
/* CPU data structures
cpu_dev CPU device descriptor
@ -699,7 +693,6 @@ DEVICE pit_dev = {
t_stat sim_instr (void)
{
extern int32 sim_interval;
register int32 PC, IR, i, t, MA, j, k, tac;
register uint32 mddata, uAC0, uAC1, uAC2, uAC3;
int16 sAC0, sAC1, sAC2;

2
NOVA/eclipse_tt.c
View file

@ -35,6 +35,7 @@
*/
#include "nova_defs.h"
#include "sim_tmxr.h"
#define UNIT_V_DASHER (UNIT_V_UF + 0) /* Dasher mode */
#define UNIT_DASHER (1 << UNIT_V_DASHER)
@ -192,6 +193,7 @@ void translate_in()
t_stat tti_reset (DEVICE *dptr)
{
tmxr_set_console_units (&tti_unit, &tto_unit);
tti_unit.buf = 0;
dev_busy = dev_busy & ~INT_TTI; /* clear busy */
dev_done = dev_done & ~INT_TTI; /* clear done, int */

8
NOVA/nova_cpu.c
View file

@ -330,14 +330,6 @@ char * devBitNames( int32 flags, char * ptr, char * sepStr ) ;
void mask_out (int32 mask);
extern int32 sim_interval;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern DEVICE * sim_devices[];
extern t_stat fprint_sym(FILE *ofile, t_addr addr, t_value *val, UNIT *uptr, int32 sw);
/* CPU data structures
cpu_dev CPU device descriptor

5
NOVA/nova_dkp.c
View file

@ -25,6 +25,7 @@
dkp moving head disk
27-Apr-12 RMS Changed ??? string digraphs to ?, per C rules
04-Jul-04 BKR device name changed to DG's DKP from DEC's DP,
DEV_SET/CLR/INTR macro use started,
fixed 'P' pulse code and secret quirks,
@ -706,7 +707,7 @@ if ( DKP_TRACE(1) )
"write"
: ((uptr->FUNC == FCCY_SEEK) ?
"seek"
: "<?\?\?>"
: "<?>"
)
)
),
@ -871,7 +872,7 @@ do {
"read"
: ((uptr->FUNC == FCCY_WRITE) ?
"write"
: "<?\?\?>")
: "<?>")
),
(unsigned) (uptr->CYL),
(unsigned) (GET_SURF(dkp_ussc, dtype)),

2
NOVA/nova_mta.c
View file

@ -236,7 +236,7 @@ DEVICE mta_dev = {
MTA_NUMDR, 10, 31, 1, 8, 8,
NULL, NULL, &mta_reset,
&mta_boot, &mta_attach, &mta_detach,
&mta_dib, DEV_DISABLE
&mta_dib, DEV_DISABLE | DEV_TAPE
};
/* IOT routine */

6
NOVA/nova_qty.c
View file

@ -105,8 +105,6 @@
extern int32 int_req, dev_busy, dev_done, dev_disable ;
extern int32 sim_switches ;
extern FILE * sim_log ;
extern int32 tmxr_poll ; /* calibrated delay */
t_stat qty_setnl ( UNIT * uptr, int32 val, char * cptr, void * desc ) ;
@ -193,7 +191,7 @@ DEVICE qty_dev =
1, 10, 31, 1, 8, 8,
NULL, NULL, &qty_reset,
NULL, &qty_attach, &qty_detach,
&qty_dib, (DEV_DISABLE | DEV_DIS | DEV_NET)
&qty_dib, (DEV_DISABLE | DEV_DIS | DEV_MUX)
};
#define DG_RETURN( status, data ) (int32)(((status) << IOT_V_REASON) | ((data) & 0x0FFFF) )
@ -222,7 +220,7 @@ DEVICE qty_dev =
#define QTY_LINE_RX_CHAR( line ) (qty_status[ (line) ] & QTY_S_DMASK)
#define QTY_UNIT_ACTIVE( unitp ) ( (unitp)->conn )
#define QTY_LINE_BITS( line, bits ) qty_status[ (line) ] & bits
#define QTY_LINE_BITS( line, bits ) (qty_status[ (line) ] & bits)
#define QTY_LINE_SET_BIT( line, bit ) qty_status[ (line) ] |= (bit) ;
#define QTY_LINE_CLEAR_BIT( line, bit ) qty_status[ (line) ] &= ~(bit) ;

3
NOVA/nova_sys.c
View file

@ -79,9 +79,6 @@ extern int32 MapStat;
#endif
extern int32 sim_switches;
/* SCP data structures
sim_name simulator name string

2
NOVA/nova_tt.c
View file

@ -49,6 +49,7 @@
*/
#include "nova_defs.h"
#include "sim_tmxr.h"
#define UNIT_V_DASHER (UNIT_V_UF + 0) /* Dasher mode */
#define UNIT_DASHER (1 << UNIT_V_DASHER)
@ -186,6 +187,7 @@ return SCPE_OK;
t_stat tti_reset (DEVICE *dptr)
{
tmxr_set_console_units (&tti_unit, &tto_unit);
tti_unit.buf = 0; /* <not DG compatible> */
DEV_CLR_BUSY( INT_TTI ) ;
DEV_CLR_DONE( INT_TTI ) ;

4
NOVA/nova_tt1.c
View file

@ -108,7 +108,7 @@ DEVICE tti1_dev = {
1, 10, 31, 1, 8, 8,
&tmxr_ex, &tmxr_dep, &tti1_reset,
NULL, &tti1_attach, &tti1_detach,
&tti1_dib, DEV_NET | DEV_DISABLE
&tti1_dib, DEV_MUX | DEV_DISABLE
};
/* TTO1 data structures
@ -148,7 +148,7 @@ DEVICE tto1_dev = {
1, 10, 31, 1, 8, 8,
NULL, NULL, &tto1_reset,
NULL, NULL, NULL,
&tto1_dib, DEV_DISABLE
&tto1_dib, DEV_DISABLE | DEV_MUX
};
/* Terminal input: IOT routine */

2
PDP1/pdp1_clk.c
View file

@ -89,7 +89,7 @@ int32 used, incr;
if (clk_dev.flags & DEV_DIS) /* disabled? */
return (stop_inst << IOT_V_REASON) | dat; /* illegal inst */
used = tmxr_poll - (sim_is_active (&clk_unit) - 1);
used = tmxr_poll - (sim_activate_time (&clk_unit) - 1);
incr = (used * CLK_CNTS) / tmxr_poll;
return clk_cntr + incr;
}

7
PDP1/pdp1_cpu.c
View file

@ -335,10 +335,6 @@ int32 hst_p = 0; /* history pointer */
int32 hst_lnt = 0; /* history length */
InstHistory *hst = NULL; /* inst history */
extern UNIT *sim_clock_queue;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_reset (DEVICE *dptr);
@ -503,7 +499,6 @@ DEVICE cpu_dev = {
t_stat sim_instr (void)
{
extern int32 sim_interval;
int32 IR, op, i, t, xct_count;
int32 sign, signd, v, sbs_lvl, byno;
int32 dev, pulse, io_data, sc, skip;
@ -1656,8 +1651,6 @@ char *cptr = (char *) desc;
t_stat r;
t_value sim_eval;
InstHistory *h;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
if (hst_lnt == 0) /* enabled? */
return SCPE_NOFNC;

6
PDP1/pdp1_dcs.c
View file

@ -48,7 +48,7 @@ uint8 dcs_buf[DCS_LINES]; /* line bufffers */
extern int32 iosta, stop_inst;
extern int32 tmxr_poll;
TMLN dcs_ldsc[DCS_LINES] = { 0 }; /* line descriptors */
TMLN dcs_ldsc[DCS_LINES] = { {0} }; /* line descriptors */
TMXR dcs_desc = { DCS_LINES, 0, 0, dcs_ldsc }; /* mux descriptor */
t_stat dcsi_svc (UNIT *uptr);
@ -101,7 +101,7 @@ DEVICE dcs_dev = {
1, 10, 31, 1, 8, 8,
&tmxr_ex, &tmxr_dep, &dcs_reset,
NULL, &dcs_attach, &dcs_detach,
NULL, DEV_NET | DEV_DISABLE | DEV_DIS
NULL, DEV_MUX | DEV_DISABLE | DEV_DIS
};
/* DCSL data structures
@ -172,7 +172,7 @@ DEVICE dcsl_dev = {
DCS_LINES, 10, 31, 1, 8, 8,
NULL, NULL, &dcs_reset,
NULL, NULL, NULL,
NULL, DEV_DIS
NULL, DEV_DIS | DEV_MUX
};
/* DCS IOT routine */

3
PDP1/pdp1_dt.c
View file

@ -250,9 +250,6 @@
extern int32 M[];
extern int32 stop_inst;
extern UNIT cpu_unit;
extern int32 sim_switches;
extern int32 sim_is_running;
extern FILE *sim_deb;
int32 dtsa = 0; /* status A */
int32 dtsb = 0; /* status B */

2
PDP1/pdp1_stddev.c
View file

@ -51,6 +51,7 @@
*/
#include "pdp1_defs.h"
#include "sim_tmxr.h"
#define FIODEC_STOP 013 /* stop code */
#define FIODEC_UC 074
@ -624,6 +625,7 @@ return SCPE_OK;
t_stat tty_reset (DEVICE *dptr)
{
tmxr_set_console_units (&tti_unit, &tto_unit);
tty_buf = 0; /* clear buffer */
tty_uc = 0; /* clear case */
tti_hold = 0; /* clear hold buf */

1
PDP1/pdp1_sys.c
View file

@ -65,7 +65,6 @@ extern int32 M[];
extern int32 PC;
extern int32 ascii_to_fiodec[], fiodec_to_ascii[];
extern int32 sc_map[];
extern int32 sim_switches;
/* SCP data structures and interface routines

6
PDP10/pdp10_cpu.c
View file

@ -198,10 +198,6 @@ int32 hst_p = 0; /* history pointer */
int32 hst_lnt = 0; /* history length */
InstHistory *hst = NULL; /* instruction history */
extern int32 sim_int_char;
extern int32 sim_interval;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
/* Forward and external declarations */
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
@ -2393,8 +2389,6 @@ char *cptr = (char *) desc;
t_stat r;
t_value sim_eval;
InstHistory *h;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
if (hst_lnt == 0) /* enabled? */
return SCPE_NOFNC;

14
PDP10/pdp10_defs.h
View file

@ -624,11 +624,9 @@ typedef struct pdp_dib DIB;
#define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */
#define DEV_V_QBUS (DEV_V_UF + 1) /* Qbus */
#define DEV_V_Q18 (DEV_V_UF + 2) /* Qbus, mem <= 256KB */
#define DEV_V_FLTA (DEV_V_UF + 3) /* float addr */
#define DEV_UBUS (1u << DEV_V_UBUS)
#define DEV_QBUS (1u << DEV_V_QBUS)
#define DEV_Q18 (1u << DEV_V_Q18)
#define DEV_FLTA (1u << DEV_V_FLTA)
#define UNIBUS TRUE /* 18b only */
@ -636,7 +634,7 @@ typedef struct pdp_dib DIB;
/* I/O page layout */
#define IOPAGEBASE 0760000 /* I/O page base */
#define IOPAGEBASE (IO_UBA3 + 0760000) /* I/O page base */
#define IOBA_UBMAP 0763000
#define IOBA_UBMAP1 (IO_UBA1 + IOBA_UBMAP) /* Unibus 1 map */
@ -672,6 +670,7 @@ typedef struct pdp_dib DIB;
#define IOLN_PTR 004
#define IOBA_PTP (IO_UBA3 + 017554) /* PC11 punch */
#define IOLN_PTP 004
#define IOBA_AUTO 0 /* Set by Auto Configure */
/* Common Unibus CSR flags */
@ -697,6 +696,8 @@ typedef struct pdp_dib DIB;
#define INT_V_RP 6 /* RH11/RP,RM drives */
#define INT_V_TU 7 /* RH11/TM03/TU45 */
#define INT_V_DMCRX 13
#define INT_V_DMCTX 14
#define INT_V_XU 15 /* DEUNA/DELUA */
#define INT_V_DZRX 16 /* DZ11 */
#define INT_V_DZTX 17
@ -708,6 +709,8 @@ typedef struct pdp_dib DIB;
#define INT_RP (1u << INT_V_RP)
#define INT_TU (1u << INT_V_TU)
#define INT_DMCRX (1u << INT_V_DMCRX)
#define INT_DMCTX (1u << INT_V_DMCTX)
#define INT_XU (1u << INT_V_XU)
#define INT_DZRX (1u << INT_V_DZRX)
#define INT_DZTX (1u << INT_V_DZTX)
@ -719,6 +722,8 @@ typedef struct pdp_dib DIB;
#define IPL_RP 6 /* int levels */
#define IPL_TU 6
#define IPL_DMCRX 5
#define IPL_DMCTX 5
#define IPL_XU 5
#define IPL_DZRX 5
#define IPL_DZTX 5
@ -747,6 +752,7 @@ typedef struct pdp_dib DIB;
#define VEC_DZRX 0340
#define VEC_DZTX 0344
#define VEC_LP20 0754
#define VEC_AUTO 0 /* Set by Auto Configure */
#define IVCL(dv) (INT_V_##dv)
#define IREQ(dv) int_req
@ -768,8 +774,6 @@ t_stat show_vec (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat show_vec_mux (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat auto_config (char *name, int32 num);
int32 clk_cosched (int32 wait);
/* Global data */
extern t_bool sim_idle_enab;

5
PDP10/pdp10_fe.c
View file

@ -39,6 +39,7 @@
*/
#include "pdp10_defs.h"
#include "sim_tmxr.h"
#define UNIT_DUMMY (1 << UNIT_V_UF)
extern d10 *M;
@ -143,8 +144,7 @@ t_stat fei_svc (UNIT *uptr)
{
int32 temp;
sim_activate (uptr, KBD_WAIT (uptr->wait, clk_cosched (tmxr_poll)));
/* continue poll */
sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */
if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */
return temp;
if (temp & SCPE_BREAK) /* ignore break */
@ -160,6 +160,7 @@ return SCPE_OK;
t_stat fe_reset (DEVICE *dptr)
{
tmxr_set_console_units (&fe_unit[0], &fe_unit[1]);
fei_unit.buf = feo_unit.buf = 0;
M[FE_CTYIN] = M[FE_CTYOUT] = 0;
apr_flg = apr_flg & ~(APRF_ITC | APRF_CON);

331
PDP10/pdp10_ksio.c
View file

@ -74,6 +74,11 @@
#include "sim_sock.h"
#include "sim_tmxr.h"
#define AUTO_MAXC 32 /* Maximum number of controllers */
#define AUTO_CSRBASE 0010
#define AUTO_CSRMAX 04000
#define AUTO_VECBASE 0300
#define XBA_MBZ 0400000 /* ba mbz */
#define eaRB (ea & ~1)
#define GETBYTE(ea,x) ((((ea) & 1)? (x) >> 8: (x)) & 0377)
@ -92,6 +97,9 @@ int32 ubcs[UBANUM] = { 0 }; /* status registers */
int32 ubmap[UBANUM][UMAP_MEMSIZE] = { 0 }; /* Unibus maps */
int32 int_req = 0; /* interrupt requests */
int32 autcon_enb = 1; /* auto configure enabled */
/* Map IO controller numbers to Unibus adapters: -1 = non-existent */
static int iocmap[IO_N_UBA] = { /* map I/O ext to UBA # */
@ -112,9 +120,7 @@ extern d10 pager_word;
extern int32 flags;
extern const int32 pi_l2bit[8];
extern UNIT cpu_unit;
extern FILE *sim_log;
extern jmp_buf save_env;
extern DEVICE *sim_devices[];
extern int32 pi_eval (void);
extern int32 rp_inta (void);
@ -698,6 +704,7 @@ if (GET_IOUBA (newba) != GET_IOUBA (dibp->ba))
if (newba % ((uint32) val)) /* check modulus */
return SCPE_ARG;
dibp->ba = newba; /* store */
autcon_enb = 0; /* autoconfig off */
return SCPE_OK;
}
@ -714,11 +721,16 @@ dptr = find_dev_from_unit (uptr);
if (dptr == NULL)
return SCPE_IERR;
dibp = (DIB *) dptr->ctxt;
if ((dibp == NULL) || (dibp->ba <= IOPAGEBASE))
if (dibp == NULL)
return SCPE_IERR;
if (((dibp->ba>>IO_V_UBA) != 1) &&
((dibp->ba>>IO_V_UBA) != 3))
return SCPE_IERR;
fprintf (st, "address=%07o", dibp->ba);
if (dibp->lnt > 1)
fprintf (st, "-%07o", dibp->ba + dibp->lnt - 1);
if ((dibp->ba & ((1 << IO_V_UBA) - 1)) < AUTO_CSRBASE + AUTO_CSRMAX)
fprintf (st, "*");
return SCPE_OK;
}
@ -747,6 +759,7 @@ if ((r != SCPE_OK) || (newvec == VEC_Q) ||
(newvec & ((dibp->vnum > 1)? 07: 03)))
return SCPE_ARG;
dibp->vec = newvec;
autcon_enb = 0; /* autoconfig off */
return SCPE_OK;
}
@ -777,6 +790,8 @@ else {
if (numvec > 1)
fprintf (st, "-%o", vec + (4 * (numvec - 1)));
}
if (vec >= AUTO_VECBASE)
fprintf (st, "*");
return SCPE_OK;
}
@ -904,16 +919,318 @@ for (i = 0; dib_tab[i] != NULL; i++) { /* print table */
return SCPE_OK;
}
/* Stub auto-configure */
/* Autoconfiguration
t_stat auto_config (char *name, int32 num)
The table reflects the MicroVAX 3900 microcode, with one field addition - the
number of controllers field handles devices where multiple instances
are simulated through a single DEVICE structure (e.g., DZ, VH, DL, DC).
The table has been reviewed, extended and updated to reflect the contents of
the auto configure table in VMS sysgen (V5.5-2)
A minus number of vectors indicates a field that should be calculated
but not placed in the DIB (RQ, TQ dynamic vectors)
An amod value of 0 indicates that all addresses are FIXED
An vmod value of 0 indicates that all vectors are FIXED */
typedef struct {
char *dnam[AUTO_MAXC];
int32 numc;
int32 numv;
uint32 amod;
uint32 vmod;
uint32 fixa[AUTO_MAXC];
uint32 fixv[AUTO_MAXC];
} AUTO_CON;
AUTO_CON auto_tab[] = {/*c #v am vm fxa fxv */
{ { "QBA" }, 1, 0, 0, 0,
{017500} }, /* doorbell - fx CSR, no VEC */
{ { "MCTL" }, 1, 0, 0, 0,
{012100} }, /* MSV11-P - fx CSR, no VEC */
{ { "KE" }, 1, 0, 0, 0,
{017300} }, /* KE11-A - fx CSR, no VEC */
{ { "KG" }, 1, 0, 0, 0,
{010700} }, /* KG11-A - fx CSR, no VEC */
{ { "RHA", "RHB" }, 1, 1, 0, 0,
{016700, 012440}, {0254, 0224} }, /* RH11/RH70 - fx CSR, fx VEC */
{ { "CLK" }, 1, 1, 0, 0,
{017546}, {0100} }, /* KW11L - fx CSR, fx VEC */
{ { "PCLK" }, 1, 1, 0, 0,
{012540}, {0104} }, /* KW11P - fx CSR, fx VEC */
{ { "PTR" }, 1, 1, 0, 0,
{017550}, {0070} }, /* PC11 reader - fx CSR, fx VEC */
{ { "PTP" }, 1, 1, 0, 0,
{017554}, {0074} }, /* PC11 punch - fx CSR, fx VEC */
{ { "RK" }, 1, 1, 0, 0,
{017400}, {0220} }, /* RK11 - fx CSR, fx VEC */
{ { "TM" }, 1, 1, 0, 0,
{012520}, {0224} }, /* TM11 - fx CSR, fx VEC */
{ { "RC" }, 1, 1, 0, 0,
{017440}, {0210} }, /* RC11 - fx CSR, fx VEC */
{ { "RF" }, 1, 1, 0, 0,
{017460}, {0204} }, /* RF11 - fx CSR, fx VEC */
{ { "CR" }, 1, 1, 0, 0,
{017160}, {0230} }, /* CR11 - fx CSR, fx VEC */
{ { "HK" }, 1, 1, 0, 0,
{017440}, {0210} }, /* RK611 - fx CSR, fx VEC */
{ { "LPT" }, 1, 1, 0, 0,
{017514, 004004, 004014, 004024, 004034},
{0200, 0170, 0174, 0270, 0274} }, /* LP11 - fx CSR, fx VEC */
{ { "RB" }, 1, 1, 0, 0,
{015606}, {0250} }, /* RB730 - fx CSR, fx VEC */
{ { "RL" }, 1, 1, 0, 0,
{014400}, {0160} }, /* RL11 - fx CSR, fx VEC */
{ { "RL" }, 1, 1, 0, 0,
{014400}, {0160} }, /* RL11 - fx CSR, fx VEC */
{ { "DCI" }, 1, 2, 0, 8,
{014000, 014010, 014020, 014030,
014040, 014050, 014060, 014070,
014100, 014110, 014120, 014130,
014140, 014150, 014160, 014170,
014200, 014210, 014220, 014230,
014240, 014250, 014260, 014270,
014300, 014310, 014320, 014330,
014340, 014350, 014360, 014370} }, /* DC11 - fx CSRs */
{ { NULL }, 1, 2, 0, 8,
{016500, 016510, 016520, 016530,
016540, 016550, 016560, 016570,
016600, 016610, 016620, 016630,
016640, 016650, 016660, 016670} }, /* TU58 - fx CSRs */
{ { NULL }, 1, 1, 0, 4,
{015200, 015210, 015220, 015230,
015240, 015250, 015260, 015270,
015300, 015310, 015320, 015330,
015340, 015350, 015360, 015370} }, /* DN11 - fx CSRs */
{ { NULL }, 1, 1, 0, 4,
{010500, 010510, 010520, 010530,
010540, 010550, 010560, 010570,
010600, 010610, 010620, 010630,
010640, 010650, 010660, 010670} }, /* DM11B - fx CSRs */
{ { NULL }, 1, 2, 0, 8,
{007600, 007570, 007560, 007550,
007540, 007530, 007520, 007510,
007500, 007470, 007460, 007450,
007440, 007430, 007420, 007410} }, /* DR11C - fx CSRs */
{ { NULL }, 1, 1, 0, 8,
{012600, 012604, 012610, 012614,
012620, 012624, 012620, 012624} }, /* PR611 - fx CSRs */
{ { NULL }, 1, 1, 0, 8,
{017420, 017422, 017424, 017426,
017430, 017432, 017434, 017436} }, /* DT11 - fx CSRs */
{ { NULL }, 1, 2, 0, 8,
{016200, 016240} }, /* DX11 */
{ { "DLI" }, 1, 2, 0, 8,
{016500, 016510, 016520, 016530,
016540, 016550, 016560, 016570,
016600, 016610, 016620, 016630,
016740, 016750, 016760, 016770} }, /* KL11/DL11/DLV11 - fx CSRs */
{ { NULL }, 1, 2, 0, 8, { 0 } }, /* DLV11J - fx CSRs */
{ { NULL }, 1, 2, 8, 8 }, /* DJ11 */
{ { NULL }, 1, 2, 16, 8 }, /* DH11 */
{ { NULL }, 1, 4, 0, 8,
{012000, 012010, 012020, 012030} }, /* GT40 */
{ { NULL }, 1, 2, 0, 8,
{010400} }, /* LPS11 */
{ { NULL }, 1, 2, 8, 8 }, /* DQ11 */
{ { NULL }, 1, 2, 0, 8,
{012400} }, /* KW11W */
{ { NULL }, 1, 2, 8, 8 }, /* DU11 */
{ { NULL }, 1, 2, 8, 8 }, /* DUP11 */
{ { NULL }, 1, 3, 0, 8,
{015000, 015040, 015100, 015140, }}, /* DV11 */
{ { NULL }, 1, 2, 8, 8 }, /* LK11A */
{ { "DMC0", "DMC1", "DMC2", "DMC3" },
1, 2, 8, 8 }, /* DMC11 */
{ { "DZ" }, 1, 2, 8, 8 }, /* DZ11 */
{ { NULL }, 1, 2, 8, 8 }, /* KMC11 */
{ { NULL }, 1, 2, 8, 8 }, /* LPP11 */
{ { NULL }, 1, 2, 8, 8 }, /* VMV21 */
{ { NULL }, 1, 2, 16, 8 }, /* VMV31 */
{ { NULL }, 1, 2, 8, 8 }, /* DWR70 */
{ { "RL", "RLB"}, 1, 1, 8, 4,
{014400}, {0160} }, /* RL11 */
{ { "TS", "TSB", "TSC", "TSD"},
1, 1, 0, 4, /* TS11 */
{012520, 012524, 012530, 012534},
{0224} },
{ { NULL }, 1, 2, 16, 8,
{010460} }, /* LPA11K */
{ { NULL }, 1, 2, 8, 8 }, /* KW11C */
{ { NULL }, 1, 1, 8, 8 }, /* reserved */
{ { "RX", "RY" }, 1, 1, 8, 4,
{017170} , {0264} }, /* RX11/RX211 */
{ { NULL }, 1, 1, 8, 4 }, /* DR11W */
{ { NULL }, 1, 1, 8, 4,
{012410, 012410}, {0124} }, /* DR11B - fx CSRs,vec */
{ { "DMP" }, 1, 2, 8, 8 }, /* DMP11 */
{ { NULL }, 1, 2, 8, 8 }, /* DPV11 */
{ { NULL }, 1, 2, 8, 8 }, /* ISB11 */
{ { NULL }, 1, 2, 16, 8 }, /* DMV11 */
{ { "XU", "XUB" }, 1, 1, 8, 4,
{014510}, {0120} }, /* DEUNA */
{ { "XQ", "XQB" }, 1, -1, 0, 4,
{014440, 014460, 014520, 014540}, {0120} }, /* DEQNA */
{ { "RQ", "RQB", "RQC", "RQD" },
1, -1, 4, 4, /* RQDX3 */
{012150}, {0154} },
{ { NULL }, 1, 8, 32, 4 }, /* DMF32 */
{ { NULL }, 1, 3, 16, 8 }, /* KMS11 */
{ { NULL }, 1, 2, 0, 8,
{004200, 004240, 004300, 004340} }, /* PLC11 */
{ { NULL }, 1, 1, 16, 4 }, /* VS100 */
{ { "TQ", "TQB" }, 1, -1, 4, 4,
{014500}, {0260} }, /* TQK50 */
{ { NULL }, 1, 2, 16, 8 }, /* KMV11 */
{ { NULL }, 1, 2, 0, 8,
{004400, 004440, 004500, 004540} }, /* KTC32 */
{ { NULL }, 1, 2, 0, 8,
{004100} }, /* IEQ11 */
{ { "VH" }, 1, 2, 16, 8 }, /* DHU11/DHQ11 */
{ { NULL }, 1, 6, 32, 4 }, /* DMZ32 */
{ { NULL }, 1, 6, 32, 4 }, /* CP132 */
{ { "TC" }, 1, 1, 0, 0,
{017340}, {0214} }, /* TC11 */
{ { "TA" }, 1, 1, 0, 0,
{017500}, {0260} }, /* TA11 */
{ { NULL }, 1, 2, 64, 8,
{017200} }, /* QVSS - fx CSR */
{ { NULL }, 1, 1, 8, 4 }, /* VS31 */
{ { NULL }, 1, 1, 0, 4,
{016200} }, /* LNV11 - fx CSR */
{ { NULL }, 1, 1, 16, 4 }, /* LNV21/QPSS */
{ { NULL }, 1, 1, 8, 4,
{012570} }, /* QTA - fx CSR */
{ { NULL }, 1, 1, 8, 4 }, /* DSV11 */
{ { NULL }, 1, 2, 8, 8 }, /* CSAM */
{ { NULL }, 1, 2, 8, 8 }, /* ADV11C */
{ { NULL }, 1, 0, 8, 8,
{010440} }, /* AAV11/AAV11C */
{ { NULL }, 1, 2, 8, 8,
{016400}, {0140} }, /* AXV11C - fx CSR,vec */
{ { NULL }, 1, 2, 4, 8,
{010420} }, /* KWV11C - fx CSR */
{ { NULL }, 1, 2, 8, 8,
{016410} }, /* ADV11D - fx CSR */
{ { NULL }, 1, 2, 8, 8,
{016420} }, /* AAV11D - fx CSR */
{ { "QDSS" }, 1, 3, 0, 16,
{017400, 017402, 017404, 017406,
017410, 017412, 017414, 017416} }, /* VCB02 - QDSS - fx CSR */
{ { NULL }, 1, 16, 0, 4,
{004160, 004140, 004120} }, /* DRV11J - fx CSR */
{ { NULL }, 1, 2, 16, 8 }, /* DRQ3B */
{ { NULL }, 1, 1, 8, 4 }, /* VSV24 */
{ { NULL }, 1, 1, 8, 4 }, /* VSV21 */
{ { NULL }, 1, 1, 8, 4 }, /* IBQ01 */
{ { NULL }, 1, 1, 8, 8 }, /* IDV11A */
{ { NULL }, 1, 0, 8, 8 }, /* IDV11B */
{ { NULL }, 1, 0, 8, 8 }, /* IDV11C */
{ { NULL }, 1, 1, 8, 8 }, /* IDV11D */
{ { NULL }, 1, 2, 8, 8 }, /* IAV11A */
{ { NULL }, 1, 0, 8, 8 }, /* IAV11B */
{ { NULL }, 1, 2, 8, 8 }, /* MIRA */
{ { NULL }, 1, 2, 16, 8 }, /* IEQ11 */
{ { NULL }, 1, 2, 32, 8 }, /* ADQ32 */
{ { NULL }, 1, 2, 8, 8 }, /* DTC04, DECvoice */
{ { NULL }, 1, 1, 32, 4 }, /* DESNA */
{ { NULL }, 1, 2, 4, 8 }, /* IGQ11 */
{ { NULL }, 1, 2, 32, 8 }, /* KMV1F */
{ { NULL }, 1, 1, 8, 4 }, /* DIV32 */
{ { NULL }, 1, 2, 4, 8 }, /* DTCN5, DECvoice */
{ { NULL }, 1, 2, 4, 8 }, /* DTC05, DECvoice */
{ { NULL }, 1, 2, 8, 8 }, /* KWV32 (DSV11) */
{ { NULL }, 1, 1, 64, 4 }, /* QZA */
{ { NULL }, -1 } /* end table */
};
#if !defined(DEV_NEXUS)
#if defined(DEV_MBUS)
#define DEV_NEXUS DEV_MBUS
#else
#define DEV_NEXUS 0
#endif
#endif
t_stat auto_config (char *name, int32 nctrl)
{
uint32 csr = IOPAGEBASE + AUTO_CSRBASE;
uint32 vec = VEC_Q + AUTO_VECBASE;
AUTO_CON *autp;
DEVICE *dptr;
DIB *dibp;
uint32 j, vmask, amask;
if (autcon_enb == 0) /* enabled? */
return SCPE_OK;
if (name) { /* updating? */
if (nctrl < 0)
return SCPE_ARG;
for (autp = auto_tab; autp->numc >= 0; autp++) {
for (j = 0; (j < AUTO_MAXC) && autp->dnam[j]; j++) {
if (strcmp (name, autp->dnam[j]) == 0)
autp->numc = nctrl;
}
}
}
for (autp = auto_tab; autp->numc >= 0; autp++) { /* loop thru table */
if (autp->amod) { /* floating csr? */
amask = autp->amod - 1;
csr = (csr + amask) & ~amask; /* align csr */
}
for (j = 0; (j < AUTO_MAXC) && autp->dnam[j]; j++) {
if (autp->dnam[j] == NULL) /* no device? */
break;
dptr = find_dev (autp->dnam[j]); /* find ctrl */
if ((dptr == NULL) || /* enabled, not nexus? */
(dptr->flags & DEV_DIS) ||
(dptr->flags & DEV_NEXUS) )
continue;
dibp = (DIB *) dptr->ctxt; /* get DIB */
if (dibp == NULL) /* not there??? */
return SCPE_IERR;
if (autp->fixa[j]) /* fixed csr avail? */
dibp->ba = IOPAGEBASE + autp->fixa[j]; /* use it */
else { /* no fixed left */
dibp->ba = csr; /* set CSR */
csr += (autp->numc * autp->amod); /* next CSR */
} /* end else */
if (autp->numv) { /* vec needed? */
if (autp->fixv[j]) { /* fixed vec avail? */
if (autp->numv > 0)
dibp->vec = VEC_Q + autp->fixv[j]; /* use it */
}
else { /* no fixed left */
uint32 numv = abs (autp->numv); /* get num vec */
vmask = autp->vmod - 1;
vec = (vec + vmask) & ~vmask; /* align vector */
if (autp->numv > 0)
dibp->vec = vec; /* set vector */
vec += (autp->numc * numv * 4);
} /* end else */
} /* end vec needed */
} /* end for j */
if (autp->amod) /* flt CSR? gap */
csr = csr + 2;
} /* end for i */
return SCPE_OK;
}
/* Stub floating address */
/* Set address floating */
t_stat set_addr_flt (UNIT *uptr, int32 val, char *cptr, void *desc)
{
return SCPE_OK;
DEVICE *dptr;
if (cptr != NULL)
return SCPE_ARG;
if (uptr == NULL)
return SCPE_IERR;
dptr = find_dev_from_unit (uptr);
if (dptr == NULL)
return SCPE_IERR;
return auto_config (NULL, 0); /* autoconfigure */
}

5
PDP10/pdp10_rp.c
View file

@ -1167,7 +1167,8 @@ if (sim_is_active (uptr)) { /* unit active? */
if (uptr->FUNC >= FNC_WCHK) /* data transfer? */
rpcs1 = rpcs1 | CS1_DONE | CS1_TRE; /* set done, err */
}
update_rpcs (CS1_SC, drv); /* request intr */
if (!sim_is_running) /* from console? */
update_rpcs (CS1_SC, drv); /* request intr */
return detach_unit (uptr);
}
@ -1284,7 +1285,7 @@ static const d10 boot_rom_its[] = {
t_stat rp_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern a10 saved_PC;
M[FE_UNIT] = unitno & CS2_M_UNIT;

1
PDP10/pdp10_sys.c
View file

@ -338,7 +338,6 @@ t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
{
d10 data;
int32 wc, fmt;
extern int32 sim_switches;
fmt = 0; /* no fmt */
if (sim_switches & SWMASK ('R')) /* -r? */

14
PDP10/pdp10_tim.c
View file

@ -154,7 +154,7 @@ tempbase[1] = tim_base[1];
if (tim_mult != TIM_MULT_T20) { /* interpolate? */
int32 used;
d10 incr;
used = tmr_poll - (sim_is_active (&tim_unit) - 1);
used = tmr_poll - (sim_activate_time (&tim_unit) - 1);
incr = (d10) (((double) used * TIM_HW_FREQ) /
((double) tmr_poll * (double) clk_tps));
tim_incr_base (tempbase, incr);
@ -211,18 +211,6 @@ else if (t20_idlelock && PROB (100 - tim_t20_prob))
return SCPE_OK;
}
/* Clock coscheduling routine */
int32 clk_cosched (int32 wait)
{
int32 t;
if (tim_mult == TIM_MULT_T20)
return wait;
t = sim_is_active (&tim_unit);
return (t? t - 1: wait);
}
void tim_incr_base (d10 *base, d10 incr)
{
base[1] = base[1] + incr; /* add on incr */

8
PDP10/pdp10_tu.c
View file

@ -297,8 +297,6 @@ extern int32 int_req;
extern int32 ubmap[UBANUM][UMAP_MEMSIZE]; /* Unibus map */
extern int32 ubcs[UBANUM];
extern UNIT cpu_unit;
extern int32 sim_switches;
extern FILE *sim_deb;
int32 tucs1 = 0; /* control/status 1 */
int32 tuwc = 0; /* word count */
@ -415,7 +413,7 @@ DEVICE tu_dev = {
TU_NUMDR, 10, 31, 1, 8, 8,
NULL, NULL, &tu_reset,
&tu_boot, &tu_attach, &tu_detach,
&tu_dib, DEV_UBUS | DEV_DEBUG
&tu_dib, DEV_UBUS | DEV_DEBUG | DEV_TAPE
};
/* I/O dispatch routine, I/O addresses 17772440 - 17772472 */
@ -1015,7 +1013,7 @@ return;
void update_tucs (int32 flag, int32 drv)
{
int32 act = sim_is_active (&tu_unit[drv]);
int32 act = sim_activate_time (&tu_unit[drv]);
if ((flag & ~tucs1) & CS1_DONE) /* DONE 0 to 1? */
tuiff = (tucs1 & CS1_IE)? 1: 0; /* CSTB INTR <- IE */
@ -1273,7 +1271,7 @@ static const d10 boot_rom_its[] = {
t_stat tu_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern a10 saved_PC;
M[FE_UNIT] = 0;

16
PDP11/pdp11_cis.c
View file

@ -170,14 +170,12 @@ typedef struct {
uint32 val[DSTRLNT];
} DSTR;
static DSTR Dstr0 = { 0, 0, 0, 0, 0 };
static DSTR Dstr0 = { 0, {0, 0, 0, 0} };
extern int32 isenable, dsenable;
extern int32 N, Z, V, C, fpd, ipl;
extern int32 R[8], trap_req;
extern int32 sim_interval;
extern uint32 cpu_type;
extern FILE *sim_deb;
int32 ReadDstr (int32 *dscr, DSTR *dec, int32 flag);
void WriteDstr (int32 *dscr, DSTR *dec, int32 flag);
@ -321,14 +319,12 @@ static int32 overbin[128] = {
/* Overpunch to ASCII table: indexed by sign and digit */
static int32 binover[2][16] = {
'{', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I',
'0', '0', '0', '0', '0', '0',
'}', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R',
'0', '0', '0', '0', '0', '0'
{'{', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I',
'0', '0', '0', '0', '0', '0'},
{'}', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R',
'0', '0', '0', '0', '0', '0'}
};
static unsigned char movbuf[65536];
/* CIS emulator */
t_stat cis11 (int32 IR)
@ -342,7 +338,7 @@ uint32 nc, digit, result;
t_stat st;
static DSTR accum, src1, src2, dst;
static DSTR mptable[10];
static DSTR Dstr1 = { 0, 0x10, 0, 0, 0 };
static DSTR Dstr1 = { 0, {0x10, 0, 0, 0} };
old_PC = (PC - 2) & 0177777; /* original PC */
op = IR & 0177; /* IR <6:0> */

16
PDP11/pdp11_cpu.c
View file

@ -25,6 +25,7 @@
cpu PDP-11 CPU
29-Apr-12 RMS Fixed compiler warning (Mark Pizzolato)
19-Mar-12 RMS Fixed declaration of sim_switches (Mark Pizzolato)
29-Dec-08 RMS Fixed failure to clear cpu_bme on RESET (Walter Mueller)
22-Apr-08 RMS Fixed MMR0 treatment in RESET (Walter Mueller)
@ -255,7 +256,7 @@ typedef struct {
extern FILE *sim_log;
uint16 *M = NULL; /* memory */
int32 REGFILE[6][2] = { 0 }; /* R0-R5, two sets */
int32 REGFILE[6][2] = { {0} }; /* R0-R5, two sets */
int32 STACKFILE[4] = { 0 }; /* SP, four modes */
int32 saved_PC = 0; /* program counter */
int32 R[8] = { 0 }; /* working registers */
@ -272,7 +273,7 @@ int32 trap_req = 0; /* trap requests */
int32 int_req[IPL_HLVL] = { 0 }; /* interrupt requests */
int32 PIRQ = 0; /* programmed int req */
int32 STKLIM = 0; /* stack limit */
fpac_t FR[6] = { 0 }; /* fp accumulators */
fpac_t FR[6] = { {0} }; /* fp accumulators */
int32 FPS = 0; /* fp status */
int32 FEC = 0; /* fp exception code */
int32 FEA = 0; /* fp exception addr */
@ -303,12 +304,6 @@ int32 dsmask[4] = { MMR3_KDS, MMR3_SDS, 0, MMR3_UDS }; /* dspace enables */
t_addr cpu_memsize = INIMEMSIZE; /* last mem addr */
extern int32 CPUERR, MAINT;
extern int32 sim_interval;
extern int32 sim_int_char;
extern int32 sim_switches;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern t_bool sim_idle_enab;
extern DEVICE *sim_devices[];
extern CPUTAB cpu_tab[];
/* Function declarations */
@ -605,6 +600,7 @@ MTAB cpu_mod[] = {
{ UNIT_MSIZE, 524288, NULL, "512K", &cpu_set_size},
{ UNIT_MSIZE, 786432, NULL, "768K", &cpu_set_size},
{ UNIT_MSIZE, 1048576, NULL, "1024K", &cpu_set_size},
{ UNIT_MSIZE, 1572864, NULL, "1536K", &cpu_set_size},
{ UNIT_MSIZE, 2097152, NULL, "2048K", &cpu_set_size},
{ UNIT_MSIZE, 3145728, NULL, "3072K", &cpu_set_size},
{ UNIT_MSIZE, 4186112, NULL, "4096K", &cpu_set_size},
@ -1245,7 +1241,7 @@ while (reason == 0) {
else dst = R[dstspec];
}
else {
i = ((cm == pm) && (cm == MD_USR))? calc_ds (pm): calc_is (pm);
i = ((cm == pm) && (cm == MD_USR))? (int32)calc_ds (pm): (int32)calc_is (pm);
dst = ReadW ((GeteaW (dstspec) & 0177777) | i);
}
N = GET_SIGN_W (dst);
@ -3115,8 +3111,6 @@ char *cptr = (char *) desc;
t_value sim_eval[HIST_ILNT];
t_stat r;
InstHistory *h;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
if (hst_lnt == 0) /* enabled? */
return SCPE_NOFNC;

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