vax610_defs,h, vax630_defs.h - Corrected device IPL levels for all qbus devices for the VAX610, VAX620 and VAX630 simulators
This commit is contained in:
Mark Pizzolato
parent
b01fa8fbb0
commit
8a6d90cf57
2 changed files with 91 additions and 101 deletions
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@ -40,8 +40,8 @@
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#undef FULL_VAX
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#endif
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#ifndef _VAX610_DEFS_H_
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#define _VAX610_DEFS_H_ 1
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#ifndef _VAX_610_DEFS_H_
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#define _VAX_610_DEFS_H_ 1
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/* Microcode constructs */
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@ -127,8 +127,6 @@
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#define LP_MBZ84_TEST(r)
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#define LP_MBZ92_TEST(r)
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#define SCB_VALID (ADDR_IS_MEM(SCBB) || ADDR_IS_ROM(SCBB))
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/* Qbus I/O modes */
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#define READ 0 /* PDP-11 compatibility */
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@ -152,10 +150,6 @@
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#define TMR_CLK 0 /* 100Hz clock */
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/* Internal I/O interrupts */
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#define IPL_CLKINT 0x16 /* clock IPL */
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/* I/O system definitions */
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#define DZ_MUXES 4 /* max # of DZV muxes */
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@ -243,43 +237,50 @@ typedef struct {
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#define IOBA_PTP (IOPAGEBASE + 017554) /* PC11 punch */
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#define IOLN_PTP 004
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/* For the KA610, all hardware devices interrupt at IPL 17 regardless
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of their bus request level. Within each IPL, priority is right to left
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/* The KA610 maintains 4 separate hardware IPL levels, IPL 17 to IPL 14;
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however, DEC Qbus controllers all interrupt on IPL 14
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Within each IPL, priority is right to left
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*/
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/* IPL 17 */
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/* IPL 16 */
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#define INT_V_CLK 0 /* clock */
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#define INT_V_RQ 1 /* RQDX3 */
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#define INT_V_RL 2 /* RLV12/RL02 */
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#define INT_V_DZRX 3 /* DZ11 */
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#define INT_V_DZTX 4
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#define INT_V_RP 5 /* RP,RM drives */
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#define INT_V_TS 6 /* TS11/TSV05 */
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#define INT_V_TQ 7 /* TMSCP */
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#define INT_V_XQ 8 /* DEQNA/DELQA */
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#define INT_V_RY 9 /* RXV21 */
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#define INT_V_TTI 10 /* console */
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#define INT_V_TTO 11
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#define INT_V_PTR 12 /* PC11 */
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#define INT_V_PTP 13
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#define INT_V_LPT 14 /* LP11 */
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#define INT_V_CSI 15 /* SSC cons UART */
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#define INT_V_CSO 16
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#define INT_V_TMR0 17 /* SSC timers */
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#define INT_V_TMR1 18
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#define INT_V_VHRX 19 /* DHQ11 */
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#define INT_V_VHTX 20
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#define INT_V_QDSS 21 /* QDSS */
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#define INT_V_CR 22
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#define INT_V_QVSS 23 /* QVSS */
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/* IPL 15 */
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/* IPL 14 - devices through RY are IPL 15 on Unibus systems */
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#define INT_V_RQ 0 /* RQDX3 */
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#define INT_V_RL 1 /* RLV12/RL02 */
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#define INT_V_DZRX 2 /* DZ11 */
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#define INT_V_DZTX 3
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#define INT_V_TS 4 /* TS11/TSV05 */
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#define INT_V_TQ 5 /* TMSCP */
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#define INT_V_XQ 6 /* DEQNA/DELQA */
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#define INT_V_RY 7 /* RXV21 */
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#define INT_V_TTI 8 /* console */
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#define INT_V_TTO 9
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#define INT_V_PTR 10 /* PC11 */
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#define INT_V_PTP 11
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#define INT_V_LPT 12 /* LP11 */
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#define INT_V_CSI 13 /* SSC cons UART */
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#define INT_V_CSO 14
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#define INT_V_TMR0 15 /* SSC timers */
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#define INT_V_TMR1 16
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#define INT_V_VHRX 17 /* DHQ11 */
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#define INT_V_VHTX 18
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#define INT_V_QDSS 19 /* QDSS */
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#define INT_V_CR 20
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#define INT_V_QVSS 21 /* QVSS */
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#define INT_CLK (1u << INT_V_CLK)
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#define INT_RQ (1u << INT_V_RQ)
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#define INT_RL (1u << INT_V_RL)
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#define INT_DZRX (1u << INT_V_DZRX)
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#define INT_DZTX (1u << INT_V_DZTX)
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#define INT_RP (1u << INT_V_RP)
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#define INT_TS (1u << INT_V_TS)
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#define INT_TQ (1u << INT_V_TQ)
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#define INT_XQ (1u << INT_V_XQ)
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@ -299,33 +300,32 @@ typedef struct {
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#define INT_CR (1u << INT_V_CR)
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#define INT_QVSS (1u << INT_V_QVSS)
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#define IPL_CLK (0x17 - IPL_HMIN) /* relative IPL */
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#define IPL_RQ (0x17 - IPL_HMIN)
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#define IPL_RL (0x17 - IPL_HMIN)
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#define IPL_DZRX (0x17 - IPL_HMIN)
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#define IPL_DZTX (0x17 - IPL_HMIN)
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#define IPL_RP (0x17 - IPL_HMIN)
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#define IPL_TS (0x17 - IPL_HMIN)
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#define IPL_TQ (0x17 - IPL_HMIN)
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#define IPL_XQ (0x17 - IPL_HMIN)
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#define IPL_RY (0x17 - IPL_HMIN)
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#define IPL_TTI (0x17 - IPL_HMIN)
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#define IPL_TTO (0x17 - IPL_HMIN)
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#define IPL_PTR (0x17 - IPL_HMIN)
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#define IPL_PTP (0x17 - IPL_HMIN)
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#define IPL_LPT (0x17 - IPL_HMIN)
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#define IPL_CSI (0x17 - IPL_HMIN)
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#define IPL_CSO (0x17 - IPL_HMIN)
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#define IPL_TMR0 (0x17 - IPL_HMIN)
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#define IPL_TMR1 (0x17 - IPL_HMIN)
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#define IPL_VHRX (0x17 - IPL_HMIN)
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#define IPL_VHTX (0x17 - IPL_HMIN)
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#define IPL_QDSS (0x17 - IPL_HMIN)
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#define IPL_CR (0x17 - IPL_HMIN)
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#define IPL_QVSS (0x17 - IPL_HMIN)
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#define IPL_CLK (0x16 - IPL_HMIN) /* relative IPL */
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#define IPL_RQ (0x14 - IPL_HMIN)
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#define IPL_RL (0x14 - IPL_HMIN)
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#define IPL_DZRX (0x14 - IPL_HMIN)
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#define IPL_DZTX (0x14 - IPL_HMIN)
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#define IPL_TS (0x14 - IPL_HMIN)
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#define IPL_TQ (0x14 - IPL_HMIN)
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#define IPL_XQ (0x14 - IPL_HMIN)
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#define IPL_RY (0x14 - IPL_HMIN)
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#define IPL_TTI (0x14 - IPL_HMIN)
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#define IPL_TTO (0x14 - IPL_HMIN)
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#define IPL_PTR (0x14 - IPL_HMIN)
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#define IPL_PTP (0x14 - IPL_HMIN)
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#define IPL_LPT (0x14 - IPL_HMIN)
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#define IPL_CSI (0x14 - IPL_HMIN)
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#define IPL_CSO (0x14 - IPL_HMIN)
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#define IPL_TMR0 (0x14 - IPL_HMIN)
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#define IPL_TMR1 (0x14 - IPL_HMIN)
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#define IPL_VHRX (0x14 - IPL_HMIN)
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#define IPL_VHTX (0x14 - IPL_HMIN)
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#define IPL_QDSS (0x14 - IPL_HMIN)
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#define IPL_CR (0x14 - IPL_HMIN)
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#define IPL_QVSS (0x14 - IPL_HMIN)
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#define IPL_HMAX 0x17 /* highest hwre level */
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#define IPL_HMIN 0x17 /* lowest hwre level */
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#define IPL_HMIN 0x14 /* lowest hwre level */
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#define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */
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#define IPL_SMAX 0xF /* highest swre level */
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@ -342,7 +342,6 @@ typedef struct {
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#define VEC_LPT (VEC_Q + 0200)
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#define VEC_TS (VEC_Q + 0224)
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#define VEC_CR (VEC_Q + 0230)
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#define VEC_RP (VEC_Q + 0254)
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#define VEC_TQ (VEC_Q + 0260)
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#define VEC_RX (VEC_Q + 0264)
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#define VEC_RY (VEC_Q + 0264)
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@ -47,8 +47,8 @@
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#undef FULL_VAX
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#endif
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#ifndef _VAXMOD_DEFS_H_
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#define _VAXMOD_DEFS_H_ 1
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#ifndef _VAX_630_DEFS_H_
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#define _VAX_630_DEFS_H_ 1
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/* Microcode constructs */
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@ -172,8 +172,6 @@
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#define LP_MBZ84_TEST(r)
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#define LP_MBZ92_TEST(r)
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#define SCB_VALID (ADDR_IS_MEM(SCBB) || ADDR_IS_ROM(SCBB))
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/* Qbus I/O modes */
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#define READ 0 /* PDP-11 compatibility */
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@ -197,10 +195,6 @@
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#define TMR_CLK 0 /* 100Hz clock */
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/* Internal I/O interrupts */
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#define IPL_CLKINT 0x16 /* clock IPL */
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/* I/O system definitions */
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#define DZ_MUXES 4 /* max # of DZV muxes */
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@ -286,7 +280,8 @@ typedef struct {
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#define IOBA_PTP (IOPAGEBASE + 017554) /* PC11 punch */
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#define IOLN_PTP 004
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/* The KA65x maintains 4 separate hardware IPL levels, IPL 17 to IPL 14
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/* The KA620/KA630 maintains 4 separate hardware IPL levels, IPL 17 to IPL 14;
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however, DEC Qbus controllers all interrupt on IPL 14
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Within each IPL, priority is right to left
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*/
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@ -298,39 +293,37 @@ typedef struct {
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/* IPL 15 */
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/* IPL 14 - devices through RY are IPL 15 on Unibus systems */
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#define INT_V_RQ 0 /* RQDX3 */
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#define INT_V_RL 1 /* RLV12/RL02 */
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#define INT_V_DZRX 2 /* DZ11 */
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#define INT_V_DZTX 3
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#define INT_V_RP 4 /* RP,RM drives */
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#define INT_V_TS 5 /* TS11/TSV05 */
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#define INT_V_TQ 6 /* TMSCP */
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#define INT_V_XQ 7 /* DEQNA/DELQA */
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#define INT_V_RY 8 /* RXV21 */
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#define INT_V_TS 4 /* TS11/TSV05 */
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#define INT_V_TQ 5 /* TMSCP */
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#define INT_V_XQ 6 /* DEQNA/DELQA */
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#define INT_V_RY 7 /* RXV21 */
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/* IPL 14 */
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#define INT_V_TTI 0 /* console */
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#define INT_V_TTO 1
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#define INT_V_PTR 2 /* PC11 */
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#define INT_V_PTP 3
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#define INT_V_LPT 4 /* LP11 */
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#define INT_V_CSI 5 /* SSC cons UART */
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#define INT_V_CSO 6
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#define INT_V_TMR0 7 /* SSC timers */
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#define INT_V_TMR1 8
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#define INT_V_VHRX 9 /* DHQ11 */
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#define INT_V_VHTX 10
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#define INT_V_QDSS 11 /* QDSS */
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#define INT_V_CR 12
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#define INT_V_QVSS 13 /* QVSS */
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#define INT_V_TTI 8 /* console */
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#define INT_V_TTO 9
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#define INT_V_PTR 10 /* PC11 */
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#define INT_V_PTP 11
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#define INT_V_LPT 12 /* LP11 */
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#define INT_V_CSI 13 /* SSC cons UART */
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#define INT_V_CSO 14
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#define INT_V_TMR0 15 /* SSC timers */
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#define INT_V_TMR1 16
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#define INT_V_VHRX 17 /* DHQ11 */
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#define INT_V_VHTX 18
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#define INT_V_QDSS 19 /* QDSS */
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#define INT_V_CR 20
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#define INT_V_QVSS 21 /* QVSS */
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#define INT_CLK (1u << INT_V_CLK)
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#define INT_RQ (1u << INT_V_RQ)
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#define INT_RL (1u << INT_V_RL)
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#define INT_DZRX (1u << INT_V_DZRX)
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#define INT_DZTX (1u << INT_V_DZTX)
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#define INT_RP (1u << INT_V_RP)
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#define INT_TS (1u << INT_V_TS)
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#define INT_TQ (1u << INT_V_TQ)
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#define INT_XQ (1u << INT_V_XQ)
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@ -351,15 +344,14 @@ typedef struct {
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#define INT_QVSS (1u << INT_V_QVSS)
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#define IPL_CLK (0x16 - IPL_HMIN) /* relative IPL */
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#define IPL_RQ (0x15 - IPL_HMIN)
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#define IPL_RL (0x15 - IPL_HMIN)
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#define IPL_DZRX (0x15 - IPL_HMIN)
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#define IPL_DZTX (0x15 - IPL_HMIN)
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#define IPL_RP (0x15 - IPL_HMIN)
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#define IPL_TS (0x15 - IPL_HMIN)
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#define IPL_TQ (0x15 - IPL_HMIN)
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#define IPL_XQ (0x15 - IPL_HMIN)
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#define IPL_RY (0x15 - IPL_HMIN)
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#define IPL_RQ (0x14 - IPL_HMIN)
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#define IPL_RL (0x14 - IPL_HMIN)
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#define IPL_DZRX (0x14 - IPL_HMIN)
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#define IPL_DZTX (0x14 - IPL_HMIN)
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#define IPL_TS (0x14 - IPL_HMIN)
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#define IPL_TQ (0x14 - IPL_HMIN)
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#define IPL_XQ (0x14 - IPL_HMIN)
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#define IPL_RY (0x14 - IPL_HMIN)
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#define IPL_TTI (0x14 - IPL_HMIN)
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#define IPL_TTO (0x14 - IPL_HMIN)
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#define IPL_PTR (0x14 - IPL_HMIN)
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@ -393,7 +385,6 @@ typedef struct {
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#define VEC_LPT (VEC_Q + 0200)
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#define VEC_TS (VEC_Q + 0224)
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#define VEC_CR (VEC_Q + 0230)
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#define VEC_RP (VEC_Q + 0254)
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#define VEC_TQ (VEC_Q + 0260)
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#define VEC_RX (VEC_Q + 0264)
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#define VEC_RY (VEC_Q + 0264)
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