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VAX, PDP11: Add support to, by default, limit console input data to about 9600bps.

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This is necessary to avoid kernel type ahead buffer overruns when a user
pastes a chunk of data into a console session as described in issue #246

Other console input speeds can be set with SET CONSOLE SPEED=nnn
This commit is contained in:
Mark Pizzolato 2015-11-18 10:51:37 -08:00
parent 53796ba961
commit 9b45833687
7 changed files with 14 additions and 14 deletions
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4
PDP11/pdp11_stddev.c
View file

@ -114,7 +114,7 @@ DIB tti_dib = {
1, IVCL (TTI), VEC_TTI, { NULL } 1, IVCL (TTI), VEC_TTI, { NULL }
}; };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE, 0), SERIAL_IN_WAIT }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE, 0), TMLN_SPD_9600_BPS };
REG tti_reg[] = { REG tti_reg[] = {
{ HRDATAD (BUF, tti_unit.buf, 8, "last data item processed") }, { HRDATAD (BUF, tti_unit.buf, 8, "last data item processed") },
@ -259,7 +259,7 @@ switch ((PA >> 1) & 01) { /* decode PA<1> */
tti_csr = tti_csr & ~CSR_DONE; tti_csr = tti_csr & ~CSR_DONE;
CLR_INT (TTI); CLR_INT (TTI);
*data = tti_unit.buf & 0377; *data = tti_unit.buf & 0377;
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */ sim_activate_after_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
return SCPE_OK; return SCPE_OK;
} /* end switch PA */ } /* end switch PA */

4
VAX/vax610_stddev.c
View file

@ -107,7 +107,7 @@ extern int32 con_halt (int32 code, int32 cc);
DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } }; DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS };
REG tti_reg[] = { REG tti_reg[] = {
{ HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") }, { HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") },
@ -239,7 +239,7 @@ if (tti_csr & CSR_DONE) { /* Input pending ? */
tti_csr = tti_csr & ~CSR_DONE; /* clr done */ tti_csr = tti_csr & ~CSR_DONE; /* clr done */
tti_unit.buf = tti_unit.buf & 0377; /* clr errors */ tti_unit.buf = tti_unit.buf & 0377; /* clr errors */
CLR_INT (TTI); CLR_INT (TTI);
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */ sim_activate_after_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
} }
return t; return t;
} }

4
VAX/vax630_stddev.c
View file

@ -82,7 +82,7 @@ extern int32 sysd_hlt_enb (void);
DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } }; DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS };
REG tti_reg[] = { REG tti_reg[] = {
{ HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") }, { HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") },
@ -215,7 +215,7 @@ if (tti_csr & CSR_DONE) { /* Input pending ? */
tti_csr = tti_csr & ~CSR_DONE; /* clr done */ tti_csr = tti_csr & ~CSR_DONE; /* clr done */
tti_unit.buf = tti_unit.buf & 0377; /* clr errors */ tti_unit.buf = tti_unit.buf & 0377; /* clr errors */
CLR_INT (TTI); CLR_INT (TTI);
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */ sim_activate_after_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
} }
return t; return t;
} }

4
VAX/vax730_stddev.c
View file

@ -219,7 +219,7 @@ t_stat txdb_misc_wr (int32 data);
tti_reg TTI register list tti_reg TTI register list
*/ */
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS };
REG tti_reg[] = { REG tti_reg[] = {
{ HRDATAD (RXDB, tti_buf, 16, "last data item processed") }, { HRDATAD (RXDB, tti_buf, 16, "last data item processed") },
@ -480,7 +480,7 @@ if (tti_csr & CSR_DONE) { /* Input pending ? */
tti_csr = tti_csr & ~CSR_DONE; /* clr done */ tti_csr = tti_csr & ~CSR_DONE; /* clr done */
tti_buf = tti_buf & BMASK; /* clr errors */ tti_buf = tti_buf & BMASK; /* clr errors */
tti_int = 0; tti_int = 0;
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */ sim_activate_after_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
} }
return t; return t;
} }

4
VAX/vax750_stddev.c
View file

@ -211,7 +211,7 @@ extern int32 con_halt (int32 code, int32 cc);
tti_reg TTI register list tti_reg TTI register list
*/ */
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS };
REG tti_reg[] = { REG tti_reg[] = {
{ HRDATAD (RXDB, tti_buf, 16, "last data item processed") }, { HRDATAD (RXDB, tti_buf, 16, "last data item processed") },
@ -474,7 +474,7 @@ if (tti_csr & CSR_DONE) { /* Input pending ? */
tti_csr = tti_csr & ~CSR_DONE; /* clr done */ tti_csr = tti_csr & ~CSR_DONE; /* clr done */
tti_buf = tti_buf & BMASK; /* clr errors */ tti_buf = tti_buf & BMASK; /* clr errors */
tti_int = 0; tti_int = 0;
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */ sim_activate_after_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
} }
return t; return t;
} }

4
VAX/vax780_stddev.c
View file

@ -259,7 +259,7 @@ extern int32 con_halt (int32 code, int32 cc);
tti_reg TTI register list tti_reg TTI register list
*/ */
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS };
REG tti_reg[] = { REG tti_reg[] = {
{ HRDATAD (RXDB, tti_buf, 16, "last data item processed") }, { HRDATAD (RXDB, tti_buf, 16, "last data item processed") },
@ -444,7 +444,7 @@ if (tti_csr & CSR_DONE) { /* Input pending ? */
tti_csr = tti_csr & ~CSR_DONE; /* clr done */ tti_csr = tti_csr & ~CSR_DONE; /* clr done */
tti_buf = tti_buf & BMASK; /* clr errors */ tti_buf = tti_buf & BMASK; /* clr errors */
tti_int = 0; tti_int = 0;
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */ sim_activate_after_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
} }
return t; return t;
} }

4
VAX/vax_stddev.c
View file

@ -139,7 +139,7 @@ extern int32 fault_PC;
DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } }; DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS };
REG tti_reg[] = { REG tti_reg[] = {
{ HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") }, { HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") },
@ -278,7 +278,7 @@ if (tti_csr & CSR_DONE) { /* Input pending ? */
tti_csr = tti_csr & ~CSR_DONE; /* clr done */ tti_csr = tti_csr & ~CSR_DONE; /* clr done */
tti_unit.buf = tti_unit.buf & 0377; /* clr errors */ tti_unit.buf = tti_unit.buf & 0377; /* clr errors */
CLR_INT (TTI); CLR_INT (TTI);
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */ sim_activate_after_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
} }
return t; return t;
} }