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KA10: Fixed bug with page fault during ILDB/IDBP

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Set KMC default state to disabled.
This commit is contained in:
Richard Cornwell 2022-02-24 08:37:12 -05:00
parent f5fc4f0313
commit a45c6c6e4f
6 changed files with 21 additions and 33 deletions
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4
PDP10/ks10_cty.c
View file

@ -127,8 +127,10 @@ t_stat ctyi_svc (UNIT *uptr)
if (Mem_read_word(CTY_IN, &buffer, 0)) if (Mem_read_word(CTY_IN, &buffer, 0))
return SCPE_OK; return SCPE_OK;
sim_debug(DEBUG_DETAIL, &cty_dev, "CTY Read %012llo\n", buffer); sim_debug(DEBUG_DETAIL, &cty_dev, "CTY Read %012llo\n", buffer);
if (buffer & CTY_CHAR) if (buffer & CTY_CHAR) {
cty_interrupt();
return SCPE_OK; return SCPE_OK;
}
ch = sim_poll_kbd (); ch = sim_poll_kbd ();
if (ch & SCPE_KFLAG) { if (ch & SCPE_KFLAG) {
ch = 0177 & sim_tt_inpcvt(ch, TT_GET_MODE (cty_unit[0].flags)); ch = 0177 & sim_tt_inpcvt(ch, TT_GET_MODE (cty_unit[0].flags));

2
PDP10/ks10_kmc.c
View file

@ -627,7 +627,7 @@ DEVICE kmc_dev = {
NULL, /* attach routine */ NULL, /* attach routine */
NULL, /* detach routine */ NULL, /* detach routine */
&kmc_dib, /* context */ &kmc_dib, /* context */
KMC_DIS /* Flags */ DEV_DIS /* Flags */
| DEV_DISABLE | DEV_DISABLE
| DEV_DEBUG, | DEV_DEBUG,
0, /* debug control */ 0, /* debug control */

12
PDP10/ks10_uba.c
View file

@ -169,12 +169,6 @@ uba_write(t_addr addr, int ctl, uint64 data, int access)
(void)(dptr->reset)(dptr); (void)(dptr->reset)(dptr);
} }
} }
for (i = 0; i < 128; i++) {
if ((uba_irq_ctlr[i] & VECT_CTR) == ctl) {
uba_irq_ctlr[i] = 0;
clr_interrupt(i << 2);
}
}
uba_status[ubm] |= (uint32)(0277 & data); uba_status[ubm] |= (uint32)(0277 & data);
return 0; return 0;
} else if ((addr & 077) == 1) { } else if ((addr & 077) == 1) {
@ -208,12 +202,14 @@ uba_read_npr(t_addr addr, uint16 ctl, uint64 *data)
{ {
int ubm = uba_device[ctl]; int ubm = uba_device[ctl];
uint32 map = uba_map[ubm][(077) & (addr >> 11)]; uint32 map = uba_map[ubm][(077) & (addr >> 11)];
t_addr oaddr = addr;
if ((addr & 0400000) != 0) if ((addr & 0400000) != 0)
return 0; return 0;
if ((map & MAP_VALID) == 0) if ((map & MAP_VALID) == 0)
return 0; return 0;
addr = (map & PAGE_MASK) | (addr >> 2) & 0777; addr = (map & PAGE_MASK) | (addr >> 2) & 0777;
*data = M[addr]; *data = M[addr];
sim_debug(DEBUG_DATA, &cpu_dev, "Rd NPR %08o %08o %012llo\n", oaddr, addr, *data);
return 1; return 1;
} }
@ -302,7 +298,7 @@ uba_read_npr_word(t_addr addr, uint16 ctl, uint16 *data)
return 0; return 0;
addr = (map & PAGE_MASK) | (addr >> 2) & 0777; addr = (map & PAGE_MASK) | (addr >> 2) & 0777;
wd = M[addr]; wd = M[addr];
sim_debug(DEBUG_EXP, &cpu_dev, "RD NPR W %08o %08o %012llo m=%o\n", oaddr, addr, wd, map); sim_debug(DEBUG_DATA, &cpu_dev, "RD NPR W %08o %08o %012llo m=%o\n", oaddr, addr, wd, map);
if ((oaddr & 02) == 0) if ((oaddr & 02) == 0)
wd >>= 18; wd >>= 18;
*data = (uint16)(wd & 0177777); *data = (uint16)(wd & 0177777);
@ -326,7 +322,7 @@ uba_write_npr_word(t_addr addr, uint16 ctl, uint16 data)
msk = 0177777; msk = 0177777;
buf = (uint64)(data & msk); buf = (uint64)(data & msk);
wd = M[addr]; wd = M[addr];
sim_debug(DEBUG_EXP, &cpu_dev, "WR NPR W %08o %08o %012llo m=%o\n", oaddr, addr, wd, map); sim_debug(DEBUG_DATA, &cpu_dev, "WR NPR W %08o %08o %012llo m=%o\n", oaddr, addr, wd, map);
if ((oaddr & 02) == 0) { if ((oaddr & 02) == 0) {
buf <<= 18; buf <<= 18;
msk <<= 18; msk <<= 18;

15
PDP10/kx10_cpu.c
View file

@ -644,10 +644,11 @@ MTAB cpu_mod[] = {
/* Simulator debug controls */ /* Simulator debug controls */
DEBTAB cpu_debug[] = { DEBTAB cpu_debug[] = {
{"IRQ", DEBUG_IRQ, "Debug IRQ requests"}, {"IRQ", DEBUG_IRQ, "Debug IRQ requests"},
#if !KS
{"CONI", DEBUG_CONI, "Show coni instructions"}, {"CONI", DEBUG_CONI, "Show coni instructions"},
{"CONO", DEBUG_CONO, "Show cono instructions"}, {"CONO", DEBUG_CONO, "Show cono instructions"},
{"DATAIO", DEBUG_DATAIO, "Show datai and datao instructions"}, {"DATAIO", DEBUG_DATAIO, "Show datai and datao instructions"},
#if KS #else
{"DATA", DEBUG_DATA, "Show data transfers"}, {"DATA", DEBUG_DATA, "Show data transfers"},
{"DETAIL", DEBUG_DETAIL, "Show details about device"}, {"DETAIL", DEBUG_DETAIL, "Show details about device"},
{"EXP", DEBUG_EXP, "Show exception information"}, {"EXP", DEBUG_EXP, "Show exception information"},
@ -4644,11 +4645,11 @@ st_pi:
dev_irq[f] = 0; dev_irq[f] = 0;
break; break;
} }
}
#if DEBUG #if DEBUG
sim_debug(DEBUG_IRQ, &cpu_dev, "vect irq %o %06o\n", pi_enc, AB); sim_debug(DEBUG_IRQ, &cpu_dev, "vect irq %o %06o\n", pi_enc, AB);
#endif #endif
} }
}
#if KS_ITS #if KS_ITS
pi_act |= pi_mask; pi_act |= pi_mask;
#endif #endif
@ -8167,8 +8168,6 @@ mul_done:
if (sim_interval <= 0) { if (sim_interval <= 0) {
if ((reason = sim_process_event()) != SCPE_OK) { if ((reason = sim_process_event()) != SCPE_OK) {
f_pc_inh = 1; f_pc_inh = 1;
f_load_pc = 0;
f_inst_fetch = 0;
set_reg(AC, AR); set_reg(AC, AR);
break; break;
} }
@ -8177,8 +8176,6 @@ mul_done:
pi_rq = check_irq_level(); pi_rq = check_irq_level();
if (pi_rq) { if (pi_rq) {
f_pc_inh = 1; f_pc_inh = 1;
f_load_pc = 0;
f_inst_fetch = 0;
set_reg(AC, AR); set_reg(AC, AR);
break; break;
} }
@ -11367,8 +11364,6 @@ its_wr:
if (sim_interval <= 0) { if (sim_interval <= 0) {
if ((reason = sim_process_event()) != SCPE_OK) { if ((reason = sim_process_event()) != SCPE_OK) {
f_pc_inh = 1; f_pc_inh = 1;
f_load_pc = 0;
f_inst_fetch = 0;
set_reg(AC, AR); set_reg(AC, AR);
break; break;
} }
@ -11377,8 +11372,6 @@ its_wr:
pi_rq = check_irq_level(); pi_rq = check_irq_level();
if (pi_rq) { if (pi_rq) {
f_pc_inh = 1; f_pc_inh = 1;
f_load_pc = 0;
f_inst_fetch = 0;
set_reg(AC, AR); set_reg(AC, AR);
break; break;
} }
@ -11879,6 +11872,7 @@ last:
PC = MB & RMASK; PC = MB & RMASK;
xct_flag = 0; xct_flag = 0;
f_load_pc = 1; f_load_pc = 1;
f_inst_fetch = 1;
f_pc_inh = 1; f_pc_inh = 1;
} }
#endif #endif
@ -11944,6 +11938,7 @@ last:
xct_flag = 0; xct_flag = 0;
f_load_pc = 1; f_load_pc = 1;
f_pc_inh = 1; f_pc_inh = 1;
f_inst_fetch = 1;
if (pi_cycle) { if (pi_cycle) {
pi_cycle = 0; pi_cycle = 0;
FM[(7 << 4) | 2] = fault_data; FM[(7 << 4) | 2] = fault_data;

1
PDP10/kx10_defs.h
View file

@ -584,7 +584,6 @@ void uba_set_irq(DIB *dibp, int vect);
void uba_clr_irq(DIB *dibp, int vect); void uba_clr_irq(DIB *dibp, int vect);
t_addr uba_get_vect(t_addr addr, int lvl, int dev); t_addr uba_get_vect(t_addr addr, int lvl, int dev);
void uba_set_parity(uint16 ctl); void uba_set_parity(uint16 ctl);
uint16 uba_rh_vect(struct pdp_dib *dibp);
int uba_rh_read(DEVICE *dptr, t_addr addr, uint16 *data, int32 access); int uba_rh_read(DEVICE *dptr, t_addr addr, uint16 *data, int32 access);
int uba_rh_write(DEVICE *dptr, t_addr addr, uint16 data, int32 access); int uba_rh_write(DEVICE *dptr, t_addr addr, uint16 data, int32 access);
void uba_reset(); void uba_reset();

14
PDP10/kx10_rh.c
View file

@ -331,6 +331,8 @@ uba_rh_write(DEVICE *dptr, t_addr addr, uint16 data, int32 access) {
rhc->cs2 |= CS2_NED; rhc->cs2 |= CS2_NED;
r = 0; r = 0;
} }
if ((data & CS1_GO) == 0 && (rhc->cs1 & CS1_IE) != 0 && rhc->attn != 0)
uba_set_irq(rhc->dib, rhc->dib->uba_vect);
sim_debug(DEBUG_DETAIL, dptr, "RH%o write %06o %06o %o\n", rhc->drive, sim_debug(DEBUG_DETAIL, dptr, "RH%o write %06o %06o %o\n", rhc->drive,
addr, data, access); addr, data, access);
return r; return r;
@ -411,12 +413,6 @@ uba_rh_read(DEVICE *dptr, t_addr addr, uint16 *data, int32 access) {
return r; return r;
} }
uint16
uba_rh_vect(struct pdp_dib *dibp)
{
return dibp->uba_vect;
}
#else #else
/* 0-37 mass bus register. /* 0-37 mass bus register.
70 SBAR, block address. 70 SBAR, block address.
@ -812,7 +808,6 @@ void rh_reset(DEVICE *dptr, struct rh_if *rhc)
rhc->wcr = 0; rhc->wcr = 0;
rhc->cda = 0; rhc->cda = 0;
rhc->drive = 0; rhc->drive = 0;
// rhc->xfer_drive = -1;
#if KS #if KS
rhc->dib = (DIB *)dptr->ctxt; rhc->dib = (DIB *)dptr->ctxt;
rhc->cs1 = 0; rhc->cs1 = 0;
@ -820,6 +815,7 @@ void rh_reset(DEVICE *dptr, struct rh_if *rhc)
rhc->dba = 0; rhc->dba = 0;
rhc->dbb = 0; rhc->dbb = 0;
rhc->error = 0; rhc->error = 0;
uba_clr_irq(rhc->dib, rhc->dib->uba_vect);
#endif #endif
} }
@ -828,10 +824,10 @@ void rh_setattn(struct rh_if *rhc, int unit)
{ {
rhc->attn |= 1<<unit; rhc->attn |= 1<<unit;
#if KS #if KS
if ((rhc->status & BUSY) == 0 && (rhc->cs1 & CS1_IE) != 0) if ((rhc->cs1 & CS1_IE) != 0)
uba_set_irq(rhc->dib, rhc->dib->uba_vect); uba_set_irq(rhc->dib, rhc->dib->uba_vect);
#else #else
if ((rhc->status & BUSY) == 0 && (rhc->status & IADR_ATTN) != 0) if ((rhc->status & IADR_ATTN) != 0)
set_interrupt(rhc->devnum, rhc->status); set_interrupt(rhc->devnum, rhc->status);
#endif #endif
} }