All VAX: Added model-specific AST validation test
From page 6-6 of DEC STD 032 (the VAX architecture spec): "Execution of MTPR src, #PR$_ASTLVL with src<31:0> GEQU 5 results in UNDEFINED behavior. The preferred implementation is to cause a reserved operand fault." MicroVAX II, CVAX, and Rigel all conform to the preferred behavior, as does the current simulator, which was written from the CVAX microcode. NVAX masks to 3b and does not take an exception on a value GEQU 5. The 1982 Architecture Handbook describes ASTLVL as a 3b register, with src<31:3> ignored/read as zero, and exceptions taken on values GEQU 5. The780 microcode masks the input value to 3b before doing the GEQU 5 test. The ASTLVL test needs to be model specific. I suspect the behavior became undefined when MicroVAX II simplified the original test to save a microword. I do not see how the code fragment Matt references could work on a MicroVAX II, which was supported under 4.5. Perhaps the device Matt mentions couldn't exist on a MicroVAX II? For those who wants the gory details... uVAX, CVAX, and Rigel do an unsigned compare on the unmasked src and the constant 5. Carry out means reserved operand. Overflow is ignored. So an input of 0x80000002 - 0x00000005 (done in the data path as 0x80000002 + 0xFFFFFFFB) generates overflow (ignored) and carry out. # Conflicts: # VAX/vaxmod_defs.h
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8 changed files with 26 additions and 6 deletions
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@ -132,7 +132,7 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc
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#define ADDR_IS_ROM(x) (0)
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#define ADDR_IS_ROM(x) (0)
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#define ADDR_IS_NVR(x) (0)
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#define ADDR_IS_NVR(x) (0)
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/* Machine specific reserved operand tests (all NOPs) */
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/* Machine specific reserved operand tests (mostly NOPs) */
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#define ML_PA_TEST(r)
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#define ML_PA_TEST(r)
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#define ML_LR_TEST(r)
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#define ML_LR_TEST(r)
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@ -142,6 +142,8 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc
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#define LP_MBZ84_TEST(r)
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#define LP_MBZ84_TEST(r)
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#define LP_MBZ92_TEST(r)
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#define LP_MBZ92_TEST(r)
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#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
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/* Qbus I/O modes */
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/* Qbus I/O modes */
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#define READ 0 /* PDP-11 compatibility */
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#define READ 0 /* PDP-11 compatibility */
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@ -182,7 +182,7 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc
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#define ADDR_IS_CDG(x) (0)
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#define ADDR_IS_CDG(x) (0)
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/* Machine specific reserved operand tests (all NOPs) */
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/* Machine specific reserved operand tests (mostly NOPs) */
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#define ML_PA_TEST(r)
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#define ML_PA_TEST(r)
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#define ML_LR_TEST(r)
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#define ML_LR_TEST(r)
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@ -192,6 +192,8 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc
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#define LP_MBZ84_TEST(r)
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#define LP_MBZ84_TEST(r)
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#define LP_MBZ92_TEST(r)
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#define LP_MBZ92_TEST(r)
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#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
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/* Qbus I/O modes */
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/* Qbus I/O modes */
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#define READ 0 /* PDP-11 compatibility */
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#define READ 0 /* PDP-11 compatibility */
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@ -116,6 +116,9 @@
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#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
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#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
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#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
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#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
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#define MT_AST_TEST(r) r = (r) & 07; \
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if ((r) > AST_MAX) RSVD_OPND_FAULT
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/* Memory */
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/* Memory */
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#define MAXMEMWIDTH 21 /* max mem, 16k chips */
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#define MAXMEMWIDTH 21 /* max mem, 16k chips */
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@ -137,6 +137,9 @@
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#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
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#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
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#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
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#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
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#define MT_AST_TEST(r) r = (r) & 07; \
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if ((r) > AST_MAX) RSVD_OPND_FAULT
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/* Memory */
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/* Memory */
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#define MAXMEMWIDTH 21 /* max mem, 16k chips */
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#define MAXMEMWIDTH 21 /* max mem, 16k chips */
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@ -23,6 +23,7 @@
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used in advertising or otherwise to promote the sale, use or other dealings
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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in this Software without prior written authorization from Robert M Supnik.
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18-May-17 RMS Added model-specific AST validation test
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19-Jan-17 RMS Moved CR to BR6 (Mark Pizzolato)
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19-Jan-17 RMS Moved CR to BR6 (Mark Pizzolato)
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29-Mar-15 RMS Added model specific IPR max
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29-Mar-15 RMS Added model specific IPR max
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16-Dec-14 RMS Removed TQ boot code (780 VMB doesn't support tape boot)
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16-Dec-14 RMS Removed TQ boot code (780 VMB doesn't support tape boot)
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@ -154,6 +155,9 @@
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#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
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#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
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#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
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#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
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#define MT_AST_TEST(r) r = (r) & 07; \
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if ((r) > AST_MAX) RSVD_OPND_FAULT
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/* Memory */
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/* Memory */
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#define MAXMEMWIDTH 23 /* max mem, MS780C */
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#define MAXMEMWIDTH 23 /* max mem, MS780C */
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@ -174,6 +174,9 @@
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#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
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#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
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#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
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#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
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#define MT_AST_TEST(r) r = (r) & 07; \
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if ((r) > AST_MAX) RSVD_OPND_FAULT
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/* Memory */
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/* Memory */
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#define MAXMEMWIDTH 25 /* max mem, 4MB boards */
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#define MAXMEMWIDTH 25 /* max mem, 4MB boards */
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@ -1506,8 +1506,7 @@ switch (prn) { /* case on reg # */
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break;
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break;
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case MT_ASTLVL: /* ASTLVL */
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case MT_ASTLVL: /* ASTLVL */
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if (val > AST_MAX) /* > 4? fault */
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MT_AST_TEST (val); /* trim, test val */
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RSVD_OPND_FAULT;
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ASTLVL = val;
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ASTLVL = val;
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break;
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break;
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@ -1,6 +1,6 @@
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/* vaxmod_defs.h: VAX model-specific definitions file
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/* vaxmod_defs.h: VAX model-specific definitions file
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Copyright (c) 1998-2013, Robert M Supnik
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Copyright (c) 1998-2017, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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copy of this software and associated documentation files (the "Software"),
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@ -23,6 +23,7 @@
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used in advertising or otherwise to promote the sale, use or other dealings
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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in this Software without prior written authorization from Robert M Supnik.
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18-May-17 RMS Added model-specific AST validation test
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20-Dec-13 RMS Added prototypes for unaligned IO and register handling
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20-Dec-13 RMS Added prototypes for unaligned IO and register handling
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11-Dec-11 RMS Moved all Qbus devices to BR4; deleted RP definitions
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11-Dec-11 RMS Moved all Qbus devices to BR4; deleted RP definitions
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25-Nov-11 RMS Added VEC_QBUS definition
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25-Nov-11 RMS Added VEC_QBUS definition
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@ -232,7 +233,7 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc
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#define ADDR_IS_QVM(x) ((((uint32) (x)) >= QVMBASE) && \
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#define ADDR_IS_QVM(x) ((((uint32) (x)) >= QVMBASE) && \
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(((uint32) (x)) < (QVMBASE + QVMSIZE)))
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(((uint32) (x)) < (QVMBASE + QVMSIZE)))
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/* Machine specific reserved operand tests (all NOPs) */
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/* Machine specific reserved operand tests (mostly NOPs) */
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#define ML_PA_TEST(r)
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#define ML_PA_TEST(r)
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#define ML_LR_TEST(r)
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#define ML_LR_TEST(r)
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@ -242,6 +243,9 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc
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#define LP_MBZ84_TEST(r)
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#define LP_MBZ84_TEST(r)
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#define LP_MBZ92_TEST(r)
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#define LP_MBZ92_TEST(r)
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#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
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/* Qbus I/O modes */
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/* Qbus I/O modes */
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#define READ 0 /* PDP-11 compatibility */
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#define READ 0 /* PDP-11 compatibility */
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