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PDP8/PDP11/VAX: Support high speed character input on console and other multiplexer ports instead of limiting input data rate to 1 character per clock tick.

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This commit is contained in:
Mark Pizzolato 2013-10-23 07:50:39 -07:00
parent c8ae76cb65
commit be46bac750
12 changed files with 39 additions and 48 deletions
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4
PDP11/pdp11_dc.c
View file

@ -158,12 +158,13 @@ DIB dci_dib = {
2, IVCL (DCI), VEC_AUTO, { &dci_iack, &dco_iack }, IOLN_DC, 2, IVCL (DCI), VEC_AUTO, { &dci_iack, &dco_iack }, IOLN_DC,
}; };
UNIT dci_unit = { UDATA (&dci_svc, 0, 0), KBD_POLL_WAIT }; UNIT dci_unit = { UDATA (&dci_svc, 0, 0), SERIAL_IN_WAIT };
REG dci_reg[] = { REG dci_reg[] = {
{ BRDATAD (BUF, dci_buf, DEV_RDX, 8, DCX_LINES, "input control/stats register") }, { BRDATAD (BUF, dci_buf, DEV_RDX, 8, DCX_LINES, "input control/stats register") },
{ BRDATAD (CSR, dci_csr, DEV_RDX, 16, DCX_LINES, "input buffer") }, { BRDATAD (CSR, dci_csr, DEV_RDX, 16, DCX_LINES, "input buffer") },
{ GRDATAD (IREQ, dci_ireq, DEV_RDX, DCX_LINES, 0, "interrupt requests") }, { GRDATAD (IREQ, dci_ireq, DEV_RDX, DCX_LINES, 0, "interrupt requests") },
{ DRDATAD (TIME, dci_unit.wait, 24, "input polling interval"), PV_LEFT },
{ DRDATA (LINES, dcx_desc.lines, 6), REG_HRO }, { DRDATA (LINES, dcx_desc.lines, 6), REG_HRO },
{ GRDATA (DEVADDR, dci_dib.ba, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVADDR, dci_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVIOLN, dci_dib.lnt, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVIOLN, dci_dib.lnt, DEV_RDX, 32, 0), REG_HRO },
@ -289,6 +290,7 @@ switch ((PA >> 1) & 03) { /* decode PA<2:1> */
case 01: /* dci buf */ case 01: /* dci buf */
dci_clr_int (ln); dci_clr_int (ln);
*data = dci_buf[ln]; *data = dci_buf[ln];
sim_activate_abs (&dci_unit, dci_unit.wait);
return SCPE_OK; return SCPE_OK;
case 02: /* dco csr */ case 02: /* dco csr */

4
PDP11/pdp11_dl.c
View file

@ -122,11 +122,12 @@ DIB dli_dib = {
2, IVCL (DLI), VEC_AUTO, { &dli_iack, &dlo_iack }, IOLN_DL, 2, IVCL (DLI), VEC_AUTO, { &dli_iack, &dlo_iack }, IOLN_DL,
}; };
UNIT dli_unit = { UDATA (&dli_svc, 0, 0), KBD_POLL_WAIT }; UNIT dli_unit = { UDATA (&dli_svc, 0, 0), SERIAL_IN_WAIT };
REG dli_reg[] = { REG dli_reg[] = {
{ BRDATA (BUF, dli_buf, DEV_RDX, 16, DLX_LINES) }, { BRDATA (BUF, dli_buf, DEV_RDX, 16, DLX_LINES) },
{ BRDATA (CSR, dli_csr, DEV_RDX, 16, DLX_LINES) }, { BRDATA (CSR, dli_csr, DEV_RDX, 16, DLX_LINES) },
{ DRDATAD (TIME, dli_unit.wait, 24, "input polling interval"), PV_LEFT },
{ GRDATA (IREQ, dli_ireq[DLI_RCI], DEV_RDX, DLX_LINES, 0) }, { GRDATA (IREQ, dli_ireq[DLI_RCI], DEV_RDX, DLX_LINES, 0) },
{ GRDATA (DSI, dli_ireq[DLI_DSI], DEV_RDX, DLX_LINES, 0) }, { GRDATA (DSI, dli_ireq[DLI_DSI], DEV_RDX, DLX_LINES, 0) },
{ DRDATA (LINES, dlx_desc.lines, 6), REG_HRO }, { DRDATA (LINES, dlx_desc.lines, 6), REG_HRO },
@ -245,6 +246,7 @@ switch ((PA >> 1) & 03) { /* decode PA<2:1> */
*data = dli_buf[ln] & DLIBUF_RD; *data = dli_buf[ln] & DLIBUF_RD;
dli_csr[ln] &= ~CSR_DONE; /* clr rcv done */ dli_csr[ln] &= ~CSR_DONE; /* clr rcv done */
dli_clr_int (ln, DLI_RCI); /* clr rcv int req */ dli_clr_int (ln, DLI_RCI); /* clr rcv int req */
sim_activate_abs (&dli_unit, dli_unit.wait);
return SCPE_OK; return SCPE_OK;
case 02: /* tto csr */ case 02: /* tto csr */

19
PDP11/pdp11_stddev.c
View file

@ -113,17 +113,17 @@ DIB tti_dib = {
1, IVCL (TTI), VEC_TTI, { NULL } 1, IVCL (TTI), VEC_TTI, { NULL }
}; };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE, 0), 0 }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE, 0), SERIAL_IN_WAIT };
REG tti_reg[] = { REG tti_reg[] = {
{ ORDATA (BUF, tti_unit.buf, 8) }, { HRDATAD (BUF, tti_unit.buf, 8, "last data item processed") },
{ ORDATA (CSR, tti_csr, 16) }, { HRDATAD (CSR, tti_csr, 16, "control/status register") },
{ FLDATA (INT, IREQ (TTI), INT_V_TTI) }, { FLDATAD (INT, IREQ (TTI), INT_V_TTI, "interrupt pending flag") },
{ FLDATA (ERR, tti_csr, CSR_V_ERR) }, { FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATA (DONE, tti_csr, CSR_V_DONE) }, { FLDATAD (ERR, tti_csr, CSR_V_ERR, "device error flag (CSR<15>)") },
{ FLDATA (IE, tti_csr, CSR_V_IE) }, { FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT }, { DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT }, { DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT },
{ NULL } { NULL }
}; };
@ -258,6 +258,7 @@ switch ((PA >> 1) & 01) { /* decode PA<1> */
tti_csr = tti_csr & ~CSR_DONE; tti_csr = tti_csr & ~CSR_DONE;
CLR_INT (TTI); CLR_INT (TTI);
*data = tti_unit.buf & 0377; *data = tti_unit.buf & 0377;
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
return SCPE_OK; return SCPE_OK;
} /* end switch PA */ } /* end switch PA */

3
PDP8/pdp8_tt.c
View file

@ -66,7 +66,7 @@ t_stat tty_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc);
DIB tti_dib = { DEV_TTI, 1, { &tti } }; DIB tti_dib = { DEV_TTI, 1, { &tti } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_KSR, 0), 0 }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_KSR, 0), SERIAL_IN_WAIT };
REG tti_reg[] = { REG tti_reg[] = {
{ ORDATA (BUF, tti_unit.buf, 8) }, { ORDATA (BUF, tti_unit.buf, 8) },
@ -164,6 +164,7 @@ switch (IR & 07) { /* decode IR<9:11> */
case 6: /* KRB */ case 6: /* KRB */
dev_done = dev_done & ~INT_TTI; /* clear flag */ dev_done = dev_done & ~INT_TTI; /* clear flag */
int_req = int_req & ~INT_TTI; int_req = int_req & ~INT_TTI;
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
return (tti_unit.buf); /* return buffer */ return (tti_unit.buf); /* return buffer */
default: default:

31
PDP8/pdp8_ttx.c
View file

@ -92,7 +92,7 @@ void ttx_enbdis (int32 dis);
DIB ttix_dib = { DEV_KJ8, 8, DIB ttix_dib = { DEV_KJ8, 8,
{ &ttix, &ttox, &ttix, &ttox, &ttix, &ttox, &ttix, &ttox } }; { &ttix, &ttox, &ttix, &ttox, &ttix, &ttox, &ttix, &ttox } };
UNIT ttix_unit = { UDATA (&ttix_svc, UNIT_IDLE|UNIT_ATTABLE, 0), KBD_POLL_WAIT }; UNIT ttix_unit = { UDATA (&ttix_svc, UNIT_IDLE|UNIT_ATTABLE, 0), SERIAL_IN_WAIT };
REG ttix_reg[] = { REG ttix_reg[] = {
{ BRDATA (BUF, ttix_buf, 8, 8, TTX_LINES) }, { BRDATA (BUF, ttix_buf, 8, 8, TTX_LINES) },
@ -119,30 +119,12 @@ MTAB ttix_mod[] = {
{ 0 } { 0 }
}; };
#define DBG_XMT TMXR_DBG_XMT /* display Transmitted Data */
#define DBG_RCV TMXR_DBG_RCV /* display Received Data */
#define DBG_MDM TMXR_DBG_MDM /* display Modem Signals */
#define DBG_CON TMXR_DBG_CON /* display connection activities */
#define DBG_TRC TMXR_DBG_TRC /* display trace routine calls */
#define DBG_ASY TMXR_DBG_ASY /* display Asynchronous Activities */
DEBTAB ttx_debug[] = {
{"XMT", DBG_XMT},
{"RCV", DBG_RCV},
{"MDM", DBG_MDM},
{"CON", DBG_CON},
{"TRC", DBG_TRC},
{"ASY", DBG_ASY},
{0}
};
DEVICE ttix_dev = { DEVICE ttix_dev = {
"TTIX", &ttix_unit, ttix_reg, ttix_mod, "TTIX", &ttix_unit, ttix_reg, ttix_mod,
1, 10, 31, 1, 8, 8, 1, 10, 31, 1, 8, 8,
&tmxr_ex, &tmxr_dep, &ttix_reset, &tmxr_ex, &tmxr_dep, &ttix_reset,
NULL, &ttx_attach, &ttx_detach, NULL, &ttx_attach, &ttx_detach,
&ttix_dib, DEV_DEBUG | DEV_MUX | DEV_DISABLE, &ttix_dib, DEV_MUX | DEV_DISABLE,
0, ttx_debug
}; };
/* TTOx data structures /* TTOx data structures
@ -188,8 +170,7 @@ DEVICE ttox_dev = {
4, 10, 31, 1, 8, 8, 4, 10, 31, 1, 8, 8,
NULL, NULL, &ttox_reset, NULL, NULL, &ttox_reset,
NULL, NULL, NULL, NULL, NULL, NULL,
NULL, DEV_DISABLE | DEV_DEBUG, NULL, DEV_DISABLE
0, ttx_debug
}; };
/* Terminal input: IOT routine */ /* Terminal input: IOT routine */
@ -200,7 +181,6 @@ int32 pulse = inst & 07; /* IOT pulse */
int32 ln = TTX_GETLN (inst); /* line # */ int32 ln = TTX_GETLN (inst); /* line # */
int32 itti = (INT_TTI1 << ln); /* rx intr */ int32 itti = (INT_TTI1 << ln); /* rx intr */
int32 itto = (INT_TTO1 << ln); /* tx intr */ int32 itto = (INT_TTO1 << ln); /* tx intr */
int32 itti_data;
switch (pulse) { /* case IR<9:11> */ switch (pulse) { /* case IR<9:11> */
@ -219,7 +199,7 @@ switch (pulse) { /* case IR<9:11> */
return 0; /* clear AC */ return 0; /* clear AC */
case 4: /* KRS */ case 4: /* KRS */
return ttix_buf[ln]; /* return buf */ return (AC | ttix_buf[ln]); /* return buf */
case 5: /* KIE */ case 5: /* KIE */
if (AC & 1) if (AC & 1)
@ -231,9 +211,8 @@ switch (pulse) { /* case IR<9:11> */
case 6: /* KRB */ case 6: /* KRB */
dev_done = dev_done & ~itti; /* clear flag */ dev_done = dev_done & ~itti; /* clear flag */
int_req = int_req & ~itti; int_req = int_req & ~itti;
itti_data = ttix_buf[ln]; /* return buf */
sim_activate_abs (&ttix_unit, ttix_unit.wait); /* check soon for more input */ sim_activate_abs (&ttix_unit, ttix_unit.wait); /* check soon for more input */
return itti_data; return ttix_buf[ln]; /* return buf */
default: default:
return (stop_inst << IOT_V_REASON) + AC; return (stop_inst << IOT_V_REASON) + AC;

3
VAX/vax610_stddev.c
View file

@ -107,7 +107,7 @@ extern int32 con_halt (int32 code, int32 cc);
DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } }; DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT };
REG tti_reg[] = { REG tti_reg[] = {
{ HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") }, { HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") },
@ -238,6 +238,7 @@ int32 t = tti_unit.buf; /* char + error */
tti_csr = tti_csr & ~CSR_DONE; /* clr done */ tti_csr = tti_csr & ~CSR_DONE; /* clr done */
tti_unit.buf = tti_unit.buf & 0377; /* clr errors */ tti_unit.buf = tti_unit.buf & 0377; /* clr errors */
CLR_INT (TTI); CLR_INT (TTI);
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
return t; return t;
} }

3
VAX/vax630_stddev.c
View file

@ -82,7 +82,7 @@ extern int32 sysd_hlt_enb (void);
DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } }; DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT };
REG tti_reg[] = { REG tti_reg[] = {
{ HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") }, { HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") },
@ -214,6 +214,7 @@ int32 t = tti_unit.buf; /* char + error */
tti_csr = tti_csr & ~CSR_DONE; /* clr done */ tti_csr = tti_csr & ~CSR_DONE; /* clr done */
tti_unit.buf = tti_unit.buf & 0377; /* clr errors */ tti_unit.buf = tti_unit.buf & 0377; /* clr errors */
CLR_INT (TTI); CLR_INT (TTI);
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
return t; return t;
} }

3
VAX/vax730_stddev.c
View file

@ -243,7 +243,7 @@ t_bool td_test_xfr (UNIT *uptr, int32 state);
tti_reg TTI register list tti_reg TTI register list
*/ */
UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), 0 }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT };
REG tti_reg[] = { REG tti_reg[] = {
{ HRDATAD (RXDB, tti_buf, 16, "last data item processed") }, { HRDATAD (RXDB, tti_buf, 16, "last data item processed") },
@ -629,6 +629,7 @@ int32 t = tti_buf; /* char + error */
tti_csr = tti_csr & ~CSR_DONE; /* clr done */ tti_csr = tti_csr & ~CSR_DONE; /* clr done */
tti_buf = tti_buf & BMASK; /* clr errors */ tti_buf = tti_buf & BMASK; /* clr errors */
tti_int = 0; tti_int = 0;
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
return t; return t;
} }

3
VAX/vax750_stddev.c
View file

@ -243,7 +243,7 @@ extern int32 con_halt (int32 code, int32 cc);
tti_reg TTI register list tti_reg TTI register list
*/ */
UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), 0 }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT };
REG tti_reg[] = { REG tti_reg[] = {
{ HRDATAD (RXDB, tti_buf, 16, "last data item processed") }, { HRDATAD (RXDB, tti_buf, 16, "last data item processed") },
@ -622,6 +622,7 @@ int32 t = tti_buf; /* char + error */
tti_csr = tti_csr & ~CSR_DONE; /* clr done */ tti_csr = tti_csr & ~CSR_DONE; /* clr done */
tti_buf = tti_buf & BMASK; /* clr errors */ tti_buf = tti_buf & BMASK; /* clr errors */
tti_int = 0; tti_int = 0;
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
return t; return t;
} }

3
VAX/vax780_stddev.c
View file

@ -259,7 +259,7 @@ extern int32 con_halt (int32 code, int32 cc);
tti_reg TTI register list tti_reg TTI register list
*/ */
UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), 0 }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT };
REG tti_reg[] = { REG tti_reg[] = {
{ HRDATAD (RXDB, tti_buf, 16, "last data item processed") }, { HRDATAD (RXDB, tti_buf, 16, "last data item processed") },
@ -443,6 +443,7 @@ int32 t = tti_buf; /* char + error */
tti_csr = tti_csr & ~CSR_DONE; /* clr done */ tti_csr = tti_csr & ~CSR_DONE; /* clr done */
tti_buf = tti_buf & BMASK; /* clr errors */ tti_buf = tti_buf & BMASK; /* clr errors */
tti_int = 0; tti_int = 0;
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
return t; return t;
} }

8
VAX/vax860_stddev.c
View file

@ -274,10 +274,10 @@ extern int32 con_halt (int32 code, int32 cc);
*/ */
UNIT tti_unit[] = { UNIT tti_unit[] = {
{ UDATA (&tti_svc, TT_MODE_8B, 0), 0 }, { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 },
{ UDATA (&tti_svc, TT_MODE_8B, 0), 0 }, { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 },
{ UDATA (&tti_svc, TT_MODE_8B, 0), 0 }, { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 },
{ UDATA (&tti_svc, TT_MODE_8B, 0), 0 }, { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 },
}; };
REG tti_reg[] = { REG tti_reg[] = {

3
VAX/vax_stddev.c
View file

@ -139,7 +139,7 @@ extern int32 fault_PC;
DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } }; DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT };
REG tti_reg[] = { REG tti_reg[] = {
{ HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") }, { HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") },
@ -277,6 +277,7 @@ int32 t = tti_unit.buf; /* char + error */
tti_csr = tti_csr & ~CSR_DONE; /* clr done */ tti_csr = tti_csr & ~CSR_DONE; /* clr done */
tti_unit.buf = tti_unit.buf & 0377; /* clr errors */ tti_unit.buf = tti_unit.buf & 0377; /* clr errors */
CLR_INT (TTI); CLR_INT (TTI);
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
return t; return t;
} }