folkert/simh-testsetgenerator
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

3B2: Header refactoring and cleanup

Browse source 
This change signficantly improves header hygiene in the 3B2 project by
moving global symbols out of 3b2_defs.h and into the appropriate
individual module header files.

Each compilation unit now includes:

  - its appropriate matching .h file
  - any other .h files necessary for linting and compilation

Each header file in turn includes 3b2_defs.h, which contains truly
global symbols, and which pulls in sim_defs.h and exports global
devices.
This commit is contained in:
Seth Morabito 2021-08-11 19:43:51 -07:00
parent 78d3d1b560
commit c02491f733
40 changed files with 235 additions and 131 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
3B2/3b2_cpu.c
View file

@ -42,16 +42,28 @@
* - "WE 32200 Microprocessor Information Manual" (AT&T, 1988) * - "WE 32200 Microprocessor Information Manual" (AT&T, 1988)
* *
*/ */
#include <sim_defs.h>
#include "3b2_defs.h"
#include "3b2_cpu.h" #include "3b2_cpu.h"
#if defined(REV3) #if defined(REV3)
#include "3b2_rev2_mau.h" /* TODO: Replace with Rev 3 MAU when implemented */
#include "3b2_rev3_csr.h"
#include "3b2_rev3_mmu.h"
#include "rom_rev3_bin.h" #include "rom_rev3_bin.h"
#else #else
#include "3b2_rev2_csr.h"
#include "3b2_rev2_mau.h"
#include "3b2_rev2_mmu.h"
#include "3b2_id.h"
#include "rom_rev2_bin.h" #include "rom_rev2_bin.h"
#endif #endif
#include "3b2_dmac.h"
#include "3b2_io.h"
#include "3b2_iu.h"
#include "3b2_mem.h"
#include "3b2_stddev.h"
#define MAX_SUB_RETURN_SKIP 9 #define MAX_SUB_RETURN_SKIP 9
uint32 rom_size = BOOT_CODE_SIZE; uint32 rom_size = BOOT_CODE_SIZE;

14
3B2/3b2_cpu.h
View file

@ -31,7 +31,7 @@
#ifndef _3B2_CPU_H_ #ifndef _3B2_CPU_H_
#define _3B2_CPU_H_ #define _3B2_CPU_H_
#include "sim_defs.h" #include "3b2_defs.h"
/* Execution Modes */ /* Execution Modes */
#define EX_LVL_KERN 0 #define EX_LVL_KERN 0
@ -649,4 +649,16 @@ void cpu_clear_irq(uint8 ipl, uint16 csr_flags);
(d) = (uint8) (a)[(p)++]; \ (d) = (uint8) (a)[(p)++]; \
} }
extern volatile int32 stop_reason;
extern uint32 rom_size;
extern instr *cpu_instr;
extern t_bool cpu_nmi;
extern uint32 *ROM;
extern uint32 *RAM;
extern uint32 R[NUM_REGISTERS];
extern REG cpu_reg[];
extern UNIT cpu_unit;
extern uint8 fault;
extern t_bool cpu_km;
#endif #endif

6
3B2/3b2_ctc.c
View file

@ -28,9 +28,13 @@
from the author. from the author.
*/ */
#include "3b2_defs.h"
#include "3b2_ctc.h" #include "3b2_ctc.h"
#include "sim_disk.h"
#include "3b2_mem.h"
#include "3b2_io.h"
#define CTQRESIZE 20 #define CTQRESIZE 20
#define CTQCESIZE 16 #define CTQCESIZE 16

3
3B2/3b2_ctc.h
View file

@ -51,8 +51,7 @@
#ifndef _3B2_CTC_H_ #ifndef _3B2_CTC_H_
#define _3B2_CTC_H_ #define _3B2_CTC_H_
#include "sim_defs.h" #include "3b2_defs.h"
#include "3b2_io.h"
#define CTC_ID 0x0005 #define CTC_ID 0x0005
#define CTC_IPL 12 #define CTC_IPL 12

59
3B2/3b2_defs.h
View file

@ -31,38 +31,16 @@
#ifndef _3B2_DEFS_H_ #ifndef _3B2_DEFS_H_
#define _3B2_DEFS_H_ #define _3B2_DEFS_H_
#include "sim_defs.h"
#include "sim_tmxr.h"
#include "sim_disk.h"
#include <setjmp.h> #include <setjmp.h>
#include "sim_defs.h"
#if defined(REV3) #if defined(REV3)
#include "3b2_rev3_defs.h" #include "3b2_rev3_defs.h"
#include "3b2_rev3_csr.h"
#include "3b2_rev3_mmu.h"
#include "3b2_rev2_mau.h" /* Use Rev 2 MAU until Rev 3 is implemented */
#include "3b2_scsi.h"
#else #else
#include "3b2_rev2_defs.h" #include "3b2_rev2_defs.h"
#include "3b2_rev2_csr.h"
#include "3b2_rev2_mau.h"
#include "3b2_rev2_mmu.h"
#include "3b2_id.h"
#include "3b2_ctc.h"
#endif #endif
#include "3b2_sys.h"
#include "3b2_cpu.h"
#include "3b2_io.h"
#include "3b2_stddev.h"
#include "3b2_mem.h"
#include "3b2_dmac.h"
#include "3b2_if.h"
#include "3b2_iu.h"
#include "3b2_ports.h"
#include "3b2_ni.h"
#ifndef FALSE #ifndef FALSE
#define FALSE 0 #define FALSE 0
#endif #endif
@ -159,25 +137,6 @@ noret __libc_longjmp(jmp_buf buf, int val);
/* Global symbols */ /* Global symbols */
extern volatile int32 stop_reason;
extern CIO_STATE cio[CIO_SLOTS];
extern uint32 rom_size;
extern instr *cpu_instr;
extern t_bool cpu_nmi;
extern uint32 *ROM;
extern uint32 *RAM;
extern uint32 R[NUM_REGISTERS];
extern REG cpu_reg[];
extern UNIT cpu_unit;
extern uint8 fault;
extern t_bool cpu_km;
extern char sim_name[];
extern REG *sim_PC;
extern int32 sim_emax;
extern int32 tmxr_poll;
extern DEBTAB sys_deb_tab[]; extern DEBTAB sys_deb_tab[];
extern DEVICE contty_dev; extern DEVICE contty_dev;
extern DEVICE cpu_dev; extern DEVICE cpu_dev;
@ -196,17 +155,9 @@ extern DEVICE timer_dev;
extern DEVICE tod_dev; extern DEVICE tod_dev;
extern DEVICE tti_dev; extern DEVICE tti_dev;
extern DEVICE tto_dev; extern DEVICE tto_dev;
#if defined(REV3)
extern IU_PORT iu_console; extern DEVICE flt_dev;
extern IU_PORT iu_contty; extern DEVICE ha_dev;
extern IF_STATE if_state; #endif
extern MMU_STATE mmu_state;
extern DMA_STATE dma_state;
extern t_bool id_drq;
extern t_bool if_irq;
extern t_bool cio_skip_seqbit;
extern t_bool iu_increment_a;
extern t_bool iu_increment_b;
#endif #endif

10
3B2/3b2_dmac.c
View file

@ -28,9 +28,17 @@
from the author. from the author.
*/ */
#include "3b2_defs.h"
#include "3b2_dmac.h" #include "3b2_dmac.h"
#if defined(REV2)
#include "3b2_id.h"
#endif
#include "3b2_cpu.h"
#include "3b2_if.h"
#include "3b2_iu.h"
#include "3b2_mem.h"
DMA_STATE dma_state; DMA_STATE dma_state;
UNIT dmac_unit[] = { UNIT dmac_unit[] = {

4
3B2/3b2_dmac.h
View file

@ -31,7 +31,7 @@
#ifndef _3B2_DMAC_H_ #ifndef _3B2_DMAC_H_
#define _3B2_DMAC_H_ #define _3B2_DMAC_H_
#include "sim_defs.h" #include "3b2_defs.h"
#define DMA_MODE_VERIFY 0 #define DMA_MODE_VERIFY 0
#define DMA_MODE_WRITE 1 /* Write to memory from device */ #define DMA_MODE_WRITE 1 /* Write to memory from device */
@ -79,4 +79,6 @@ void dmac_service_drqs();
void dmac_generic_dma(uint8 channel, uint32 service_address); void dmac_generic_dma(uint8 channel, uint32 service_address);
uint32 dma_address(uint8 channel, uint32 offset, t_bool r); uint32 dma_address(uint8 channel, uint32 offset, t_bool r);
extern DMA_STATE dma_state;
#endif #endif

5
3B2/3b2_id.c
View file

@ -42,9 +42,12 @@
* HD135 11 1224 15 18 512 Maxtor XT1190 * HD135 11 1224 15 18 512 Maxtor XT1190
*/ */
#include "3b2_defs.h"
#include "3b2_id.h" #include "3b2_id.h"
#include "sim_disk.h"
#include "3b2_cpu.h"
#define ID_SEEK_WAIT 50 #define ID_SEEK_WAIT 50
#define ID_SEEK_BASE 700 #define ID_SEEK_BASE 700
#define ID_RECAL_WAIT 6000 #define ID_RECAL_WAIT 6000

4
3B2/3b2_id.h
View file

@ -31,7 +31,7 @@
#ifndef __3B2_ID_H__ #ifndef __3B2_ID_H__
#define __3B2_ID_H__ #define __3B2_ID_H__
#include "sim_defs.h" #include "3b2_defs.h"
#define ID0 0 #define ID0 0
#define ID1 1 #define ID1 1
@ -174,4 +174,6 @@ void id_handle_data(uint8 val);
void id_handle_command(uint8 val); void id_handle_command(uint8 val);
void id_after_dma(); void id_after_dma();
extern t_bool id_drq;
#endif #endif

12
3B2/3b2_if.c
View file

@ -28,9 +28,19 @@
from the author. from the author.
*/ */
#include "3b2_defs.h"
#include "3b2_if.h" #include "3b2_if.h"
#include "sim_disk.h"
#if defined(REV3)
#include "3b2_rev3_csr.h"
#else
#include "3b2_rev2_csr.h"
#endif
#include "3b2_cpu.h"
/* Static function declarations */ /* Static function declarations */
static SIM_INLINE void if_set_irq(); static SIM_INLINE void if_set_irq();
static SIM_INLINE void if_clear_irq(); static SIM_INLINE void if_clear_irq();

5
3B2/3b2_if.h
View file

@ -31,7 +31,7 @@
#ifndef __3B2_IF_H__ #ifndef __3B2_IF_H__
#define __3B2_IF_H__ #define __3B2_IF_H__
#include "sim_defs.h" #include "3b2_defs.h"
typedef struct { typedef struct {
uint8 data; uint8 data;
@ -126,4 +126,7 @@ void if_after_dma();
CONST char *if_description(DEVICE *dptr); CONST char *if_description(DEVICE *dptr);
t_stat if_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); t_stat if_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
extern IF_STATE if_state;
extern t_bool if_irq;
#endif #endif

17
3B2/3b2_io.c
View file

@ -28,9 +28,24 @@
from the author. from the author.
*/ */
#include "3b2_defs.h"
#include "3b2_io.h" #include "3b2_io.h"
#if defined(REV3)
#include "3b2_rev3_csr.h"
#include "3b2_rev3_mmu.h"
#else
#include "3b2_id.h"
#include "3b2_rev2_csr.h"
#include "3b2_rev2_mmu.h"
#endif
#include "3b2_cpu.h"
#include "3b2_dmac.h"
#include "3b2_if.h"
#include "3b2_iu.h"
#include "3b2_mem.h"
#include "3b2_stddev.h"
CIO_STATE cio[CIO_SLOTS] = {{0}}; CIO_STATE cio[CIO_SLOTS] = {{0}};
#if defined(REV3) #if defined(REV3)

7
3B2/3b2_io.h
View file

@ -28,8 +28,6 @@
from the author. from the author.
*/ */
/* Reference Documentation /* Reference Documentation
* ======================= * =======================
* *
@ -111,8 +109,7 @@
#ifndef _3B2_IO_H_ #ifndef _3B2_IO_H_
#define _3B2_IO_H_ #define _3B2_IO_H_
#include "sim_defs.h" #include "3b2_defs.h"
#include "sim_tmxr.h"
#define CRC_POLYNOMIAL 0xEDB88320 #define CRC_POLYNOMIAL 0xEDB88320
@ -248,4 +245,6 @@ void io_write(uint32 pa, uint32 val, size_t size);
void dump_entry(uint32 dbits, DEVICE *dev, CONST char *type, void dump_entry(uint32 dbits, DEVICE *dev, CONST char *type,
uint32 esize, cio_entry *entry, uint8 *app_data); uint32 esize, cio_entry *entry, uint8 *app_data);
extern CIO_STATE cio[CIO_SLOTS];
#endif #endif

13
3B2/3b2_iu.c
View file

@ -28,9 +28,20 @@
from the author. from the author.
*/ */
#include "3b2_defs.h"
#include "3b2_iu.h" #include "3b2_iu.h"
#include "sim_tmxr.h"
#if defined(REV3)
#include "3b2_rev3_csr.h"
#else
#include "3b2_rev2_csr.h"
#endif
#include "3b2_cpu.h"
#include "3b2_dmac.h"
#include "3b2_mem.h"
#include "3b2_stddev.h"
/* Static function declarations */ /* Static function declarations */
static SIM_INLINE void iu_w_cmd(uint8 portno, uint8 val); static SIM_INLINE void iu_w_cmd(uint8 portno, uint8 val);

8
3B2/3b2_iu.h
View file

@ -31,8 +31,7 @@
#ifndef __3B2_IU_H__ #ifndef __3B2_IU_H__
#define __3B2_IU_H__ #define __3B2_IU_H__
#include "sim_defs.h" #include "3b2_defs.h"
#include "sim_tmxr.h"
#define CMD_ERX 0x01 /* Enable receiver */ #define CMD_ERX 0x01 /* Enable receiver */
#define CMD_DRX 0x02 /* Disable receiver */ #define CMD_DRX 0x02 /* Disable receiver */
@ -207,4 +206,9 @@ void iu_dma_contty(uint8 channel, uint32 service_address);
void increment_modep_a(); void increment_modep_a();
void increment_modep_b(); void increment_modep_b();
extern IU_PORT iu_console;
extern IU_PORT iu_contty;
extern t_bool iu_increment_a;
extern t_bool iu_increment_b;
#endif #endif

12
3B2/3b2_mem.c
View file

@ -28,9 +28,19 @@
from the author. from the author.
*/ */
#include "3b2_defs.h"
#include "3b2_mem.h" #include "3b2_mem.h"
#if defined(REV3)
#include "3b2_rev3_csr.h"
#include "3b2_rev3_mmu.h"
#else
#include "3b2_rev2_csr.h"
#include "3b2_rev2_mmu.h"
#endif
#include "3b2_cpu.h"
#include "3b2_io.h"
t_bool addr_is_rom(uint32 pa) t_bool addr_is_rom(uint32 pa)
{ {
return (pa < rom_size); return (pa < rom_size);

2
3B2/3b2_mem.h
View file

@ -31,7 +31,7 @@
#ifndef _3B2_MEM_H_ #ifndef _3B2_MEM_H_
#define _3B2_MEM_H_ #define _3B2_MEM_H_
#include "sim_defs.h" #include "3b2_defs.h"
uint32 pread_w(uint32 pa); uint32 pread_w(uint32 pa);
void pwrite_w(uint32 pa, uint32 val); void pwrite_w(uint32 pa, uint32 val);

5
3B2/3b2_ni.c
View file

@ -93,10 +93,11 @@
* *
*/ */
#include "3b2_defs.h"
#include "3b2_ni.h" #include "3b2_ni.h"
#include <math.h> #include "3b2_io.h"
#include "3b2_mem.h"
#include "3b2_stddev.h"
/* State container for the card */ /* State container for the card */
NI_STATE ni; NI_STATE ni;

2
3B2/3b2_ni.h
View file

@ -31,7 +31,7 @@
#ifndef _3B2_NI_H_ #ifndef _3B2_NI_H_
#define _3B2_NI_H_ #define _3B2_NI_H_
#include "sim_defs.h" #include "3b2_defs.h"
#include "sim_ether.h" #include "sim_ether.h"
#define NI_ID 0x0002 #define NI_ID 0x0002

10
3B2/3b2_ports.c
View file

@ -42,9 +42,15 @@
* *
*/ */
#include "3b2_defs.h"
#include "3b2_ports.h" #include "3b2_ports.h"
#include "sim_tmxr.h"
#include "3b2_cpu.h"
#include "3b2_io.h"
#include "3b2_mem.h"
#include "3b2_stddev.h"
/* Static function declarations */ /* Static function declarations */
static t_stat ports_show_queue_common(FILE *st, UNIT *uptr, int32 val, static t_stat ports_show_queue_common(FILE *st, UNIT *uptr, int32 val,
CONST void *desc, t_bool rq); CONST void *desc, t_bool rq);
@ -375,7 +381,7 @@ static void ports_cmd(uint8 cid, cio_entry *rentry, uint8 *rapp_data)
tmxr_set_config_line(&ports_ldsc[ln], line_config); tmxr_set_config_line(&ports_ldsc[ln], line_config);
} }
centry.byte_count = sizeof(PPC_OPTIONS); centry.byte_count = 20;
centry.opcode = PPC_OPTIONS; centry.opcode = PPC_OPTIONS;
centry.subdevice = rentry->subdevice; centry.subdevice = rentry->subdevice;
centry.address = rentry->address; centry.address = rentry->address;

2
3B2/3b2_ports.h
View file

@ -45,7 +45,7 @@
#ifndef _3B2_PORTS_H_ #ifndef _3B2_PORTS_H_
#define _3B2_PORTS_H_ #define _3B2_PORTS_H_
#include "sim_defs.h" #include "3b2_defs.h"
#define PORTS_ID 0x0003 #define PORTS_ID 0x0003
#define PORTS_IPL 10 #define PORTS_IPL 10

5
3B2/3b2_rev2_csr.c
View file

@ -28,9 +28,12 @@
from the author. from the author.
*/ */
#include "3b2_defs.h"
#include "3b2_rev2_csr.h" #include "3b2_rev2_csr.h"
#include "3b2_cpu.h"
#include "3b2_sys.h"
#include "3b2_stddev.h"
uint16 csr_data; uint16 csr_data;
BITFIELD csr_bits[] = { BITFIELD csr_bits[] = {

4
3B2/3b2_rev2_csr.h
View file

@ -31,7 +31,7 @@
#ifndef _3B2_REV2_CSR_H_ #ifndef _3B2_REV2_CSR_H_
#define _3B2_REV2_CSR_H_ #define _3B2_REV2_CSR_H_
#include "sim_defs.h" #include "3b2_defs.h"
/* CSR */ /* CSR */
t_stat csr_svc(UNIT *uptr); t_stat csr_svc(UNIT *uptr);
@ -41,4 +41,6 @@ t_stat csr_reset(DEVICE *dptr);
uint32 csr_read(uint32 pa, size_t size); uint32 csr_read(uint32 pa, size_t size);
void csr_write(uint32 pa, uint32 val, size_t size); void csr_write(uint32 pa, uint32 val, size_t size);
extern uint16 csr_data;
#endif /* 3B2_REV2_CSR_H_ */ #endif /* 3B2_REV2_CSR_H_ */

4
3B2/3b2_rev2_defs.h
View file

@ -31,8 +31,6 @@
#ifndef _3B2_REV2_DEFS_H_ #ifndef _3B2_REV2_DEFS_H_
#define _3B2_REV2_DEFS_H_ #define _3B2_REV2_DEFS_H_
#include "sim_defs.h"
#define NUM_REGISTERS 16 #define NUM_REGISTERS 16
#define DEFMEMSIZE MSIZ_4M #define DEFMEMSIZE MSIZ_4M
@ -119,6 +117,4 @@
#define DMA_C 0x48 #define DMA_C 0x48
#define DMA_IF 0x4E #define DMA_IF 0x4E
extern uint16 csr_data;
#endif /* _3B2_REV2_DEFS_H_ */ #endif /* _3B2_REV2_DEFS_H_ */

13
3B2/3b2_rev2_mau.c
View file

@ -81,10 +81,19 @@
--------------------------------------------------------------------- ---------------------------------------------------------------------
*/ */
#include "3b2_rev2_mau.h"
#include <math.h> #include <math.h>
#include "3b2_defs.h" /* TODO: Simplify after 3b2_rev3_mau is implemented */
#include "3b2_rev2_mau.h" #if defined(REV3)
#include "3b2_rev3_mmu.h"
#else
#include "3b2_rev2_mmu.h"
#endif
#include "3b2_cpu.h"
#include "3b2_mem.h"
#define MAU_ID 0 /* Coprocessor ID of MAU */ #define MAU_ID 0 /* Coprocessor ID of MAU */

4
3B2/3b2_rev2_mmu.c
View file

@ -28,9 +28,11 @@
from the author. from the author.
*/ */
#include "3b2_defs.h"
#include "3b2_rev2_mmu.h" #include "3b2_rev2_mmu.h"
#include "3b2_sys.h"
#include "3b2_cpu.h"
UNIT mmu_unit = { UDATA(NULL, 0, 0) }; UNIT mmu_unit = { UDATA(NULL, 0, 0) };
MMU_STATE mmu_state; MMU_STATE mmu_state;

3
3B2/3b2_rev2_mmu.h
View file

@ -32,7 +32,6 @@
#define _3B2_REV2_MMU_H_ #define _3B2_REV2_MMU_H_
#include "sim_defs.h" #include "sim_defs.h"
#include "3b2_rev2_defs.h"
/************************************************************************ /************************************************************************
* *
@ -382,4 +381,6 @@ t_stat mmu_decode_va(uint32 va, uint8 r_acc, t_bool fc, uint32 *pa);
void mmu_enable(); void mmu_enable();
void mmu_disable(); void mmu_disable();
extern MMU_STATE mmu_state;
#endif /* _3B2_REV2_MMU_H_ */ #endif /* _3B2_REV2_MMU_H_ */

10
3B2/3b2_rev2_sys.c
View file

@ -30,6 +30,16 @@
#include "3b2_defs.h" #include "3b2_defs.h"
#include "3b2_cpu.h"
#include "3b2_ctc.h"
#include "3b2_id.h"
#include "3b2_if.h"
#include "3b2_iu.h"
#include "3b2_ni.h"
#include "3b2_ports.h"
#include "3b2_rev2_mau.h"
#include "3b2_stddev.h"
char sim_name[] = "AT&T 3B2/400"; char sim_name[] = "AT&T 3B2/400";
DEVICE *sim_devices[] = { DEVICE *sim_devices[] = {

6
3B2/3b2_rev3_csr.c
View file

@ -28,7 +28,11 @@
from the author. from the author.
*/ */
#include "3b2_defs.h" #include "3b2_rev3_csr.h"
#include "3b2_cpu.h"
#include "3b2_if.h"
#include "3b2_stddev.h"
uint32 csr_data; uint32 csr_data;

4
3B2/3b2_rev3_csr.h
View file

@ -31,7 +31,7 @@
#ifndef _3B2_400_CSR_H_ #ifndef _3B2_400_CSR_H_
#define _3B2_400_CSR_H_ #define _3B2_400_CSR_H_
#include "sim_defs.h" #include "3b2_defs.h"
t_stat csr_svc(UNIT *uptr); t_stat csr_svc(UNIT *uptr);
t_stat csr_ex(t_value *vptr, t_addr exta, UNIT *uptr, int32 sw); t_stat csr_ex(t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
@ -40,4 +40,6 @@ t_stat csr_reset(DEVICE *dptr);
uint32 csr_read(uint32 pa, size_t size); uint32 csr_read(uint32 pa, size_t size);
void csr_write(uint32 pa, uint32 val, size_t size); void csr_write(uint32 pa, uint32 val, size_t size);
extern uint32 csr_data;
#endif #endif

6
3B2/3b2_rev3_defs.h
View file

@ -31,8 +31,6 @@
#ifndef _3B2_REV3_DEFS_H_ #ifndef _3B2_REV3_DEFS_H_
#define _3B2_REV3_DEFS_H_ #define _3B2_REV3_DEFS_H_
#include "sim_defs.h"
#define NUM_REGISTERS 32 #define NUM_REGISTERS 32
#define DEFMEMSIZE MSIZ_4M #define DEFMEMSIZE MSIZ_4M
@ -131,8 +129,4 @@
#define CSRABRT (1u << 30) /* Abort Switch Activated */ #define CSRABRT (1u << 30) /* Abort Switch Activated */
#define CSRRRST (1u << 31) /* System Reset Request */ #define CSRRRST (1u << 31) /* System Reset Request */
extern DEVICE flt_dev;
extern DEVICE ha_dev;
extern uint32 csr_data;
#endif #endif

6
3B2/3b2_rev3_mmu.c
View file

@ -28,9 +28,11 @@
from the author. from the author.
*/ */
#include "3b2_defs.h"
#include "3b2_rev3_mmu.h" #include "3b2_rev3_mmu.h"
#include <scp.h>
#include "3b2_cpu.h"
#include "3b2_mem.h"
#include "3b2_rev3_csr.h"
UNIT mmu_unit = { UDATA(NULL, 0, 0) }; UNIT mmu_unit = { UDATA(NULL, 0, 0) };

2
3B2/3b2_rev3_mmu.h
View file

@ -31,7 +31,7 @@
#ifndef _3B2_1000_MMU_H_ #ifndef _3B2_1000_MMU_H_
#define _3B2_1000_MMU_H_ #define _3B2_1000_MMU_H_
#include "sim_defs.h" #include "3b2_defs.h"
#define MMU_SRS 4 /* Section RAM array size (words) */ #define MMU_SRS 4 /* Section RAM array size (words) */
#define MMU_SDCS 8 /* SD Cache H/L array size */ #define MMU_SDCS 8 /* SD Cache H/L array size */

10
3B2/3b2_rev3_sys.c
View file

@ -29,7 +29,15 @@
*/ */
#include "3b2_defs.h" #include "3b2_defs.h"
#include "3b2_sys.h"
#include "3b2_cpu.h"
#include "3b2_if.h"
#include "3b2_iu.h"
#include "3b2_ni.h"
#include "3b2_ports.h"
#include "3b2_rev2_mau.h" /* TODO: Replace with Rev 3 MAU when implemented */
#include "3b2_scsi.h"
#include "3b2_stddev.h"
char sim_name[] = "AT&T 3B2/600G"; char sim_name[] = "AT&T 3B2/600G";

9
3B2/3b2_scsi.c
View file

@ -1,4 +1,4 @@
/* 3b2_scsi.h: AT&T 3B2 SCSI (CM195W) feature card /* 3b2_scsi.c: AT&T 3B2 SCSI (CM195W) feature card
Copyright (c) 2020, Seth J. Morabito Copyright (c) 2020, Seth J. Morabito
@ -28,11 +28,14 @@
from the author. from the author.
*/ */
#include "3b2_scsi.h"
#include "sim_scsi.h" #include "sim_scsi.h"
#include "sim_tape.h" #include "sim_tape.h"
#include "3b2_defs.h" #include "3b2_cpu.h"
#include "3b2_scsi.h" #include "3b2_io.h"
#include "3b2_mem.h"
#define PUMP_CRC 0x201b3617 #define PUMP_CRC 0x201b3617

2
3B2/3b2_scsi.h
View file

@ -31,7 +31,7 @@
#ifndef _3B2_SCSI_H_ #ifndef _3B2_SCSI_H_
#define _3B2_SCSI_H_ #define _3B2_SCSI_H_
#include "sim_defs.h" #include "3b2_defs.h"
/* CIO Opcodes */ /* CIO Opcodes */
#define HA_BOOT 0x0a #define HA_BOOT 0x0a

9
3B2/3b2_stddev.c
View file

@ -38,9 +38,16 @@
- tod MM58174A Real-Time-Clock - tod MM58174A Real-Time-Clock
*/ */
#include "3b2_defs.h"
#include "3b2_stddev.h" #include "3b2_stddev.h"
#if defined(REV3)
#include "3b2_rev3_csr.h"
#else
#include "3b2_rev2_csr.h"
#endif
#include "3b2_cpu.h"
DEBTAB sys_deb_tab[] = { DEBTAB sys_deb_tab[] = {
{ "INIT", INIT_MSG, "Init" }, { "INIT", INIT_MSG, "Init" },
{ "READ", READ_MSG, "Read activity" }, { "READ", READ_MSG, "Read activity" },

4
3B2/3b2_stddev.h
View file

@ -31,7 +31,7 @@
#ifndef _3B2_REV2_SYSDEV_H_ #ifndef _3B2_REV2_SYSDEV_H_
#define _3B2_REV2_SYSDEV_H_ #define _3B2_REV2_SYSDEV_H_
#include "sim_defs.h" #include "3b2_defs.h"
/* Timer definitions */ /* Timer definitions */
#define TMR_CLK 0 /* The clock responsible for IPL 15 interrupts */ #define TMR_CLK 0 /* The clock responsible for IPL 15 interrupts */
@ -130,4 +130,6 @@ uint32 flt_read(uint32 pa, size_t size);
void flt_write(uint32 pa, uint32 val, size_t size); void flt_write(uint32 pa, uint32 val, size_t size);
#endif #endif
extern int32 tmxr_poll;
#endif /* _3B2_REV2_SYSDEV_H_ */ #endif /* _3B2_REV2_SYSDEV_H_ */

5
3B2/3b2_sys.c
View file

@ -28,7 +28,10 @@
from the author. from the author.
*/ */
#include "3b2_defs.h" #include "3b2_sys.h"
#include "3b2_cpu.h"
#include "3b2_mem.h"
REG *sim_PC = &cpu_reg[NUM_PC]; REG *sim_PC = &cpu_reg[NUM_PC];

6
3B2/3b2_sys.h
View file

@ -31,7 +31,7 @@
#ifndef _3B2_REV2_SYS_H_ #ifndef _3B2_REV2_SYS_H_
#define _3B2_REV2_SYS_H_ #define _3B2_REV2_SYS_H_
#include "sim_defs.h" #include "3b2_defs.h"
void full_reset(); void full_reset();
t_stat sim_load(FILE *fileref, CONST char *cptr, CONST char *fnam, int flag); t_stat sim_load(FILE *fileref, CONST char *cptr, CONST char *fnam, int flag);
@ -39,4 +39,8 @@ t_stat parse_sym(CONST char *cptr, t_addr addr, UNIT *uptr, t_value *val,
int32 sw); int32 sw);
t_stat fprint_sym(FILE *of, t_addr addr, t_value *val, UNIT *uptr, int32 sw); t_stat fprint_sym(FILE *of, t_addr addr, t_value *val, UNIT *uptr, int32 sw);
extern char sim_name[];
extern REG *sim_PC;
extern int32 sim_emax;
#endif /* _3B2_REV2_SYS_H_ */ #endif /* _3B2_REV2_SYS_H_ */