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PDP8: Renamed switch register variable to SR

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As discussed in: #385
This commit is contained in:
Bob Supnik 2017-01-28 12:15:34 -08:00 • committed by Mark Pizzolato
parent 110ded6904
commit d14243c858
1 changed files with 5 additions and 4 deletions
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9
PDP8/pdp8_cpu.c
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@ -1,6 +1,6 @@
/* pdp8_cpu.c: PDP-8 CPU simulator /* pdp8_cpu.c: PDP-8 CPU simulator
Copyright (c) 1993-2016, Robert M Supnik Copyright (c) 1993-2017, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),
@ -25,6 +25,7 @@
cpu central processor cpu central processor
28-Jan-17 RMS Renamed switch register variable to SR, per request
18-Sep-16 RMS Added alternate dispatch table for non-contiguous devices 18-Sep-16 RMS Added alternate dispatch table for non-contiguous devices
17-Sep-13 RMS Fixed boot in wrong field problem (Dave Gesswein) 17-Sep-13 RMS Fixed boot in wrong field problem (Dave Gesswein)
28-Apr-07 RMS Removed clock initialization 28-Apr-07 RMS Removed clock initialization
@ -225,7 +226,7 @@ int32 gtf = 0; /* EAE gtf flag */
int32 SC = 0; /* EAE shift count */ int32 SC = 0; /* EAE shift count */
int32 UB = 0; /* User mode Buffer */ int32 UB = 0; /* User mode Buffer */
int32 UF = 0; /* User mode Flag */ int32 UF = 0; /* User mode Flag */
int32 OSR = 0; /* Switch Register */ int32 SR = 0; /* Switch Register */
int32 tsc_ir = 0; /* TSC8-75 IR */ int32 tsc_ir = 0; /* TSC8-75 IR */
int32 tsc_pc = 0; /* TSC8-75 PC */ int32 tsc_pc = 0; /* TSC8-75 PC */
int32 tsc_cdf = 0; /* TSC8-75 CDF flag */ int32 tsc_cdf = 0; /* TSC8-75 CDF flag */
@ -266,7 +267,7 @@ REG cpu_reg[] = {
{ ORDATAD (AC, saved_LAC, 12, "accumulator") }, { ORDATAD (AC, saved_LAC, 12, "accumulator") },
{ FLDATAD (L, saved_LAC, 12, "link") }, { FLDATAD (L, saved_LAC, 12, "link") },
{ ORDATAD (MQ, saved_MQ, 12, "multiplier-quotient") }, { ORDATAD (MQ, saved_MQ, 12, "multiplier-quotient") },
{ ORDATAD (SR, OSR, 12, "front panel switches") }, { ORDATAD (SR, SR, 12, "front panel switches") },
{ GRDATAD (IF, saved_PC, 8, 3, 12, "instruction field") }, { GRDATAD (IF, saved_PC, 8, 3, 12, "instruction field") },
{ GRDATAD (DF, saved_DF, 8, 3, 12, "data field") }, { GRDATAD (DF, saved_DF, 8, 3, 12, "data field") },
{ GRDATAD (IB, IB, 8, 3, 12, "instruction field buffter") }, { GRDATAD (IB, IB, 8, 3, 12, "instruction field buffter") },
@ -921,7 +922,7 @@ switch ((IR >> 7) & 037) { /* decode IR<0:4> */
} }
else { else {
if (IR & 04) /* OSR */ if (IR & 04) /* OSR */
LAC = LAC | OSR; LAC = LAC | SR;
if (IR & 02) /* HLT */ if (IR & 02) /* HLT */
reason = STOP_HALT; reason = STOP_HALT;
} }