PDP10: Added debug support to clock device (TIM)
This commit is contained in:
Mark Pizzolato
parent
1845fcd53b
commit
d4082f383e
1 changed files with 45 additions and 10 deletions
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@ -191,12 +191,31 @@ static MTAB tim_mod[] = {
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{ 0 }
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};
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/* Debug detail levels */
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#define DEB_RRD 0001 /* reg reads */
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#define DEB_RWR 0002 /* reg writes */
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#define DEB_TPS 0004 /* Ticks Per Second changes */
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#define DEB_INT 0010 /* interrupts */
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#define DEB_TRC 0020 /* trace */
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static DEBTAB tim_deb[] = {
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{ "RRD", DEB_RRD, "register reads" },
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{ "RWR", DEB_RWR, "register writes" },
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{ "TPS", DEB_TPS, "Ticks Per Second changes " },
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{ "INT", DEB_INT, "interrupts" },
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{ "TRACE", DEB_TRC, "trace" },
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{ NULL, 0 }
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};
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DEVICE tim_dev = {
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"TIM", &tim_unit, tim_reg, tim_mod,
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1, 0, 0, 0, 0, 0,
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NULL, NULL, &tim_reset,
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NULL, NULL, NULL,
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&tcu_dib, DEV_UBUS
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&tcu_dib, DEV_UBUS | DEV_DEBUG,
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0, tim_deb
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};
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/* Timer instructions */
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@ -250,6 +269,7 @@ tempbase[1] &= ~((d10) TIM_BASE_RAZ);
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*/
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Write (ea, tempbase[0], prv);
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Write (INCA(ea), tempbase[1], prv);
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sim_debug (DEB_RRD, &tim_dev, "rdtim() = %012" LL_FMT "o %012" LL_FMT "o\n", tempbase[0], tempbase[1]);
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return FALSE;
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}
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@ -257,12 +277,14 @@ t_bool wrtim (a10 ea, int32 prv)
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{
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tim_base[0] = Read (ea, prv);
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tim_base[1] = CLRS (Read (INCA (ea), prv) & ~((d10) TIM_HWRE_MASK));
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sim_debug (DEB_RWR, &tim_dev, "wrtim(%012" LL_FMT "o, %012" LL_FMT "o)\n", tim_base[0], tim_base[1]);
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return FALSE;
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}
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t_bool rdint (a10 ea, int32 prv)
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{
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Write (ea, tim_interval, prv);
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sim_debug (DEB_RRD, &tim_dev, "rdint() = %012" LL_FMT "o\n", tim_interval);
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return FALSE;
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}
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@ -275,11 +297,13 @@ return FALSE;
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t_bool wrint (a10 ea, int32 prv)
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{
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tim_interval = CLRS (Read (ea, prv));
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sim_debug (DEB_RWR, &tim_dev, "wrint(%012" LL_FMT "o)\n", tim_interval);
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return update_interval (tim_interval);
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}
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static t_bool update_interval (d10 new_interval)
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{
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int32 old_clk_tps = clk_tps;
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/*
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* The value provided is in hardware clicks. For a frequency of 4.1
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* MHz, that means that dividing by 4096 (shifting 12 to the right) we get
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@ -293,7 +317,9 @@ if (new_interval & TIM_HWRE_MASK) tim_new_period += 010000;
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/* clk_tps is the new number of clocks ticks per second */
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clk_tps = (int32) ceil(((double)TIM_HW_FREQ /(double)tim_new_period) - 0.5);
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if (clk_tps != old_clk_tps)
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sim_debug (DEB_TPS, &tim_dev, "update_interval() - clk_tps changed from %d to %d\n", old_clk_tps, clk_tps);
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/* tmxr is polled every tim_mult clks. Compute the divisor matching the target. */
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tim_mult = (clk_tps <= TIM_TMXR_FREQ) ? 1 : (clk_tps / TIM_TMXR_FREQ) ;
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@ -317,13 +343,15 @@ static t_stat tim_svc (UNIT *uptr)
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{
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if (cpu_unit.flags & UNIT_KLAD) /* diags? */
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tmr_poll = uptr->wait; /* fixed clock */
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else tmr_poll = sim_rtc_calb (clk_tps); /* else calibrate */
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else
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tmr_poll = sim_rtc_calb (clk_tps); /* else calibrate */
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sim_activate (uptr, tmr_poll); /* reactivate unit */
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tmxr_poll = tmr_poll * tim_mult; /* set mux poll */
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tim_incr_base (tim_base, tim_period); /* incr time base based on period of expired interval */
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tim_period = tim_new_period; /* If interval has changed, update period */
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apr_flg = apr_flg | APRF_TIM; /* request interrupt */
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sim_debug (DEB_INT, &tim_dev, "tim_svc(INT) tmr_poll=%d, tmxr_poll=%d, tim_period=%" LL_FMT "d\n", tmr_poll, tmxr_poll, tim_period);
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if (Q_ITS) { /* ITS? */
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if (pi_act == 0)
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quant = (quant + TIM_ITS_QUANT) & DMASK;
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@ -332,8 +360,10 @@ if (Q_ITS) { /* ITS? */
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pcst = AOB (pcst); /* add 1,,1 */
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}
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} /* end ITS */
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else if (t20_idlelock && PROB (100 - tim_t20_prob))
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t20_idlelock = 0;
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else {
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if (t20_idlelock && PROB (100 - tim_t20_prob))
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t20_idlelock = 0;
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}
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return SCPE_OK;
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}
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@ -350,6 +380,7 @@ return;
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static t_stat tim_reset (DEVICE *dptr)
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{
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sim_debug (DEB_TRC, &tim_dev, "tim_reset()\n");
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sim_register_clock_unit (&tim_unit); /* declare clock unit */
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tim_base[0] = tim_base[1] = 0; /* clear timebase (HW does) */
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@ -366,6 +397,7 @@ tim_base[0] = tim_base[1] = 0; /* clear timebase (HW do
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*/
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tim_interval = 0;
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clk_tps = 60;
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sim_debug (DEB_TPS, &tim_dev, "tim_reset() - clk_tps set to %d\n", clk_tps);
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update_interval(17*4096);
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apr_flg = apr_flg & ~APRF_TIM; /* clear interrupt */
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@ -411,6 +443,7 @@ static t_stat tcu_rd (int32 *data, int32 PA, int32 access)
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{
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time_t curtim;
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struct tm *tptr;
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t_stat st = SCPE_OK;
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curtim = time (NULL); /* get time */
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tptr = localtime (&curtim); /* decompose */
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@ -425,21 +458,23 @@ switch ((PA >> 1) & 03) { /* decode PA<3:1> */
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*data = (((tptr->tm_year) & 0177) << 9) |
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(((tptr->tm_mon + 1) & 017) << 5) |
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((tptr->tm_mday) & 037);
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return SCPE_OK;
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break;
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case 1: /* hour/minute */
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*data = (((tptr->tm_hour) & 037) << 8) |
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((tptr->tm_min) & 077);
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return SCPE_OK;
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break;
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case 2: /* second */
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*data = (tptr->tm_sec) & 077;
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return SCPE_OK;
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break;
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case 3: /* status */
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*data = CSR_DONE;
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return SCPE_OK;
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break;
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}
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return SCPE_NXM; /* can't get here */
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sim_debug (DEB_RRD, &tim_dev, "tcu_rd() = %o\n", *data);
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return st;
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}
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