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Intel-Systems: Cleanup compile error/warnings

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This commit is contained in:
Bill Beech 2019-10-18 16:12:49 -07:00
parent aff3346eae
commit e99d731b8a
30 changed files with 158 additions and 158 deletions
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6
Intel-Systems/common/i8080.c
View file

@ -169,9 +169,9 @@ uint32 IM = 0; /* Interrupt Mask Register */
uint8 xack = 0; /* XACK signal */
uint32 int_req = 0; /* Interrupt request */
uint8 INTA = 0; // interrupt acknowledge
int32 PCX; /* External view of PC */
int32 PCY; /* Internal view of PC */
int32 PC;
uint16 PCX; /* External view of PC */
uint16 PCY; /* Internal view of PC */
uint16 PC;
UNIT *uptr;
uint16 port; //port used in any IN/OUT
uint16 addr; //addr used for operand fetch

4
Intel-Systems/common/i8237.c
View file

@ -264,7 +264,7 @@ uint8 i8237_rFx(t_bool io, uint8 data);
/* external function prototypes */
extern uint16 reg_dev(uint8 (*routine)(t_bool, uint8), uint16);
extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8);
/* globals */
@ -429,7 +429,7 @@ t_stat i8237_svc(UNIT *uptr)
/* Reset routine */
t_stat i8237_reset(DEVICE *dptr, uint16 base)
t_stat i8237_reset(DEVICE *dptr)
{
if (i8237_devnum > I8237_NUM) {
sim_printf("i8237_reset: too many devices!\n");

2
Intel-Systems/common/i8253.c
View file

@ -145,7 +145,7 @@ t_stat i8253_reset (DEVICE *dptr)
{
uint8 devnum;
for (devnum=0; devnum<I8251_NUM; devnum++) {
for (devnum=0; devnum<I8253_NUM; devnum++) {
i8253_unit[devnum].u3 = 0; /* status */
i8253_unit[devnum].u4 = 0; /* mode instruction */
i8253_unit[devnum].u5 = 0; /* command instruction */

2
Intel-Systems/common/i8272.c
View file

@ -128,7 +128,7 @@ uint16 i8272_port[4]; //base port registered to each instance
/* external globals */
extern uint16 port; //port called in dev_table[port]
extern int32 PCX;
extern uint16 PCX;
/* internal function prototypes */

14
Intel-Systems/common/ieprom.c
View file

@ -56,7 +56,7 @@ extern uint8 i8255_C[4]; //port C byte I/O
/* SIMH EPROM Standard I/O Data Structures */
UNIT EPROM_unit[] = {
UNIT EPROM_unit = {
UDATA (NULL, UNIT_ATTABLE+UNIT_BINK+UNIT_ROABLE+UNIT_RO+UNIT_BUFABLE+UNIT_MUSTBUF, 0), 0
};
@ -73,7 +73,7 @@ DEBTAB EPROM_debug[] = {
DEVICE EPROM_dev = {
"EPROM", //name
EPROM_unit, //units
&EPROM_unit, //units
NULL, //registers
NULL, //modifiers
1, //numunits
@ -102,10 +102,10 @@ DEVICE EPROM_dev = {
t_stat EPROM_cfg(uint16 base, uint16 size)
{
EPROM_unit->capac = size; /* set EPROM size */
EPROM_unit->u3 = base & 0xFFFF; /* set EPROM base */
EPROM_unit.capac = size; /* set EPROM size */
EPROM_unit.u3 = base & 0xFFFF; /* set EPROM base */
sim_printf(" EPROM: 0%04XH bytes at base 0%04XH\n",
EPROM_unit->capac, EPROM_unit->u3);
EPROM_unit.capac, EPROM_unit.u3);
return SCPE_OK;
}
@ -135,9 +135,9 @@ uint8 EPROM_get_mbyte(uint16 addr)
{
uint8 val;
if ((addr >= EPROM_unit->u3) && ((uint32) addr <= (EPROM_unit->u3 + EPROM_unit->capac))) {
if ((addr >= EPROM_unit.u3) && ((uint32) addr <= (EPROM_unit.u3 + EPROM_unit.capac))) {
SET_XACK(1); /* good memory address */
val = *((uint8 *)EPROM_unit->filebuf + (addr - EPROM_unit->u3));
val = *((uint8 *)EPROM_unit.filebuf + (addr - EPROM_unit.u3));
val &= 0xFF;
return val;
} else {

2
Intel-Systems/common/ioc-cont.c
View file

@ -71,7 +71,7 @@
/* external globals */
extern int32 PCX;
extern uint16 PCX;
/* function prototypes */

30
Intel-Systems/common/ipb.c
View file

@ -69,19 +69,19 @@ int onetime = 0;
/* extern globals */
extern uint32 PCX; /* program counter */
extern uint16 PCX; /* program counter */
extern UNIT i8255_unit;
extern UNIT EPROM_unit;
extern UNIT RAM_unit;
extern UNIT ipc_cont_unit;
extern UNIT ioc_cont_unit;
extern DEVICE *i8080_dev;
extern DEVICE *i8251_dev;
extern DEVICE *i8253_dev;
extern DEVICE *i8255_dev;
extern DEVICE *i8259_dev;
extern DEVICE *ipc_cont_dev;
extern DEVICE *ioc_cont_dev;
extern DEVICE i8080_dev;
extern DEVICE i8251_dev;
extern DEVICE i8253_dev;
extern DEVICE i8255_dev;
extern DEVICE i8259_dev;
extern DEVICE ipc_cont_dev;
extern DEVICE ioc_cont_dev;
t_stat SBC_config(void)
{
@ -110,13 +110,13 @@ t_stat SBC_reset (DEVICE *dptr)
multibus_cfg();
onetime++;
}
i8080_reset(i8080_dev);
i8251_reset(i8251_dev);
i8253_reset(i8253_dev);
i8255_reset(i8255_dev);
i8259_reset(i8259_dev);
ipc_cont_reset(ipc_cont_dev);
ioc_cont_reset(ioc_cont_dev);
i8080_reset(&i8080_dev);
i8251_reset(&i8251_dev);
i8253_reset(&i8253_dev);
i8255_reset(&i8255_dev);
i8259_reset(&i8259_dev);
ipc_cont_reset(&ipc_cont_dev);
ioc_cont_reset(&ioc_cont_dev);
return SCPE_OK;
}

34
Intel-Systems/common/ipc-cont.c
View file

@ -45,12 +45,12 @@ extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
/* globals */
UNIT ipc_cont_unit[] = {
{ UDATA (0, 0, 0) }, /* ipc_cont*/
};
UNIT ipc_cont_unit =
{ UDATA (0, 0, 0) }; /* ipc_cont*/
REG ipc_cont_reg[] = {
{ HRDATA (CONTROL0, ipc_cont_unit[0].u3, 8) }, /* ipc_cont */
{ HRDATA (CONTROL0, ipc_cont_unit.u3, 8) }, /* ipc_cont */
{ NULL }
};
@ -69,7 +69,7 @@ DEBTAB ipc_cont_debug[] = {
DEVICE ipc_cont_dev = {
"IPC-CONT", //name
ipc_cont_unit, //units
&ipc_cont_unit, //units
ipc_cont_reg, //registers
NULL, //modifiers
1, //numunits
@ -106,7 +106,7 @@ t_stat ipc_cont_cfg(uint8 base, uint8 devnum)
t_stat ipc_cont_reset(DEVICE *dptr)
{
ipc_cont_unit[0].u3 = 0x00; /* ipc reset */
ipc_cont_unit.u3 = 0x00; /* ipc reset */
return SCPE_OK;
}
@ -119,40 +119,40 @@ t_stat ipc_cont_reset(DEVICE *dptr)
uint8 ipc_cont(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read status port */
return ipc_cont_unit[0].u3;
return ipc_cont_unit.u3;
} else { /* write control port */
//this simulates an 74LS259 register
//d0-d2 address the reg(in reverse order!), d3 is the data to be latched (inverted)
switch(data & 0x07) {
case 5: //interrupt enable 8085 INTR
if(data & 0x08) //bit low
ipc_cont_unit[0].u3 &= 0xBF;
ipc_cont_unit.u3 &= 0xBF;
else //bit high
ipc_cont_unit[0].u3 |= 0x20;
ipc_cont_unit.u3 |= 0x20;
break;
case 4: //*selboot ROM @ 0E800h
if(data & 0x08) //bit low
ipc_cont_unit[0].u3 &= 0xEF;
ipc_cont_unit.u3 &= 0xEF;
else //bit high
ipc_cont_unit[0].u3 |= 0x10;
ipc_cont_unit.u3 |= 0x10;
break;
case 2: //*startup ROM @ 00000h
if(data & 0x08) //bit low
ipc_cont_unit[0].u3 &= 0xFB;
ipc_cont_unit.u3 &= 0xFB;
else //bit high
ipc_cont_unit[0].u3 |= 0x04;
ipc_cont_unit.u3 |= 0x04;
break;
case 1: //override inhibit other multibus users
if(data & 0x08) //bit low
ipc_cont_unit[0].u3 &= 0xFD;
ipc_cont_unit.u3 &= 0xFD;
else //bit high
ipc_cont_unit[0].u3 |= 0x02;
ipc_cont_unit.u3 |= 0x02;
break;
case 0: //aux prom enable
if(data & 0x08) //bit low
ipc_cont_unit[0].u3 &= 0xFE;
ipc_cont_unit.u3 &= 0xFE;
else //bit high
ipc_cont_unit[0].u3 |= 0x01;
ipc_cont_unit.u3 |= 0x01;
break;
default:
break;

28
Intel-Systems/common/ipc.c
View file

@ -73,13 +73,13 @@ extern UNIT EPROM_unit;
extern UNIT RAM_unit;
extern UNIT ipc_cont_unit;
extern UNIT ioc_cont_unit;
extern DEVICE *i8080_dev;
extern DEVICE *i8251_dev;
extern DEVICE *i8253_dev;
extern DEVICE *i8255_dev;
extern DEVICE *i8259_dev;
extern DEVICE *ipc_cont_dev;
extern DEVICE *ioc_cont_dev;
extern DEVICE i8080_dev;
extern DEVICE i8251_dev;
extern DEVICE i8253_dev;
extern DEVICE i8255_dev;
extern DEVICE i8259_dev;
extern DEVICE ipc_cont_dev;
extern DEVICE ioc_cont_dev;
/* globals */
@ -112,13 +112,13 @@ t_stat SBC_reset (DEVICE *dptr)
multibus_cfg();
onetime++;
}
i8080_reset(i8080_dev);
i8251_reset(i8251_dev);
i8253_reset(i8253_dev);
i8255_reset(i8255_dev);
i8259_reset(i8259_dev);
ipc_cont_reset(ipc_cont_dev);
ioc_cont_reset(ioc_cont_dev);
i8080_reset(&i8080_dev);
i8251_reset(&i8251_dev);
i8253_reset(&i8253_dev);
i8255_reset(&i8255_dev);
i8259_reset(&i8259_dev);
ipc_cont_reset(&ipc_cont_dev);
ioc_cont_reset(&ioc_cont_dev);
return SCPE_OK;
}

2
Intel-Systems/common/iram8.c
View file

@ -95,7 +95,7 @@ t_stat RAM_cfg(uint16 base, uint16 size)
{
RAM_unit.capac = size & 0xFFFF; /* set RAM size */
RAM_unit.u3 = base & 0xFFFF; /* set RAM base */
RAM_unit.filebuf = (uint8 *)malloc(size * sizeof(uint8));
RAM_unit.filebuf = (uint8 *)calloc(size, size * sizeof(uint8));
if (RAM_unit.filebuf == NULL) {
sim_printf (" RAM: Malloc error\n");
return SCPE_MEM;

2
Intel-Systems/common/isbc064.c
View file

@ -56,7 +56,7 @@ void isbc064_put_mbyte(uint16 addr, uint8 val);
/* external globals */
extern uint32 PCX; /* program counter */
extern uint16 PCX; /* program counter */
extern uint8 xack;
/* isbc064 Standard SIMH Device Data Structures */

2
Intel-Systems/common/isbc201.c
View file

@ -206,7 +206,7 @@
/* external globals */
extern int32 PCX;
extern uint16 PCX;
/* external function prototypes */

2
Intel-Systems/common/isbc202.c
View file

@ -184,7 +184,7 @@
/* external globals */
extern int32 PCX;
extern uint16 PCX;
/* external function prototypes */

2
Intel-Systems/common/isbc206.c
View file

@ -174,7 +174,7 @@
/* external globals */
extern int32 PCX;
extern uint16 PCX;
/* external function prototypes */

2
Intel-Systems/common/isbc208.c
View file

@ -510,7 +510,7 @@ extern int32 multibus_get_mbyte(uint16 addr);
/* external globals */
extern int32 PCX;
extern uint16 PCX;
/* 8237 physical register definitions */
uint16 i8237_r0; // 8237 ch 0 address register

18
Intel-Systems/common/isbc464.c
View file

@ -53,7 +53,7 @@ extern uint8 xack; /* XACK signal */
/* isbc464 Standard I/O Data Structures */
UNIT isbc464_unit[] = {
UNIT isbc464_unit = {
UDATA (NULL, UNIT_ATTABLE+UNIT_BINK+UNIT_ROABLE+UNIT_RO+UNIT_BUFABLE+UNIT_MUSTBUF, 0), 0
};
@ -70,7 +70,7 @@ DEBTAB isbc464_debug[] = {
DEVICE isbc464_dev = {
"SBC464", //name
isbc464_unit, //units
&isbc464_unit, //units
NULL, //registers
NULL, //modifiers
1, //numunits
@ -101,8 +101,8 @@ t_stat isbc464_cfg(uint16 base, uint16 size)
{
sim_printf(" sbc464: 0%04XH bytes at base 0%04XH\n",
size, base);
isbc464_unit->capac = size; //set size
isbc464_unit->u3 = base; //and base
isbc464_unit.capac = size; //set size
isbc464_unit.u3 = base; //and base
return SCPE_OK;
}
@ -135,9 +135,9 @@ uint8 isbc464_get_mbyte(uint16 addr)
uint8 *fbuf;
if ((isbc464_dev.flags & DEV_DIS) == 0) {
org = isbc464_unit->u3;
len = isbc464_unit->capac;
fbuf = (uint8 *) isbc464_unit->filebuf;
org = isbc464_unit.u3;
len = isbc464_unit.capac;
fbuf = (uint8 *) isbc464_unit.filebuf;
if ((addr >= org) && (addr < (org + len))) {
SET_XACK(1); /* good memory address */
val = *(fbuf + (addr - org));
@ -158,8 +158,8 @@ void isbc464_put_mbyte(uint16 addr, uint8 val)
uint32 org, len;
if ((isbc464_dev.flags & DEV_DIS) == 0) {
org = isbc464_unit->u3;
len = isbc464_unit->capac;
org = isbc464_unit.u3;
len = isbc464_unit.capac;
if ((addr >= org) && (addr < (org + len))) {
// SET_XACK(1); /* good memory address */
sim_printf ("isbc464_put_mbyte: Read-only Memory\n");

2
Intel-Systems/common/multibus.c
View file

@ -77,7 +77,7 @@ int32 mbirq = 0; /* set no multibus interrupts */
extern uint8 xack; /* XACK signal */
extern int32 int_req; /* i8080 INT signal */
extern int32 PCX;
extern uint16 PCX;
extern DEVICE isbc064_dev;
extern DEVICE isbc464_dev;
extern DEVICE isbc201_dev;

2
Intel-Systems/common/zx200a.c
View file

@ -198,7 +198,7 @@ extern void multibus_put_mbyte(uint16 addr, uint8 val);
/* external globals */
extern int32 PCX;
extern uint16 PCX;
/* internal function prototypes */

14
Intel-Systems/imds-220/system_defs.h
View file

@ -60,19 +60,19 @@
/* set the base and size for the EPROM on the MDS 220 */
#define ROM_BASE 0x0000
#define ROM_SIZE 0x1000
#define ROM_SIZE 0x0FFF
#define ROM_DISABLE 1
#define EPROM_NUM 1
/* set the base and size for the RAM on the MDS 220 */
#define RAM_BASE 0x0000
#define RAM_SIZE 0x8000
#define RAM_SIZE 0x7FFF
//board definitions for the multibus
/* set the base I/O address for the iSBC 201 */
#define SBC201_BASE 0x78
#define SBC201_BASE 0x88
#define SBC201_INT INT_2
#define SBC201_NUM 0
#define SBC201_NUM 1
/* set the base I/O address for the iSBC 202 */
#define SBC202_BASE 0x78
@ -92,16 +92,16 @@
/* set the base for the zx-200a disk controller */
#define ZX200A_BASE 0x78
#define ZX200A_INT INT_2
#define ZX200A_NUM 1
#define ZX200A_NUM 0
/* set the base and size for the iSBC 064 RAM*/
#define SBC064_BASE 0x8000
#define SBC064_SIZE 0x8000
#define SBC064_SIZE 0x7FFF
#define SBC064_NUM 1
/* set the base and size for the iSBC 464 ROM */
#define SBC464_BASE 0xA800
#define SBC464_SIZE 0x4800
#define SBC464_SIZE 0x47FF
#define SBC464_NUM 0
/* set INTR for CPU */

4
Intel-Systems/imds-800/front_panel.c
View file

@ -43,7 +43,7 @@ extern t_stat EPROM_cfg(uint16 base, uint16 size);
/* external globals */
extern DEVICE *EPROM_dev;
extern DEVICE EPROM_dev;
t_stat fp_cfg(void)
{
@ -57,7 +57,7 @@ t_stat fp_cfg(void)
t_stat fp_reset (void)
{
EPROM_reset(EPROM_dev);
EPROM_reset(&EPROM_dev);
return SCPE_OK;
}

8
Intel-Systems/imds-800/monitor.c
View file

@ -48,8 +48,8 @@ extern uint8 i3214_monitor_do_boot(t_bool io, uint8 data, uint8 devnum);
// external globals
extern uint32 PCX; /* program counter */
extern DEVICE *i8251_dev;
extern DEVICE *EPROM1_dev;
extern DEVICE i8251_dev;
extern DEVICE EPROM1_dev;
extern uint8 monitor_boot;
// globals
@ -69,8 +69,8 @@ t_stat monitor_cfg(void)
t_stat monitor_reset (void)
{
monitor_boot = 0x00;
i8251_reset(i8251_dev);
EPROM1_reset(EPROM1_dev);
i8251_reset(&i8251_dev);
EPROM1_reset(&EPROM1_dev);
return SCPE_OK;
}

2
Intel-Systems/imds-810/cpu.c
View file

@ -62,7 +62,7 @@ extern t_stat multibus_cfg(void);
// external globals
extern uint32 PCX; /* program counter */
extern uint16 PCX; /* program counter */
extern DEVICE i3214_dev;
extern DEVICE i8080_dev;
extern uint8 EPROM_enable;

2
Intel-Systems/imds-810/front_panel.c
View file

@ -45,7 +45,7 @@ extern t_stat EPROM_cfg(uint16 base, uint16 size);
// external globals
extern UNIT EPROM_unit; //1702 EPROM
extern uint32 PCX; /* program counter */
extern uint16 PCX; /* program counter */
// fp configuration

10
Intel-Systems/imds-810/monitor.c
View file

@ -49,10 +49,10 @@ extern t_stat i8251_cfg(uint8 base, uint8 size);
// external globals
extern uint32 PCX; /* program counter */
extern uint16 PCX; /* program counter */
extern UNIT EPROM1_unit; //8316 PROM
extern DEVICE *i8251_dev;
extern DEVICE *EPROM1_dev;
extern DEVICE i8251_dev;
extern DEVICE EPROM1_dev;
// globals
@ -75,8 +75,8 @@ t_stat monitor_cfg(void)
t_stat monitor_reset (void)
{
monitor_boot = 0x00;
i8251_reset(i8251_dev);
EPROM1_reset(EPROM1_dev);
i8251_reset(&i8251_dev);
EPROM1_reset(&EPROM1_dev);
return SCPE_OK;
}

16
Intel-Systems/isys8010/isbc8010.c
View file

@ -48,12 +48,12 @@ void put_mword(uint16 addr, uint16 val);
/* external globals */
extern uint8 i8255_C[4]; //port C byte I/O
extern DEVICE *i8080_dev;
extern DEVICE *i8251_dev;
extern DEVICE *i8255_dev;
extern DEVICE *EPROM_dev;
extern DEVICE i8080_dev;
extern DEVICE i8251_dev;
extern DEVICE i8255_dev;
extern DEVICE EPROM_dev;
extern UNIT EPROM_unit;
extern DEVICE *RAM_dev;
extern DEVICE RAM_dev;
extern UNIT RAM_unit;
/* external function prototypes */
@ -99,9 +99,9 @@ t_stat SBC_reset (DEVICE *dptr)
multibus_cfg();
onetime++;
}
i8080_reset(i8080_dev);
i8251_reset(i8251_dev);
i8255_reset(i8255_dev);
i8080_reset(&i8080_dev);
i8251_reset(&i8251_dev);
i8255_reset(&i8255_dev);
return SCPE_OK;
}

2
Intel-Systems/isys8010/system_defs.h
View file

@ -76,7 +76,7 @@
/* set the base I/O address for the iSBC 208 */
#define SBC208_BASE 0x40
#define SBC208_INT INT_2
#define SBC208_NUM 1
#define SBC208_NUM 0
/* set the base for the zx-200a disk controller */
#define ZX200A_BASE 0x78

24
Intel-Systems/isys8020/isbc8020.c
View file

@ -51,27 +51,27 @@ extern uint8 i8255_C[4]; //port C byte I/O
extern uint8 multibus_get_mbyte(uint16 addr);
extern void multibus_put_mbyte(uint16 addr, uint8 val);
extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */
extern DEVICE *i8080_dev;
extern DEVICE i8080_dev;
extern t_stat i8251_reset (DEVICE *dptr);
extern uint8 i8251s(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8251d(t_bool io, uint8 data, uint8 devnum);
extern DEVICE *i8251_dev;
extern DEVICE i8251_dev;
extern t_stat i8253_reset (DEVICE *dptr);
extern uint8 i8253t0(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8253t1(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8253t2(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8253c(t_bool io, uint8 data, uint8 devnum);
extern DEVICE *i8253_dev;
extern DEVICE i8253_dev;
extern t_stat i8255_reset (DEVICE *dptr);
extern uint8 i8255a(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8255b(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8255c(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8255s(t_bool io, uint8 data, uint8 devnum);
extern DEVICE *i8255_dev;
extern DEVICE i8255_dev;
extern t_stat i8259_reset (DEVICE *dptr);
extern uint8 i8259a(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8259b(t_bool io, uint8 data, uint8 devnum);
extern DEVICE *i8259_dev;
extern DEVICE i8259_dev;
extern uint8 EPROM_get_mbyte(uint16 addr);
extern UNIT EPROM_unit;
extern t_stat EPROM_reset (DEVICE *dptr);
@ -86,7 +86,7 @@ extern t_stat i8259_cfg(uint8 base, uint8 devnum);
extern t_stat RAM_cfg(uint16 base, uint16 size);
extern t_stat EPROM_cfg(uint16 base, uint16 size);
extern t_stat multibus_cfg();
extern uint16 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
// globals
@ -115,12 +115,12 @@ t_stat SBC_reset (DEVICE *dptr)
multibus_cfg();
onetime++;
}
i8080_reset(i8080_dev);
i8251_reset(i8251_dev);
i8253_reset(i8253_dev);
i8255_reset(i8255_dev);
i8255_reset(i8255_dev);
i8259_reset(i8259_dev);
i8080_reset(&i8080_dev);
i8251_reset(&i8251_dev);
i8253_reset(&i8253_dev);
i8255_reset(&i8255_dev);
i8255_reset(&i8255_dev);
i8259_reset(&i8259_dev);
return SCPE_OK;
}

24
Intel-Systems/isys8024/isbc8024.c
View file

@ -47,34 +47,34 @@ t_stat SBC_reset (DEVICE *dptr);
/* external globals */
extern uint8 i8255_C[4]; //port C byte I/O
extern int32 PCX; /* External view of PC */
extern uint16 PCX; /* External view of PC */
/* external function prototypes */
extern uint8 multibus_get_mbyte(uint16 addr);
extern void multibus_put_mbyte(uint16 addr, uint8 val);
extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */
extern DEVICE *i8080_dev;
extern DEVICE i8080_dev;
extern t_stat i8251_reset (DEVICE *dptr);
extern uint8 i8251s(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8251d(t_bool io, uint8 data, uint8 devnum);
extern DEVICE *i8251_dev;
extern DEVICE i8251_dev;
extern t_stat i8253_reset (DEVICE *dptr);
extern uint8 i8253t0(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8253t1(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8253t2(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8253c(t_bool io, uint8 data, uint8 devnum);
extern DEVICE *i8253_dev;
extern DEVICE i8253_dev;
extern t_stat i8255_reset (DEVICE *dptr);
extern uint8 i8255a(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8255b(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8255c(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8255s(t_bool io, uint8 data, uint8 devnum);
extern DEVICE *i8255_dev;
extern DEVICE i8255_dev;
extern t_stat i8259_reset (DEVICE *dptr);
extern uint8 i8259a(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8259b(t_bool io, uint8 data, uint8 devnum);
extern DEVICE *i8259_dev;
extern DEVICE i8259_dev;
extern uint8 EPROM_get_mbyte(uint16 addr);
extern UNIT EPROM_unit;
extern t_stat EPROM_reset (DEVICE *dptr, uint16 base, uint16 size);
@ -116,12 +116,12 @@ t_stat SBC_reset (DEVICE *dptr)
multibus_cfg();
onetime++;
}
i8080_reset(i8080_dev);
i8251_reset(i8251_dev);
i8253_reset(i8253_dev);
i8255_reset(i8255_dev);
i8255_reset(i8255_dev);
i8259_reset(i8259_dev);
i8080_reset(&i8080_dev);
i8251_reset(&i8251_dev);
i8253_reset(&i8253_dev);
i8255_reset(&i8255_dev);
i8255_reset(&i8255_dev);
i8259_reset(&i8259_dev);
return SCPE_OK;
}

22
Intel-Systems/isys8030/isbc8030.c
View file

@ -47,22 +47,22 @@ t_stat SBC_reset (DEVICE *dptr);
/* external globals */
extern uint8 i8255_C[4]; //port C byte I/O
extern int32 PCX;
extern uint16 PCX;
/* external function prototypes */
extern uint8 multibus_get_mbyte(uint16 addr);
extern void multibus_put_mbyte(uint16 addr, uint8 val);
extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */
extern DEVICE *i8080_dev;
extern DEVICE i8080_dev;
extern t_stat i8251_reset (DEVICE *dptr);
extern DEVICE *i8251_dev;
extern DEVICE i8251_dev;
extern t_stat i8253_reset (DEVICE *dptr);
extern DEVICE *i8253_dev;
extern DEVICE i8253_dev;
extern t_stat i8255_reset (DEVICE *dptr);
extern DEVICE *i8255_dev;
extern DEVICE i8255_dev;
extern t_stat i8259_reset (DEVICE *dptr);
extern DEVICE *i8259_dev;
extern DEVICE i8259_dev;
extern uint8 EPROM_get_mbyte(uint16 addr);
extern UNIT EPROM_unit;
extern t_stat EPROM_reset (DEVICE *dptr, uint16 base, uint16 size);
@ -103,11 +103,11 @@ t_stat SBC_reset (DEVICE *dptr)
multibus_cfg();
onetime++;
}
i8080_reset(i8080_dev);
i8251_reset(i8251_dev);
i8253_reset(i8253_dev);
i8255_reset(i8255_dev);
i8259_reset(i8259_dev);
i8080_reset(&i8080_dev);
i8251_reset(&i8251_dev);
i8253_reset(&i8253_dev);
i8255_reset(&i8255_dev);
i8259_reset(&i8259_dev);
return SCPE_OK;
}