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Intel-MDS: Update to the latest and fix inconsistent REGister declarations

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Bill Beech 2022-08-03 13:15:03 -07:00 • committed by Mark Pizzolato
parent 5d12b9da4f
commit f03e370c6f
27 changed files with 6081 additions and 6671 deletions
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2
Intel-Systems/Intel-MDS/imds_sys.c
View file

@ -1,4 +1,4 @@
/* mds210_sys.c: multibus system interface
/* imds_sys.c: multibus system interface
Copyright (c) 2017, William A. Beech

13
Intel-Systems/Intel-MDS/system_defs.h
View file

@ -87,18 +87,18 @@
#define SBC206_NUM 0
/* set the base I/O address for the iSBC 208 */
#define SBC208_BASE 0x40
#define SBC208_INT INT_1
//#define SBC208_BASE 0x40
//#define SBC208_INT INT_1
#define SBC208_NUM 0
/* set the base for the zx-200a disk controller */
#define ZX200A_BASE 0x78
#define ZX200A_INT INT_1
//#define ZX200A_BASE 0x78
//#define ZX200A_INT INT_1
#define ZX200A_NUM 0
/* set the base and size for the iSBC 464 ROM */
#define SBC464_BASE 0xA800
#define SBC464_SIZE 0x47FF
//#define SBC464_BASE 0xA800
//#define SBC464_SIZE 0x47FF
#define SBC464_NUM 0
/* set the base and size for the iSBC 064 RAM */
@ -132,6 +132,7 @@
#define MAXMEMSIZE 0x0FFFF /* 8080 max memory size */
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
#define ADDRMASK (MAXMEMSIZE) /* 8080 address mask */
#define BYTEMASK 0xff //byte mask
#define MEM_ADDR_OK(x) (((uint16) (x)) <= MEMSIZE)
/* debug definitions */

49
Intel-Systems/common/i3214.c
View file

@ -39,9 +39,9 @@
*/
#include "system_defs.h"
#define IPC 0
#define i3214_NAME "Intel i3214 Perpherial Interrupt Contrlooer Chip"
#define UNIT_V_BOOT (UNIT_V_UF+1) /* BOOT/RUN switch */
#define UNIT_BOOT (1 << UNIT_V_BOOT)
#define i3214_NAME "Intel i3214 Perpherial Interrupt Controller Chip"
/* external globals */
@ -62,8 +62,8 @@ static const char* i3214_desc(DEVICE *dptr) {
return i3214_NAME;
}
int i3214_baseport = -1; //base port
uint8 i3214_intnum = 0; //interrupt number
uint8 i3214_verb = 0; //verbose flag
uint8 i3214_intnum = 0; //interrupt number
uint8 i3214_verb = 0; //verbose flag
/* function prototypes */
@ -98,14 +98,14 @@ DEBTAB i3214_debug[] = {
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "XACK", DEBUG_xack },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ NULL }
};
MTAB i3214_mod[] = {
{ UNIT_BOOT, 0, "BOOT", "BOOT", NULL },
{ UNIT_BOOT, UNIT_BOOT, "RUN", "RUN", NULL },
{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, i3214_show_param, NULL,
"show configured parametes for i3214" },
"show configured parameters for i3214" },
{ 0 }
};
@ -144,7 +144,7 @@ DEVICE i3214_dev = {
t_stat i3214_cfg(uint16 base, uint16 devnum, uint8 dummy)
{
i3214_baseport = base & 0xff;
i3214_baseport = base & BYTEMASK;
sim_printf(" i3214: at base port 0%02XH\n",
i3214_baseport);
reg_dev(i3214_do_mask, i3214_baseport, 0, 0);
@ -213,18 +213,18 @@ t_stat i3214_reset_dev (uint8 devnum)
uint8 i3214_do_mask(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) /* read status port */
if (io == 0) //read port
return i3214_mask;
else
else //write port
i3214_mask = data;
return 0;
}
uint8 i3214_do_status(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0)
if (io == 0) //read port
return 0;
else {
else { //write port
i3214_cnt--;
}
return 0;
@ -232,18 +232,31 @@ uint8 i3214_do_status(t_bool io, uint8 data, uint8 devnum)
uint8 i3214_cpu_bus_override(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) /* read status port */
if (io == 0) //read port
return 0;
else
else //write port
BUS_OVERRIDE = data & 0x01;
return 0;
}
uint8 i3214_monitor_do_boot(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) /* read status port */
return monitor_boot;
else
UNIT *uptr;
static uint8 onetime = 1;
uptr = i3214_unit;
if (io == 0) //read port
if (uptr->flags & UNIT_BOOT) { //toggle response
monitor_boot = 0;
printf(" Boot Switch set to BOOT\n");
} else {
monitor_boot = 0x02;
if (onetime) {
printf(" Boot Switch set to RUN\n");
onetime = 0;
}
}
else //write port
monitor_boot = data;
return 0;
}

315
Intel-Systems/common/i8080.c
View file

@ -113,10 +113,10 @@
#define UNIT_V_OPSTOP (UNIT_V_UF) /* Stop on Invalid OP? */
#define UNIT_OPSTOP (1 << UNIT_V_OPSTOP)
#define UNIT_V_8085 (UNIT_V_UF+1) /* 8080/8085 switch */
#define UNIT_V_MSTOP (UNIT_V_UF+1) /* Stop on Invalid memory? */
#define UNIT_MSTOP (1 << UNIT_V_MSTOP)
#define UNIT_V_8085 (UNIT_V_UF+2) /* 8080/8085 switch */
#define UNIT_8085 (1 << UNIT_V_8085)
#define UNIT_V_TRACE (UNIT_V_UF+2) /* Trace switch */
#define UNIT_TRACE (1 << UNIT_V_TRACE)
#define UNIT_V_XACK (UNIT_V_UF+3) /* XACK switch */
#define UNIT_XACK (1 << UNIT_V_XACK)
@ -159,6 +159,24 @@
#define i8080_NAME "Intel i8080/85 Processor Chip"
#define HIST_MIN 64
#define HIST_MAX (1u << 18)
#define HIST_ILNT 3 /* max inst length */
typedef struct {
uint16 pc;
uint16 sp;
uint8 psw;
uint8 a;
uint8 b;
uint8 c;
uint8 d;
uint8 e;
uint8 h;
uint8 l;
t_value inst[HIST_ILNT];
} InstHistory;
/* storage for the rest of the registers */
uint32 PSW = 0; /* program status word */
uint32 A = 0; /* accumulator */
@ -179,6 +197,11 @@ uint16 port; //port used in any IN/OUT
uint16 addr; //addr used for operand fetch
uint32 IR;
uint16 devnum = 0;
uint8 cpu_onetime = 0;
int32 hst_p = 0; /* history pointer */
int32 hst_lnt = 0; /* history length */
InstHistory *hst = NULL; /* instruction history */
static const char* i8080_desc(DEVICE *dptr) {
return i8080_NAME;
@ -203,6 +226,8 @@ void putpush(int32 reg, int32 data);
void putpair(int32 reg, int32 val);
void parity(int32 reg);
int32 cond(int32 con);
t_stat cpu_set_hist (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
t_stat i8080_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
t_stat i8080_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
t_stat i8080_reset (DEVICE *dptr);
@ -256,14 +281,16 @@ REG i8080_reg[] = {
};
MTAB i8080_mod[] = {
{ UNIT_OPSTOP, UNIT_OPSTOP, "ITRAP", "ITRAP", NULL },
{ UNIT_OPSTOP, 0, "NOITRAP", "NOITRAP", NULL },
{ UNIT_MSTOP, UNIT_MSTOP, "MTRAP", "MTRAP", NULL },
{ UNIT_MSTOP, 0, "NOMTRAP", "NOMTRAP", NULL },
{ UNIT_8085, 0, "8080", "8080", NULL },
{ UNIT_8085, UNIT_8085, "8085", "8085", NULL },
{ UNIT_OPSTOP, 0, "ITRAP", "ITRAP", NULL },
{ UNIT_OPSTOP, UNIT_OPSTOP, "NOITRAP", "NOITRAP", NULL },
{ UNIT_TRACE, 0, "NOTRACE", "NOTRACE", NULL },
{ UNIT_TRACE, UNIT_TRACE, "TRACE", "TRACE", NULL },
{ UNIT_XACK, 0, "NOXACK", "NOXACK", NULL },
{ UNIT_XACK, UNIT_XACK, "XACK", "XACK", NULL },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP|MTAB_NC, 0, "HISTORY", "HISTORY=n",
&cpu_set_hist, &cpu_show_hist, NULL, "Enable/Display instruction history" },
{ 0 }
};
@ -272,15 +299,12 @@ DEBTAB i8080_debug[] = {
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ "REG", DEBUG_reg },
{ "ASM", DEBUG_asm },
{ "XACK", DEBUG_xack },
{ NULL }
};
DEVICE i8080_dev = {
"I8080", //name
"CPU", //name
&i8080_unit, //units
i8080_reg, //registers
i8080_mod, //modifiers
@ -292,7 +316,7 @@ DEVICE i8080_dev = {
8, //dwidth
&i8080_ex, //examine
&i8080_dep, //deposit
NULL, //reset
&i8080_reset, //reset
NULL, //boot
NULL, //attach
NULL, //detach
@ -405,15 +429,17 @@ void set_cpuint(int32 int_num)
int32 sim_instr(void)
{
extern int32 sim_interval;
uint32 OP, DAR, reason, adr, i8080_onetime = 0;
uint32 OP, DAR, reason, adr;
int i;
InstHistory *hst_ent = NULL;
PC = saved_PC & WORD_R; /* load local PC */
reason = 0;
uptr = i8080_dev.units;
if (i8080_onetime++ == 0) {
if (uptr->flags & UNIT_8085)
if (cpu_onetime++ == 0) {
if ((uptr->flags & UNIT_8085))
sim_printf(" CPU = 8085\n");
else
sim_printf(" CPU = 8080\n");
@ -462,7 +488,7 @@ int32 sim_instr(void)
if (IM & IE) { /* enabled? */
INTA = 1;
push_word(PC); /* do an RST 2 */
PC = 0x0010;
PC = 0x0038;
int_req = 0;
// sim_printf("8080 Interrupt\n");
}
@ -471,13 +497,28 @@ int32 sim_instr(void)
if (sim_brk_summ &&
sim_brk_test (PC, SWMASK ('E'))) { /* breakpoint? */
// dumpregs();
reason = STOP_IBKPT; /* stop simulation */
break;
}
if (uptr->flags & UNIT_TRACE) {
dumpregs();
// sim_printf("\n");
if (hst_lnt) { /* record history? */
hst_ent = &hst[hst_p];
hst_ent->pc = PC;
hst_ent->sp = SP;
hst_ent->psw = PSW;
hst_ent->a = A;
hst_ent->b = (BC >> 8) & 0xFF;
hst_ent->c = (BC & 0xFF);
hst_ent->d = (DE >> 8) & 0xFF;
hst_ent->e = (DE & 0xFF);
hst_ent->h = (HL >> 8) & 0xFF;
hst_ent->l = (HL & 0xFF);
for (i = 0; i < HIST_ILNT; i++)
hst_ent->inst[i] = (t_value)get_mbyte (PC + i);
hst_p = (hst_p + 1);
if (hst_p >= hst_lnt)
hst_p = 0;
}
sim_interval--; /* countdown clock */
@ -897,13 +938,13 @@ int32 sim_instr(void)
case 0xDB: /* IN */
SET_XACK(1); /* good I/O address */
port = fetch_byte(1);
A = dev_table[port].routine(0, 0, dev_table[port].devnum & 0xff);
A = dev_table[port].routine(0, 0, dev_table[port].devnum & BYTEMASK);
break;
case 0xD3: /* OUT */
SET_XACK(1); /* good I/O address */
port = fetch_byte(1);
dev_table[port].routine(1, A, dev_table[port].devnum & 0xff);
dev_table[port].routine(1, A, dev_table[port].devnum & BYTEMASK);
break;
default: /* undefined opcode */
@ -955,7 +996,7 @@ int32 fetch_byte(int32 flag)
val = get_mbyte(PC) & 0xFF; /* fetch byte */
PC = (PC + 1) & ADDRMASK; /* increment PC */
addr = val & 0xff;
addr = val & BYTEMASK;
return val;
}
@ -1240,7 +1281,7 @@ void putpair(int32 reg, int32 val)
/* Reset routine */
t_stat i8080_reset (DEVICE *dptr)
t_stat i8080_reset(DEVICE *dptr)
{
PSW = PSW_ALWAYS_ON;
CLR_FLAG(CF);
@ -1253,54 +1294,106 @@ t_stat i8080_reset (DEVICE *dptr)
return SCPE_OK;
}
/* Memory examine */
t_stat i8080_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw)
{
if (addr >= MEMSIZE)
return SCPE_NXM;
if (vptr != NULL)
*vptr = get_mbyte(addr);
return SCPE_OK;
}
/* Memory deposit */
t_stat i8080_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw)
{
if (addr >= MEMSIZE)
return SCPE_NXM;
put_mbyte(addr, val);
return SCPE_OK;
}
/* This is the binary loader. The input file is considered to be
a string of literal bytes with no special format. The load
starts at the current value of the PC.
/* This is the dumper/loader. This command uses the -h to signify a
hex dump/load vice a binary one. If no address is given to load, it
takes the address from the hex record or the current PC for binary.
*/
int32 sim_load (FILE *fileref, CONST char *cptr, CONST char *fnam, int flag)
{
int32 i, addr = 0, cnt = 0;
#define HLEN 16
if ((*cptr != 0)) return SCPE_ARG;
if (flag == 0) { //load
// addr = saved_PC;
while ((i = getc (fileref)) != EOF) {
put_mbyte(addr, i);
addr++;
cnt++;
} /* end while */
sim_printf ("%d Bytes loaded.\n", cnt);
int32 sim_load(FILE *fileref, CONST char *cptr, CONST char *fnam, int flag)
{
int32 i, addr = 0, addr0 = 0, cnt = 0, cnt0 = 0, start = 0x10000;
int32 addr1 = 0, end = 0, byte, chk, rtype, flag0 = 1;
char buf[128], data[128], *p;
printf("sim_load cptr=%s fnam=%s flag=%d\n", cptr, fnam, flag);
cnt = sscanf(cptr, " %04X %04X", &start, &end);
addr=start;
printf("cnt=%d start=%05X end=%05X\n", cnt, start, end);
if (flag == 0) { //load
if (sim_switches & SWMASK ('H')) { //hex
if (cnt > 1) //2 arguments - error
return SCPE_ARG;
cnt = 0;
while (fgets(buf, sizeof(buf)-1, fileref)) {
sscanf(buf, " :%02x%04x%02x%s", &cnt, &addr, &rtype, data);
if (rtype == 0) {
chk = 0;
chk -= HLEN;
chk -= addr & BYTEMASK;
chk -= addr >> 8;
p = (char *) data;
for (i=0; i<=cnt; i++) {
sscanf (p, "%2x", &byte);
p += 2;
put_mbyte(addr + i, byte);
chk -= byte; chk &= BYTEMASK;
cnt++;
}
sscanf (p, "%2x", &byte);
if (chk == 0)
printf("+");
else
printf("-");
} else
return SCPE_ARG;
}
} else { //binary
cnt = 0;
addr1 = addr;
while ((i = getc (fileref)) != EOF) {
put_mbyte(addr, i);
addr++; cnt++;
}
}
printf ("%d Bytes loaded at %04X\n", cnt, addr1);
return (SCPE_OK);
} else { //dump
// addr = saved_PC;
while (addr <= 0xffff) {
i = get_mbyte(addr);
putc(i, fileref);
addr++;
cnt++;
if (cnt != 2) //must be 2 arguments
return SCPE_ARG;
cnt = 0;
addr0 = addr;
if (sim_switches & SWMASK ('H')) { //hex
while((addr + HLEN) < end) { //full records
fprintf(fileref,":%02X%04X00", HLEN, addr);
chk = 0;
chk -= HLEN;
chk -= addr & BYTEMASK;
chk -= addr >> 8;
for (i=0; i<HLEN; i++) {
byte = get_mbyte(addr + i);
fprintf(fileref, "%02X", byte & BYTEMASK);
chk -= byte; chk &= BYTEMASK;
cnt++;
}
fprintf(fileref,"%02X\n", chk & BYTEMASK);
addr += HLEN;
}
if(addr < end) { //last record
fprintf(fileref, ":%02X%04X00", end - addr, addr);
chk = 0;
chk -= end - addr;
chk -= addr & BYTEMASK;
chk -= addr >> 8;
for (i=0; i<=(end - addr); i++) {
byte = get_mbyte(addr + i);
fprintf(fileref, "%02X", byte & BYTEMASK);
chk -= byte; chk &= BYTEMASK;
cnt++;
}
fprintf(fileref, "%02X\n", chk);
addr = end;
}
fprintf(fileref,":00000001FF\n"); //EOF record
} else { //binary
while (addr <= end) {
i = get_mbyte(addr);
putc(i, fileref);
addr++; cnt++;
}
}
printf ("%d Bytes dumped from %04X\n", cnt, addr0);
}
return (SCPE_OK);
}
@ -1316,7 +1409,7 @@ int32 sim_load (FILE *fileref, CONST char *cptr, CONST char *fnam, int flag)
status = error code
*/
t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
t_stat fprint_sym(FILE *of, t_addr addr, t_value *val,
UNIT *uptr, int32 sw)
{
int32 cflag, c1, c2, inst, adr;
@ -1364,7 +1457,7 @@ t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
status = error status
*/
t_stat parse_sym (CONST char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
t_stat parse_sym(CONST char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
{
int32 cflag, i = 0, j, r;
char gbuf[CBUFSIZE];
@ -1448,4 +1541,90 @@ t_stat parse_sym (CONST char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32
return (-2);
}
/* Set history */
t_stat cpu_set_hist(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
{
int i, lnt;
t_stat r;
if (cptr == NULL) {
for (i = 0; i < hst_lnt; i++)
hst[i].pc = 0;
hst_p = 0;
return SCPE_OK;
}
lnt = (int32) get_uint (cptr, 10, HIST_MAX, &r);
if ((r != SCPE_OK) || (lnt && (lnt < HIST_MIN)))
return SCPE_ARG;
hst_p = 0;
if (hst_lnt) {
free (hst);
hst_lnt = 0;
hst = NULL;
}
if (lnt) {
hst = (InstHistory *) calloc (lnt, sizeof (InstHistory));
if (hst == NULL)
return SCPE_MEM;
hst_lnt = lnt;
}
return SCPE_OK;
}
/* Show history */
t_stat cpu_show_hist(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
{
int k, di, lnt, ir;
const char *cptr = (const char *) desc;
t_stat r;
InstHistory *h;
if (hst_lnt == 0) /* enabled? */
return SCPE_NOFNC;
if (cptr) {
lnt = (int32) get_uint (cptr, 10, hst_lnt, &r);
if ((r != SCPE_OK) || (lnt == 0))
return SCPE_ARG;
}
else lnt = hst_lnt;
di = hst_p - lnt; /* work forward */
if (di < 0)
di = di + hst_lnt;
fprintf (st, "PC SP CC A B C D E F H L Instruction\n\n");
for (k = 0; k < lnt; k++) { /* print specified */
h = &hst[(di++) % hst_lnt]; /* entry pointer */
ir = h->inst[0];
fprintf (st, "%04X %04X %02X ", h->pc , h->sp, h->psw);
fprintf (st, "%02X %02X %02X %02X %02X %02X %02X ",
h->a, h->b, h->c, h->d, h->e, h->h, h->l);
if ((fprint_sym (st, h->pc, h->inst, &i8080_unit, SWMASK ('M'))) > 0)
fprintf (st, "(undefined) %02X", h->inst[0]);
fputc ('\n', st); /* end line */
}
return SCPE_OK;
}
/* Memory examine */
t_stat i8080_ex(t_value *vptr, t_addr addr, UNIT *uptr, int32 sw)
{
if (addr >= MEMSIZE)
return SCPE_NXM;
if (vptr != NULL)
*vptr = get_mbyte(addr);
return SCPE_OK;
}
/* Memory deposit */
t_stat i8080_dep(t_value val, t_addr addr, UNIT *uptr, int32 sw)
{
if (addr >= MEMSIZE)
return SCPE_NXM;
put_mbyte(addr, val);
return SCPE_OK;
}
/* end of i8080.c */

8212
Intel-Systems/common/i8088.c
View file

File diff suppressed because it is too large Load diff

563
Intel-Systems/common/i8237.c
View file

@ -235,13 +235,17 @@
#include "system_defs.h"
#define i8237_NAME "Intel i8237 DMA Chip"
/* external globals */
/* internal function prototypes */
t_stat i8237_svc (UNIT *uptr);
t_stat i8237_cfg(uint16 base, uint16 devnum, uint8 dummy);
t_stat i8237_clr(void);
t_stat i8237_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
t_stat i8237_reset (DEVICE *dptr);
void i8237_reset_dev (uint8 devnum);
void i8237_reset_dev (void);
t_stat i8237_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
uint8 i8237_r0x(t_bool io, uint8 data, uint8 devnum);
uint8 i8237_r1x(t_bool io, uint8 data, uint8 devnum);
@ -263,112 +267,65 @@ uint8 i8237_rFx(t_bool io, uint8 data, uint8 devnum);
/* external function prototypes */
extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
extern uint8 unreg_dev(uint16);
/* globals */
static const char* i8237_desc(DEVICE *dptr) {
return i8237_NAME;
}
int i8237_baseport = -1; //base port
uint8 i8237_verb = 0; //verbose flag
/* 8237 physical register definitions */
uint16 i8237_r0[4]; // 8237 ch 0 address register
uint16 i8237_r1[4]; // 8237 ch 0 count register
uint16 i8237_r2[4]; // 8237 ch 1 address register
uint16 i8237_r3[4]; // 8237 ch 1 count register
uint16 i8237_r4[4]; // 8237 ch 2 address register
uint16 i8237_r5[4]; // 8237 ch 2 count register
uint16 i8237_r6[4]; // 8237 ch 3 address register
uint16 i8237_r7[4]; // 8237 ch 3 count register
uint8 i8237_r8[4]; // 8237 status register
uint8 i8237_r9[4]; // 8237 command register
uint8 i8237_rA[4]; // 8237 mode register
uint8 i8237_rB[4]; // 8237 mask register
uint8 i8237_rC[4]; // 8237 request register
uint8 i8237_rD[4]; // 8237 first/last ff
uint8 i8237_rE[4]; // 8237
uint8 i8237_rF[4]; // 8237
uint16 i8237_r0; // 8237 ch 0 address register
uint16 i8237_r1; // 8237 ch 0 count register
uint16 i8237_r2; // 8237 ch 1 address register
uint16 i8237_r3; // 8237 ch 1 count register
uint16 i8237_r4; // 8237 ch 2 address register
uint16 i8237_r5; // 8237 ch 2 count register
uint16 i8237_r6; // 8237 ch 3 address register
uint16 i8237_r7; // 8237 ch 3 count register
uint8 i8237_r8; // 8237 status register
uint8 i8237_r9; // 8237 command register
uint8 i8237_rA; // 8237 mode register
uint8 i8237_rB; // 8237 mask register
uint8 i8237_rC; // 8237 request register
uint8 i8237_rD; // 8237 first/last ff
uint8 i8237_rE; // 8237
uint8 i8237_rF; // 8237
/* i8237 physical register definitions */
uint16 i8237_sr[4]; // 8237 segment register
uint8 i8237_i[4]; // 8237 interrupt register
uint8 i8237_a[4]; // 8237 auxillary port register
uint16 i8237_sr; // 8237 segment register
uint8 i8237_i; // 8237 interrupt register
uint8 i8237_a; // 8237 auxillary port register
/* i8237 Standard SIMH Device Data Structures - 4 units */
/* i8237 Standard SIMH Device Data Structures - 1 unit */
UNIT i8237_unit[] = {
{ UDATA (0, 0, 0) ,20 }, /* i8237 0 */
{ UDATA (0, 0, 0) ,20 }, /* i8237 1 */
{ UDATA (0, 0, 0) ,20 }, /* i8237 2 */
{ UDATA (0, 0, 0) ,20 } /* i8237 3 */
UNIT i8237_unit = {
{ 0 }
};
REG i8237_reg[] = {
{ HRDATA (CH0ADR0, i8237_r0[0], 16) }, /* i8237 0 */
{ HRDATA (CH0CNT0, i8237_r1[0], 16) },
{ HRDATA (CH1ADR0, i8237_r2[0], 16) },
{ HRDATA (CH1CNT0, i8237_r3[0], 16) },
{ HRDATA (CH2ADR0, i8237_r4[0], 16) },
{ HRDATA (CH2CNT0, i8237_r5[0], 16) },
{ HRDATA (CH3ADR0, i8237_r6[0], 16) },
{ HRDATA (CH3CNT0, i8237_r7[0], 16) },
{ HRDATA (STAT370, i8237_r8[0], 8) },
{ HRDATA (CMD370, i8237_r9[0], 8) },
{ HRDATA (MODE0, i8237_rA[0], 8) },
{ HRDATA (MASK0, i8237_rB[0], 8) },
{ HRDATA (REQ0, i8237_rC[0], 8) },
{ HRDATA (FF0, i8237_rD[0], 8) },
{ HRDATA (SEGREG0, i8237_sr[0], 8) },
{ HRDATA (AUX0, i8237_a[0], 8) },
{ HRDATA (INT0, i8237_i[0], 8) },
{ HRDATA (CH0ADR1, i8237_r0[1], 16) }, /* i8237 1 */
{ HRDATA (CH0CNT1, i8237_r1[1], 16) },
{ HRDATA (CH1ADR1, i8237_r2[1], 16) },
{ HRDATA (CH1CNT1, i8237_r3[1], 16) },
{ HRDATA (CH2ADR1, i8237_r4[1], 16) },
{ HRDATA (CH2CNT1, i8237_r5[1], 16) },
{ HRDATA (CH3ADR1, i8237_r6[1], 16) },
{ HRDATA (CH3CNT1, i8237_r7[1], 16) },
{ HRDATA (STAT371, i8237_r8[1], 8) },
{ HRDATA (CMD371, i8237_r9[1], 8) },
{ HRDATA (MODE1, i8237_rA[1], 8) },
{ HRDATA (MASK1, i8237_rB[1], 8) },
{ HRDATA (REQ1, i8237_rC[1], 8) },
{ HRDATA (FF1, i8237_rD[1], 8) },
{ HRDATA (SEGREG1, i8237_sr[1], 8) },
{ HRDATA (AUX1, i8237_a[1], 8) },
{ HRDATA (INT1, i8237_i[1], 8) },
{ HRDATA (CH0ADR2, i8237_r0[2], 16) }, /* i8237 2 */
{ HRDATA (CH0CNT2, i8237_r1[2], 16) },
{ HRDATA (CH1ADR2, i8237_r2[2], 16) },
{ HRDATA (CH1CNT2, i8237_r3[2], 16) },
{ HRDATA (CH2ADR2, i8237_r4[2], 16) },
{ HRDATA (CH2CNT2, i8237_r5[2], 16) },
{ HRDATA (CH3ADR2, i8237_r6[2], 16) },
{ HRDATA (CH3CNT2, i8237_r7[2], 16) },
{ HRDATA (STAT372, i8237_r8[2], 8) },
{ HRDATA (CMD372, i8237_r9[2], 8) },
{ HRDATA (MODE2, i8237_rA[2], 8) },
{ HRDATA (MASK2, i8237_rB[2], 8) },
{ HRDATA (REQ2, i8237_rC[2], 8) },
{ HRDATA (FF2, i8237_rD[2], 8) },
{ HRDATA (SEGREG2, i8237_sr[2], 8) },
{ HRDATA (AUX2, i8237_a[2], 8) },
{ HRDATA (INT2, i8237_i[2], 8) },
{ HRDATA (CH0ADR3, i8237_r0[3], 16) }, /* i8237 3 */
{ HRDATA (CH0CNT3, i8237_r1[3], 16) },
{ HRDATA (CH1ADR3, i8237_r2[3], 16) },
{ HRDATA (CH1CNT3, i8237_r3[3], 16) },
{ HRDATA (CH2ADR3, i8237_r4[3], 16) },
{ HRDATA (CH2CNT3, i8237_r5[3], 16) },
{ HRDATA (CH3ADR3, i8237_r6[3], 16) },
{ HRDATA (CH3CNT3, i8237_r7[3], 16) },
{ HRDATA (STAT373, i8237_r8[3], 8) },
{ HRDATA (CMD373, i8237_r9[3], 8) },
{ HRDATA (MODE3, i8237_rA[3], 8) },
{ HRDATA (MASK3, i8237_rB[3], 8) },
{ HRDATA (REQ3, i8237_rC[3], 8) },
{ HRDATA (FF3, i8237_rD[3], 8) },
{ HRDATA (SEGREG3, i8237_sr[3], 8) },
{ HRDATA (AUX3, i8237_a[3], 8) },
{ HRDATA (INT3, i8237_i[3], 8) },
{ HRDATA (CH0ADR0, i8237_r0, 16) },
{ HRDATA (CH0CNT0, i8237_r1, 16) },
{ HRDATA (CH1ADR0, i8237_r2, 16) },
{ HRDATA (CH1CNT0, i8237_r3, 16) },
{ HRDATA (CH2ADR0, i8237_r4, 16) },
{ HRDATA (CH2CNT0, i8237_r5, 16) },
{ HRDATA (CH3ADR0, i8237_r6, 16) },
{ HRDATA (CH3CNT0, i8237_r7, 16) },
{ HRDATA (STAT370, i8237_r8, 8) },
{ HRDATA (CMD370, i8237_r9, 8) },
{ HRDATA (MODE0, i8237_rA, 8) },
{ HRDATA (MASK0, i8237_rB, 8) },
{ HRDATA (REQ0, i8237_rC, 8) },
{ HRDATA (FF0, i8237_rD, 8) },
{ HRDATA (SEGREG0, i8237_sr, 8) },
{ HRDATA (AUX0, i8237_a, 8) },
{ HRDATA (INT0, i8237_i, 8) },
{ NULL }
};
@ -389,7 +346,7 @@ DEBTAB i8237_debug[] = {
DEVICE i8237_dev = {
"8237", //name
i8237_unit, //units
&i8237_unit, //units
i8237_reg, //registers
i8237_mod, //modifiers
I8237_NUM, //numunits
@ -409,40 +366,76 @@ DEVICE i8237_dev = {
0, //dctrl
i8237_debug, //debflags
NULL, //msize
NULL //lname
NULL, //lname
NULL, //help routine
NULL, //attach help routine
NULL, //help context
&i8237_desc //device description
};
/* Service routines to handle simulator functions */
// i8251 configuration
// i8237 configuration
t_stat i8237_cfg(uint8 base, uint8 devnum)
t_stat i8237_cfg(uint16 base, uint16 devnum, uint8 dummy)
{
sim_printf(" i8237[%d]: at base port 0%02XH\n",
devnum, base & 0xFF);
reg_dev(i8237_r1x, base + 1, devnum);
reg_dev(i8237_r2x, base + 2, devnum);
reg_dev(i8237_r3x, base + 3, devnum);
reg_dev(i8237_r4x, base + 4, devnum);
reg_dev(i8237_r5x, base + 5, devnum);
reg_dev(i8237_r6x, base + 6, devnum);
reg_dev(i8237_r7x, base + 7, devnum);
reg_dev(i8237_r8x, base + 8, devnum);
reg_dev(i8237_r9x, base + 9, devnum);
reg_dev(i8237_rAx, base + 10, devnum);
reg_dev(i8237_rBx, base + 11, devnum);
reg_dev(i8237_rCx, base + 12, devnum);
reg_dev(i8237_rDx, base + 13, devnum);
reg_dev(i8237_rEx, base + 14, devnum);
reg_dev(i8237_rFx, base + 15, devnum);
i8237_baseport = base & 0x3ff;
sim_printf(" i8237: at base port 0%03XH\n",
i8237_baseport & 0x3FF);
reg_dev(i8237_r0x, i8237_baseport, 0);
reg_dev(i8237_r1x, i8237_baseport + 1, 0);
reg_dev(i8237_r2x, i8237_baseport + 2, 0);
reg_dev(i8237_r3x, i8237_baseport + 3, 0);
reg_dev(i8237_r4x, i8237_baseport + 4, 0);
reg_dev(i8237_r5x, i8237_baseport + 5, 0);
reg_dev(i8237_r6x, i8237_baseport + 6, 0);
reg_dev(i8237_r7x, i8237_baseport + 7, 0);
reg_dev(i8237_r8x, i8237_baseport + 8, 0);
reg_dev(i8237_r9x, i8237_baseport + 9, 0);
reg_dev(i8237_rAx, i8237_baseport + 10, 0);
reg_dev(i8237_rBx, i8237_baseport + 11, 0);
reg_dev(i8237_rCx, i8237_baseport + 12, 0);
reg_dev(i8237_rDx, i8237_baseport + 13, 0);
reg_dev(i8237_rEx, i8237_baseport + 14, 0);
reg_dev(i8237_rFx, i8237_baseport + 15, 0);
return SCPE_OK;
}
/* service routine - actually does the simulated DMA */
t_stat i8237_svc(UNIT *uptr)
t_stat i8237_clr(void)
{
sim_activate (&i8237_unit[uptr->u6], i8237_unit[uptr->u6].wait);
unreg_dev(i8237_baseport);
unreg_dev(i8237_baseport + 1);
unreg_dev(i8237_baseport + 2);
unreg_dev(i8237_baseport + 3);
unreg_dev(i8237_baseport + 4);
unreg_dev(i8237_baseport + 5);
unreg_dev(i8237_baseport + 6);
unreg_dev(i8237_baseport + 7);
unreg_dev(i8237_baseport + 8);
unreg_dev(i8237_baseport + 9);
unreg_dev(i8237_baseport + 10);
unreg_dev(i8237_baseport + 11);
unreg_dev(i8237_baseport + 12);
unreg_dev(i8237_baseport + 13);
unreg_dev(i8237_baseport + 14);
unreg_dev(i8237_baseport + 15);
i8237_baseport = -1;
i8237_verb = 0;
return SCPE_OK;
}
// show configuration parameters
t_stat i8237_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
{
if (uptr == NULL)
return SCPE_ARG;
fprintf(st, "Device %s\n", ((i8237_dev.flags & DEV_DIS) == 0) ? "Enabled" : "Disabled");
fprintf(st, " at Base port ");
fprintf(st, "0%03X ", i8237_baseport);
fprintf(st, "Mode ");
fprintf(st, "%s", i8237_verb ? "Verbose" : "Quiet");
fprintf(st, "\n");
return SCPE_OK;
}
@ -450,49 +443,27 @@ t_stat i8237_svc(UNIT *uptr)
t_stat i8237_reset(DEVICE *dptr)
{
uint8 devnum;
for (devnum=0; devnum<I8237_NUM; devnum++) {
i8237_reset_dev(devnum);
sim_activate (&i8237_unit[devnum], i8237_unit[devnum].wait); /* activate unit */
}
i8237_reset_dev();
return SCPE_OK;
}
void i8237_reset_dev(uint8 devnum)
void i8237_reset_dev()
{
int32 i;
UNIT *uptr;
static int flag = 1;
for (i = 0; i < 1; i++) { /* handle all units */
uptr = i8237_dev.units + i;
if (uptr->capac == 0) { /* if not configured */
// sim_printf(" SBC208%d: Not configured\n", i);
// if (flag) {
// sim_printf(" ALL: \"set isbc208 en\"\n");
// sim_printf(" EPROM: \"att isbc2080 <filename>\"\n");
// flag = 0;
// }
uptr->capac = 0; /* initialize unit */
uptr->u3 = 0;
uptr->u4 = 0;
uptr->u5 = 0;
uptr->u6 = i; /* unit number - only set here! */
sim_activate (&i8237_unit[uptr->u6], i8237_unit[uptr->u6].wait);
} else {
// sim_printf(" SBC208%d: Configured, Attached to %s\n", i, uptr->filename);
}
uptr = i8237_dev.units;
if (uptr->capac == 0) { /* if not configured */
uptr->u3 = 0;
uptr->u4 = 0;
uptr->u5 = 0;
}
devnum = uptr->u6;
i8237_r8[devnum] = 0; /* status */
i8237_r9[devnum] = 0; /* command */
i8237_rB[devnum] = 0x0F; /* mask */
i8237_rC[devnum] = 0; /* request */
i8237_rD[devnum] = 0; /* first/last FF */
i8237_r8 = 0; /* status */
i8237_r9 = 0; /* command */
i8237_rB = 0x0F; /* mask */
i8237_rC = 0; /* request */
i8237_rD = 0; /* first/last FF */
}
/* i8237 set mode = 8- or 16-bit data bus */
/* always 8-bit mode for current simulators */
@ -515,24 +486,24 @@ t_stat i8237_set_mode(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
uint8 i8237_r0x(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read current address CH 0 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0[devnum](H) read as %04X\n", i8237_r0[devnum]);
return (i8237_r0[devnum] >> 8);
if (i8237_rD) { /* high byte */
i8237_rD = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0(H) read as %04X\n", i8237_r0);
return (i8237_r0 >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0[devnum](L) read as %04X\n", i8237_r0[devnum]);
return (i8237_r0[devnum] & 0xFF);
i8237_rD++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0(L) read as %04X\n", i8237_r0);
return (i8237_r0 & 0xFF);
}
} else { /* write base & current address CH 0 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r0[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0[devnum](H) set to %04X\n", i8237_r0[devnum]);
if (i8237_rD) { /* high byte */
i8237_rD = 0;
i8237_r0 |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0(H) set to %04X\n", i8237_r0);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r0[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0[devnum](L) set to %04X\n", i8237_r0[devnum]);
i8237_rD++;
i8237_r0 = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r0(L) set to %04X\n", i8237_r0);
}
}
return 0;
@ -541,24 +512,24 @@ uint8 i8237_r0x(t_bool io, uint8 data, uint8 devnum)
uint8 i8237_r1x(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read current word count CH 0 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1[devnum](H) read as %04X\n", i8237_r1[devnum]);
return (i8237_r1[devnum] >> 8);
if (i8237_rD) { /* high byte */
i8237_rD = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1(H) read as %04X\n", i8237_r1);
return (i8237_r1 >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1[devnum](L) read as %04X\n", i8237_r1[devnum]);
return (i8237_r1[devnum] & 0xFF);
i8237_rD++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1(L) read as %04X\n", i8237_r1);
return (i8237_r1 & 0xFF);
}
} else { /* write base & current address CH 0 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r1[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1[devnum](H) set to %04X\n", i8237_r1[devnum]);
if (i8237_rD) { /* high byte */
i8237_rD = 0;
i8237_r1 |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1(H) set to %04X\n", i8237_r1);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r1[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1[devnum](L) set to %04X\n", i8237_r1[devnum]);
i8237_rD++;
i8237_r1 = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r1(L) set to %04X\n", i8237_r1);
}
}
return 0;
@ -567,24 +538,24 @@ uint8 i8237_r1x(t_bool io, uint8 data, uint8 devnum)
uint8 i8237_r2x(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read current address CH 1 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2[devnum](H) read as %04X\n", i8237_r2[devnum]);
return (i8237_r2[devnum] >> 8);
if (i8237_rD) { /* high byte */
i8237_rD = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2(H) read as %04X\n", i8237_r2);
return (i8237_r2 >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2[devnum](L) read as %04X\n", i8237_r2[devnum]);
return (i8237_r2[devnum] & 0xFF);
i8237_rD++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2(L) read as %04X\n", i8237_r2);
return (i8237_r2 & 0xFF);
}
} else { /* write base & current address CH 1 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r2[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2[devnum](H) set to %04X\n", i8237_r2[devnum]);
if (i8237_rD) { /* high byte */
i8237_rD = 0;
i8237_r2 |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2(H) set to %04X\n", i8237_r2);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r2[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2[devnum](L) set to %04X\n", i8237_r2[devnum]);
i8237_rD++;
i8237_r2 = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r2(L) set to %04X\n", i8237_r2);
}
}
return 0;
@ -593,24 +564,24 @@ uint8 i8237_r2x(t_bool io, uint8 data, uint8 devnum)
uint8 i8237_r3x(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read current word count CH 1 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3[devnum](H) read as %04X\n", i8237_r3[devnum]);
return (i8237_r3[devnum] >> 8);
if (i8237_rD) { /* high byte */
i8237_rD = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3(H) read as %04X\n", i8237_r3);
return (i8237_r3 >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3[devnum](L) read as %04X\n", i8237_r3[devnum]);
return (i8237_r3[devnum] & 0xFF);
i8237_rD++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3(L) read as %04X\n", i8237_r3);
return (i8237_r3 & 0xFF);
}
} else { /* write base & current address CH 1 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r3[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3[devnum](H) set to %04X\n", i8237_r3[devnum]);
if (i8237_rD) { /* high byte */
i8237_rD = 0;
i8237_r3 |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3(H) set to %04X\n", i8237_r3);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r3[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3[devnum](L) set to %04X\n", i8237_r3[devnum]);
i8237_rD++;
i8237_r3 = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r3(L) set to %04X\n", i8237_r3);
}
}
return 0;
@ -619,24 +590,24 @@ uint8 i8237_r3x(t_bool io, uint8 data, uint8 devnum)
uint8 i8237_r4x(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read current address CH 2 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4[devnum](H) read as %04X\n", i8237_r4[devnum]);
return (i8237_r4[devnum] >> 8);
if (i8237_rD) { /* high byte */
i8237_rD = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4(H) read as %04X\n", i8237_r4);
return (i8237_r4 >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4[devnum](L) read as %04X\n", i8237_r4[devnum]);
return (i8237_r4[devnum] & 0xFF);
i8237_rD++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4(L) read as %04X\n", i8237_r4);
return (i8237_r4 & 0xFF);
}
} else { /* write base & current address CH 2 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r4[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4[devnum](H) set to %04X\n", i8237_r4[devnum]);
if (i8237_rD) { /* high byte */
i8237_rD = 0;
i8237_r4 |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4(H) set to %04X\n", i8237_r4);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r4[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4[devnum](L) set to %04X\n", i8237_r4[devnum]);
i8237_rD++;
i8237_r4 = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r4(L) set to %04X\n", i8237_r4);
}
}
return 0;
@ -645,24 +616,24 @@ uint8 i8237_r4x(t_bool io, uint8 data, uint8 devnum)
uint8 i8237_r5x(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read current word count CH 2 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5[devnum](H) read as %04X\n", i8237_r5[devnum]);
return (i8237_r5[devnum] >> 8);
if (i8237_rD) { /* high byte */
i8237_rD = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5(H) read as %04X\n", i8237_r5);
return (i8237_r5 >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5[devnum](L) read as %04X\n", i8237_r5[devnum]);
return (i8237_r5[devnum] & 0xFF);
i8237_rD++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5(L) read as %04X\n", i8237_r5);
return (i8237_r5 & 0xFF);
}
} else { /* write base & current address CH 2 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r5[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5[devnum](H) set to %04X\n", i8237_r5[devnum]);
if (i8237_rD) { /* high byte */
i8237_rD = 0;
i8237_r5 |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5(H) set to %04X\n", i8237_r5);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r5[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5[devnum](L) set to %04X\n", i8237_r5[devnum]);
i8237_rD++;
i8237_r5 = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r5(L) set to %04X\n", i8237_r5);
}
}
return 0;
@ -671,24 +642,24 @@ uint8 i8237_r5x(t_bool io, uint8 data, uint8 devnum)
uint8 i8237_r6x(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read current address CH 3 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6[devnum](H) read as %04X\n", i8237_r6[devnum]);
return (i8237_r6[devnum] >> 8);
if (i8237_rD) { /* high byte */
i8237_rD = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6(H) read as %04X\n", i8237_r6);
return (i8237_r6 >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6[devnum](L) read as %04X\n", i8237_r6[devnum]);
return (i8237_r6[devnum] & 0xFF);
i8237_rD++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6(L) read as %04X\n", i8237_r6);
return (i8237_r6 & 0xFF);
}
} else { /* write base & current address CH 3 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r6[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6[devnum](H) set to %04X\n", i8237_r6[devnum]);
if (i8237_rD) { /* high byte */
i8237_rD = 0;
i8237_r6 |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6(H) set to %04X\n", i8237_r6);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r6[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6[devnum](L) set to %04X\n", i8237_r6[devnum]);
i8237_rD++;
i8237_r6 = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r6(L) set to %04X\n", i8237_r6);
}
}
return 0;
@ -697,24 +668,24 @@ uint8 i8237_r6x(t_bool io, uint8 data, uint8 devnum)
uint8 i8237_r7x(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read current word count CH 3 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7[devnum](H) read as %04X\n", i8237_r7[devnum]);
return (i8237_r7[devnum] >> 8);
if (i8237_rD) { /* high byte */
i8237_rD = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7(H) read as %04X\n", i8237_r7);
return (i8237_r7 >> 8);
} else { /* low byte */
i8237_rD[devnum]++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7[devnum](L) read as %04X\n", i8237_r7[devnum]);
return (i8237_r7[devnum] & 0xFF);
i8237_rD++;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7(L) read as %04X\n", i8237_r7);
return (i8237_r7 & 0xFF);
}
} else { /* write base & current address CH 3 */
if (i8237_rD[devnum]) { /* high byte */
i8237_rD[devnum] = 0;
i8237_r7[devnum] |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7[devnum](H) set to %04X\n", i8237_r7[devnum]);
if (i8237_rD) { /* high byte */
i8237_rD = 0;
i8237_r7 |= (data << 8);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7(H) set to %04X\n", i8237_r7);
} else { /* low byte */
i8237_rD[devnum]++;
i8237_r7[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7[devnum](L) set to %04X\n", i8237_r7[devnum]);
i8237_rD++;
i8237_r7 = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r7(L) set to %04X\n", i8237_r7);
}
}
return 0;
@ -723,11 +694,11 @@ uint8 i8237_r7x(t_bool io, uint8 data, uint8 devnum)
uint8 i8237_r8x(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read status register */
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r8[devnum] (status) read as %02X\n", i8237_r8[devnum]);
return (i8237_r8[devnum]);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r8 (status) read as %02X\n", i8237_r8);
return (i8237_r8);
} else { /* write command register */
i8237_r9[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r9[devnum] (command) set to %02X\n", i8237_r9[devnum]);
i8237_r9 = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_r9 (command) set to %02X\n", i8237_r9);
}
return 0;
}
@ -735,11 +706,11 @@ uint8 i8237_r8x(t_bool io, uint8 data, uint8 devnum)
uint8 i8237_r9x(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) {
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_r9[devnum]\n");
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_r9\n");
return 0;
} else { /* write request register */
i8237_rC[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rC[devnum] (request) set to %02X\n", i8237_rC[devnum]);
i8237_rC = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rC (request) set to %02X\n", i8237_rC);
}
return 0;
}
@ -747,36 +718,36 @@ uint8 i8237_r9x(t_bool io, uint8 data, uint8 devnum)
uint8 i8237_rAx(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) {
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rA[devnum]\n");
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rA\n");
return 0;
} else { /* write single mask register */
switch(data & 0x03) {
case 0:
if (data & 0x04)
i8237_rB[devnum] |= 1;
i8237_rB |= 1;
else
i8237_rB[devnum] &= ~1;
i8237_rB &= ~1;
break;
case 1:
if (data & 0x04)
i8237_rB[devnum] |= 2;
i8237_rB |= 2;
else
i8237_rB[devnum] &= ~2;
i8237_rB &= ~2;
break;
case 2:
if (data & 0x04)
i8237_rB[devnum] |= 4;
i8237_rB |= 4;
else
i8237_rB[devnum] &= ~4;
i8237_rB &= ~4;
break;
case 3:
if (data & 0x04)
i8237_rB[devnum] |= 8;
i8237_rB |= 8;
else
i8237_rB[devnum] &= ~8;
i8237_rB &= ~8;
break;
}
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rB[devnum] (mask) set to %02X\n", i8237_rB[devnum]);
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rB (mask) set to %02X\n", i8237_rB);
}
return 0;
}
@ -784,11 +755,11 @@ uint8 i8237_rAx(t_bool io, uint8 data, uint8 devnum)
uint8 i8237_rBx(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) {
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rB[devnum]\n");
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rB\n");
return 0;
} else { /* write mode register */
i8237_rA[devnum] = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rA[devnum] (mode) set to %02X\n", i8237_rA[devnum]);
i8237_rA = data & 0xFF;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rA (mode) set to %02X\n", i8237_rA);
}
return 0;
}
@ -796,11 +767,11 @@ uint8 i8237_rBx(t_bool io, uint8 data, uint8 devnum)
uint8 i8237_rCx(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) {
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rC[devnum]\n");
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rC\n");
return 0;
} else { /* clear byte pointer FF */
i8237_rD[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rD[devnum] (FF) cleared\n");
i8237_rD = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rD (FF) cleared\n");
}
return 0;
}
@ -808,7 +779,7 @@ uint8 i8237_rCx(t_bool io, uint8 data, uint8 devnum)
uint8 i8237_rDx(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read temporary register */
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rD[devnum]\n");
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rD\n");
return 0;
} else { /* master clear */
i8237_reset_dev(devnum);
@ -820,11 +791,11 @@ uint8 i8237_rDx(t_bool io, uint8 data, uint8 devnum)
uint8 i8237_rEx(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) {
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rE[devnum]\n");
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rE\n");
return 0;
} else { /* clear mask register */
i8237_rB[devnum] = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rB[devnum] (mask) cleared\n");
i8237_rB = 0;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rB (mask) cleared\n");
}
return 0;
}
@ -832,11 +803,11 @@ uint8 i8237_rEx(t_bool io, uint8 data, uint8 devnum)
uint8 i8237_rFx(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) {
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rF[devnum]\n");
sim_debug (DEBUG_reg, &i8237_dev, "Illegal read of i8237_rF\n");
return 0;
} else { /* write all mask register bits */
i8237_rB[devnum] = data & 0x0F;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rB[devnum] (mask) set to %02X\n", i8237_rB[devnum]);
i8237_rB = data & 0x0F;
sim_debug (DEBUG_reg, &i8237_dev, "i8237_rB (mask) set to %02X\n", i8237_rB);
}
return 0;
}

21
Intel-Systems/common/i8251.c
View file

@ -149,7 +149,7 @@ t_stat i8251_svc (UNIT *uptr);
t_stat i8251_reset (DEVICE *dptr);
uint8 i8251s(t_bool io, uint8 data, uint8 devnum);
uint8 i8251d(t_bool io, uint8 data, uint8 devnum);
void i8251_reset_dev(uint8 devnum);
void i8251_reset_dev(uint16 devnum);
/* i8251 Standard I/O Data Structures */
/* up to 4 i8251 devices */
@ -187,8 +187,6 @@ DEBTAB i8251_debug[] = {
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "XACK", DEBUG_xack },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ NULL }
};
@ -196,7 +194,7 @@ MTAB i8251_mod[] = {
{ UNIT_ANSI, 0, "ANSI", "ANSI", NULL },
{ UNIT_ANSI, UNIT_ANSI, "TTY", "TTY", NULL },
{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, i8251_show_param, NULL,
"show configured parametes for i8251" },
"show configured parameters for i8251" },
{ 0 }
};
@ -235,11 +233,14 @@ DEVICE i8251_dev = {
t_stat i8251_cfg(uint16 base, uint16 devnum, uint8 dummy)
{
i8251_baseport[devnum] = base & 0xff;
i8251_baseport[devnum] = base & BYTEMASK;
sim_printf(" i8251%d: installed at base port 0%02XH\n",
devnum, i8251_baseport[devnum]);
reg_dev(i8251d, i8251_baseport[devnum], devnum, 0);
reg_dev(i8251s, i8251_baseport[devnum] + 1, devnum, 0);
i8251_reset_dev(devnum);
if (devnum == 0)
sim_activate (&i8251_unit[devnum], i8251_unit[devnum].wait); /* activate unit 0 */
i8251_num++; //next device
return SCPE_OK;
}
@ -295,7 +296,7 @@ t_stat i8251_svc (UNIT *uptr)
if (uptr->flags & UNIT_ANSI)
uptr->buf = toupper(uptr->buf);
uptr->u3 |= RXR; /* Set status */
return SCPE_OK;
return SCPE_OK;
}
/* Reset routine */
@ -304,15 +305,15 @@ t_stat i8251_reset (DEVICE *dptr)
{
uint8 devnum;
for (devnum=0; devnum<I8251_NUM; devnum++) {
for (devnum=0; devnum<i8251_num+1; devnum++) {
i8251_reset_dev(devnum);
if (devnum == 0)
sim_activate (&i8251_unit[devnum], i8251_unit[devnum].wait); /* activate unit */
sim_activate (&i8251_unit[devnum], i8251_unit[devnum].wait); /* activate unit 0 */
}
return SCPE_OK;
}
void i8251_reset_dev(uint8 devnum)
void i8251_reset_dev(uint16 devnum)
{
i8251_unit[devnum].u3 = TXR + TXE; /* status */
i8251_unit[devnum].u4 = 0; /* mode instruction */
@ -340,7 +341,7 @@ uint8 i8251s(t_bool io, uint8 data, uint8 devnum)
i8251_unit[devnum].u6 = 1; /* set cmd received */
}
}
return 0;
return 0;
}
uint8 i8251d(t_bool io, uint8 data, uint8 devnum)

371
Intel-Systems/common/i8253.c
View file

@ -53,6 +53,29 @@ int i8253_num = 0;
int i8253_baseport[] = { -1, -1, -1, -1 }; //base port
uint8 i8253_intnum[4] = { 0, 0, 0, 0 }; //interrupt number
uint8 i8253_verb[4] = { 0, 0, 0, 0 }; //verbose flag
uint8 i8253_T0_control_word[4];
uint8 i8253_T0_flag[4];
uint16 i8253_T0_load[4];
uint16 i8253_T0_latch[4];
uint16 i8253_T0_count[4];
int i8253_T0_gate[4];
int i8253_T0_out[4];
uint8 i8253_T1_control_word[4];
uint8 i8253_T1_flag[4];
uint16 i8253_T1_load[4];
uint16 i8253_T1_latch[4];
uint16 i8253_T1_count[4];
int i8253_T1_gate[4];
int i8253_T1_out[4];
uint8 i8253_T2_control_word[4];
uint8 i8253_T2_flag[4];
uint16 i8253_T2_load[4];
uint16 i8253_T2_latch[4];
uint16 i8253_T2_count[4];
int i8253_T2_gate[4];
int i8253_T2_out[4];
/* function prototypes */
t_stat i8253_cfg(uint16 base, uint16 devnum, uint8 dummy);
@ -76,14 +99,10 @@ UNIT i8253_unit[] = {
};
REG i8253_reg[] = {
{ HRDATA (T0, i8253_unit[0].u3, 8) },
{ HRDATA (T1, i8253_unit[0].u4, 8) },
{ HRDATA (T2, i8253_unit[0].u5, 8) },
{ HRDATA (CMD, i8253_unit[0].u6, 8) },
{ HRDATA (T0, i8253_unit[1].u3, 8) },
{ HRDATA (T1, i8253_unit[1].u4, 8) },
{ HRDATA (T2, i8253_unit[1].u5, 8) },
{ HRDATA (CMD, i8253_unit[1].u6, 8) },
{ URDATAD(T0,i8253_unit[0].u3,16,8,0,4,0,"Timer 0") },
{ URDATAD(T1,i8253_unit[0].u4,16,8,0,4,0,"Timer 1") },
{ URDATAD(T2,i8253_unit[0].u5,16,8,0,4,0,"Timer 2") },
{ URDATAD(CMD,i8253_unit[0].u6,16,8,0,4,0,"Command") },
{ NULL }
};
@ -92,14 +111,13 @@ DEBTAB i8253_debug[] = {
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ "XACK", DEBUG_xack },
{ NULL }
};
MTAB i8253_mod[] = {
{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, i8253_show_param, NULL,
"show configured parametes for i8253" },
"show configured parameters for i8253" },
{ 0 }
};
@ -110,7 +128,7 @@ DEVICE i8253_dev = {
i8253_unit, //units
i8253_reg, //registers
i8253_mod, //modifiers
I8253_NUM, //numunits
4, //numunits
16, //aradix
16, //awidth
1, //aincr
@ -140,17 +158,24 @@ DEVICE i8253_dev = {
t_stat i8253_cfg(uint16 base, uint16 devnum, uint8 dummy)
{
i8253_baseport[devnum] = base & 0xff;
UNIT *uptr;
uptr = i8253_dev.units;
i8253_baseport[devnum] = base & BYTEMASK;
sim_printf(" i8253%d: installed at base port 0%02XH\n",
devnum, i8253_baseport[devnum]);
reg_dev(i8253t0, i8253_baseport[devnum], devnum, 0);
reg_dev(i8253t1, i8253_baseport[devnum] + 1, devnum, 0);
reg_dev(i8253t2, i8253_baseport[devnum] + 2, devnum, 0);
reg_dev(i8253c, i8253_baseport[devnum] + 3, devnum, 0);
uptr->u6 = i8253_num;
i8253_num++;
sim_activate (uptr, uptr->wait); /* start poll */
return SCPE_OK;
}
// i8253 unconfiguration
t_stat i8253_clr(void)
{
int i;
@ -189,11 +214,130 @@ t_stat i8253_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
return SCPE_OK;
}
/* i8253_svc - actually gets char & places in buffer */
/* i8253_svc - actually does timing */
t_stat i8253_svc (UNIT *uptr)
{
sim_activate (&i8253_unit[0], i8253_unit[0].wait); /* continue poll */
int devnum;
if (uptr == NULL)
return SCPE_ARG;
devnum = uptr->u6; //get devnum for unit
switch (i8253_T0_control_word[devnum]) {
case 0: //mode 0
break;
case 1: //mode 1
break;
case 2: //mode 2 - rate generator
if (i8253_T0_gate[devnum]) {
i8253_T0_out[devnum] = 0;
if (i8253_T0_flag[devnum] == 0x10) {
i8253_T0_count[devnum]--; //decrement counter
if (i8253_T0_count[devnum] == 0) { //if 0, do something
i8253_T0_out[devnum] = 1;
i8253_T0_count[devnum] = i8253_T0_load[devnum];
} else {
i8253_T0_out[devnum] = 1;
}
}
}
break;
case 3: //mode 3 - square wave rate generator
if (i8253_T0_gate[devnum]) {
i8253_T0_out[devnum] = 0;
if (i8253_T0_flag[devnum] == 0x10) {
i8253_T0_count[devnum]--; //decrement counter
if (i8253_T0_count[devnum] == 0) { //if 0, do something
i8253_T0_out[devnum] = ~i8253_T0_out[devnum];
i8253_T0_count[devnum] = i8253_T0_load[devnum];
} else {
i8253_T0_out[devnum] = 1;
}
}
}
break;
case 4: //mode 4
break;
case 5: //mode 5
break;
}
switch (i8253_T1_control_word[devnum]) {
case 0: //mode 0
break;
case 1: //mode 1
break;
case 2: //mode 2 - rate generator
if (i8253_T1_gate[devnum]) {
i8253_T1_out[devnum] = 0;
if (i8253_T0_flag[devnum] == 0x20) {
i8253_T1_count[devnum]--; //decrement counter
if (i8253_T1_count[devnum] == 0) { //if 0, do something
i8253_T1_out[devnum] = 1;
i8253_T1_count[devnum] = i8253_T1_load[devnum];
} else {
i8253_T1_out[devnum] = 1;
}
}
}
break;
case 3: //mode 3 - square wave rate generator
if (i8253_T1_gate[devnum]) {
i8253_T1_out[devnum] = 0;
if (i8253_T0_flag[devnum] == 0x20) {
i8253_T1_count[devnum]--; //decrement counter
if (i8253_T1_count[devnum] == 0) { //if 0, do something
i8253_T1_out[devnum] = ~i8253_T1_out[devnum];
i8253_T1_count[devnum] = i8253_T1_load[devnum];
} else {
i8253_T1_out[devnum] = 1;
}
}
}
break;
case 4: //mode 4
break;
case 5: //mode 5
break;
}
switch (i8253_T2_control_word[devnum]) {
case 0: //mode 0
break;
case 1: //mode 1
break;
case 2: //mode 2 - rate generator
if (i8253_T2_gate[devnum]) {
i8253_T2_out[devnum] = 0;
if (i8253_T0_flag[devnum] == 0x40) {
i8253_T2_count[devnum]--; //decrement counter
if (i8253_T2_count[devnum] == 0) { //if 0, do something
i8253_T2_out[devnum] = 1;
i8253_T2_count[devnum] = i8253_T2_load[devnum];
} else {
i8253_T2_out[devnum] = 1;
}
}
}
break;
case 3: //mode 3 - square wave rate generator
if (i8253_T2_gate[devnum]) {
i8253_T2_out[devnum] = 0;
if (i8253_T0_flag[devnum] == 0x40) {
i8253_T2_count[devnum]--; //decrement counter
if (i8253_T2_count[devnum] == 0) { //if 0, do something
i8253_T2_out[devnum] = ~i8253_T2_out[devnum];
i8253_T2_count[devnum] = i8253_T2_load[devnum];
} else {
i8253_T2_out[devnum] = 1;
}
}
}
break;
case 4: //mode 4
break;
case 5: //mode 5
break;
}
sim_activate (uptr, uptr->wait); /* continue poll */
return SCPE_OK;
}
@ -201,14 +345,15 @@ t_stat i8253_svc (UNIT *uptr)
t_stat i8253_reset (DEVICE *dptr)
{
uint8 devnum;
int i;
for (devnum=0; devnum<i8253_num+1; devnum++) {
i8253_unit[devnum].u3 = 0; /* status */
i8253_unit[devnum].u4 = 0; /* mode instruction */
i8253_unit[devnum].u5 = 0; /* command instruction */
i8253_unit[devnum].u6 = 0;
}
for (i = 0; i < 4; i++)
if (i < i8253_num)
i8253_unit[i].flags = 0;
else {
sim_cancel (&i8253_unit[i]);
i8253_unit[i].flags = UNIT_DIS;
}
return SCPE_OK;
}
@ -218,48 +363,198 @@ t_stat i8253_reset (DEVICE *dptr)
uint8 i8253t0(t_bool io, uint8 data, uint8 devnum)
{
uint8 rl;
rl = (i8253_T1_control_word[devnum] >> 4) & 0x03;
if (io == 0) { /* read data port */
return i8253_unit[devnum].u3;
switch (rl) {
case 0: //counter latching
i8253_T1_latch[devnum] = i8253_T1_count[devnum];
break;
case 1: //read/load msb
i8253_T1_latch[devnum] = i8253_T1_count[devnum];
return (i8253_T1_latch[devnum] >> 8);
break;
case 2: //read/load lsb
i8253_T1_latch[devnum] = i8253_T1_count[devnum];
return (i8253_T1_latch[devnum] & BYTEMASK);
break;
case 3: //read/load lsb then msb
i8253_T1_latch[devnum] = i8253_T1_count[devnum];
break;
}
if ((i8253_T1_flag[devnum] & 0x01) == 0) {
i8253_T1_flag[devnum] |= 0x01;
return (i8253_T1_latch[devnum] & BYTEMASK);
} else {
i8253_T1_flag[devnum] &= 0xfe;
return (i8253_T1_latch[devnum] >> 8);
}
} else { /* write data port */
i8253_unit[devnum].u3 = data;
//sim_activate_after (&i8253_unit[devnum], );
return 0;
switch (rl) {
case 0: //counter latching
i8253_T1_latch[devnum] = i8253_T1_count[devnum];
break;
case 1: //read/load msb
i8253_T1_load[devnum] = (data << 8);
i8253_T1_flag[devnum] |= 0x10;
break;
case 2: //read/load lsb
i8253_T1_load[devnum] = data;
i8253_T1_flag[devnum] |= 0x10;
break;
case 3: //read/load lsb then msb
if ((i8253_T1_flag[devnum] & 0x01) == 0) {
i8253_T1_load[devnum] = data;
i8253_T1_flag[devnum] |= 0x01;
} else {
i8253_T1_load[devnum] |= (data << 8);
i8253_T1_flag[devnum] &= 0xfe;
i8253_T1_flag[devnum] |= 0x10;
}
break;
}
}
return 0;
}
//read routine:
//sim_activate_time(&i8253_unit[devnum])/sim_inst_per_second()
uint8 i8253t1(t_bool io, uint8 data, uint8 devnum)
{
uint8 rl;
rl = (i8253_T1_control_word[devnum] >> 4) & 0x03;
if (io == 0) { /* read data port */
return i8253_unit[devnum].u4;
switch (rl) {
case 0: //counter latching
i8253_T1_latch[devnum] = i8253_T1_count[devnum];
break;
case 1: //read/load msb
i8253_T1_latch[devnum] = i8253_T1_count[devnum];
return (i8253_T1_latch[devnum] >> 8);
break;
case 2: //read/load lsb
i8253_T1_latch[devnum] = i8253_T1_count[devnum];
return (i8253_T1_latch[devnum] & BYTEMASK);
break;
case 3: //read/load lsb then msb
i8253_T1_latch[devnum] = i8253_T1_count[devnum];
break;
}
if ((i8253_T1_flag[devnum] & 0x02) == 0) {
i8253_T1_flag[devnum] |= 0x02;
return (i8253_T1_latch[devnum] & BYTEMASK);
} else {
i8253_T1_flag[devnum] &= 0xfd;
return (i8253_T1_latch[devnum] >> 8);
}
} else { /* write data port */
i8253_unit[devnum].u4 = data;
return 0;
switch (rl) {
case 0: //counter latching
i8253_T1_latch[devnum] = i8253_T1_count[devnum];
break;
case 1: //read/load msb
i8253_T1_load[devnum] = (data << 8);
i8253_T1_flag[devnum] |= 0x20;
break;
case 2: //read/load lsb
i8253_T1_load[devnum] = data;
i8253_T1_flag[devnum] |= 0x20;
break;
case 3: //read/load lsb then msb
if ((i8253_T1_flag[devnum] & 0x02) == 0) {
i8253_T1_load[devnum] = data;
i8253_T1_flag[devnum] |= 0x02;
} else {
i8253_T1_load[devnum] |= (data << 8);
i8253_T1_flag[devnum] &= 0xfd;
i8253_T1_flag[devnum] |= 0x20;
}
break;
}
}
return 0;
}
uint8 i8253t2(t_bool io, uint8 data, uint8 devnum)
{
uint8 rl;
rl = (i8253_T2_control_word[devnum] >> 4) & 0x03;
if (io == 0) { /* read data port */
return i8253_unit[devnum].u5;
switch (rl) {
case 0: //counter latching
i8253_T2_latch[devnum] = i8253_T2_count[devnum];
break;
case 1: //read/load msb
i8253_T2_latch[devnum] = i8253_T2_count[devnum];
return (i8253_T2_latch[devnum] >> 8);
break;
case 2: //read/load lsb
i8253_T2_latch[devnum] = i8253_T2_count[devnum];
return (i8253_T2_latch[devnum] & BYTEMASK);
break;
case 3: //read/load lsb then msb
i8253_T2_latch[devnum] = i8253_T2_count[devnum];
break;
}
if ((i8253_T2_flag[devnum] & 0x04) == 0) {
i8253_T2_flag[devnum] |= 0x04;
return (i8253_T2_latch[devnum] & BYTEMASK);
}
else {
i8253_T2_flag[devnum] &= 0xfb;
return (i8253_T2_latch[devnum] >> 8);
}
} else { /* write data port */
i8253_unit[devnum].u5 = data;
return 0;
switch (rl) {
case 0: //counter latching
i8253_T2_latch[devnum] = i8253_T2_count[devnum];
break;
case 1: //read/load msb
i8253_T2_load[devnum] = (data << 8);
i8253_T2_flag[devnum] |= 0x40;
break;
case 2: //read/load lsb
i8253_T2_load[devnum] = data;
i8253_T2_flag[devnum] |= 0x40;
break;
case 3: //read/load lsb then msb
if ((i8253_T2_flag[devnum] & 0x04) == 0) {
i8253_T2_load[devnum] = data;
i8253_T2_flag[devnum] |= 0x04;
} else {
i8253_T2_load[devnum] |= (data << 8);
i8253_T2_flag[devnum] &= 0xfb;
i8253_T2_flag[devnum] |= 0x40;
}
break;
}
}
return 0;
}
uint8 i8253c(t_bool io, uint8 data, uint8 devnum)
{
uint8 sc;
if (io == 0) { /* read status port */
return i8253_unit[devnum].u6;
return 0xff;
} else { /* write data port */
i8253_unit[devnum].u6 = data;
return 0;
sc = (data >> 6) & 0x03;
switch (sc) {
case 0:
i8253_T0_control_word[devnum] = data;
i8253_T0_flag[devnum] = 0;
break;
case 1:
i8253_T1_control_word[devnum] = data;
i8253_T1_flag[devnum] = 0;
break;
case 2:
i8253_T2_control_word[devnum] = data;
i8253_T2_flag[devnum] = 0;
break;
}
}
return 0;
}

11
Intel-Systems/common/i8255.c
View file

@ -152,7 +152,7 @@ MTAB i8255_mod[] = {
// { MTAB_XTD | MTAB_VDV, 0, NULL, "INT", &isbc202_set_int,
// NULL, NULL, "Sets the interrupt number for i8255"},
{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, i8255_show_param, NULL,
"show configured parametes for i8255" },
"show configured parameters for i8255" },
{ 0 }
};
@ -161,8 +161,7 @@ DEBTAB i8255_debug[] = {
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ "XACK", DEBUG_xack },
{ NULL }
};
@ -204,7 +203,7 @@ t_stat i8255_cfg(uint16 base, uint16 devnum, uint8 dummy)
DEVICE *dptr;
dptr = find_dev (i8255_dev.name);
i8255_baseport[devnum] = base & 0xff;
i8255_baseport[devnum] = base & BYTEMASK;
sim_printf(" i8255%d: installed at base port 0%02XH\n",
devnum, i8255_baseport[devnum]);
reg_dev(i8255a, i8255_baseport[devnum], devnum, 0);
@ -257,9 +256,7 @@ t_stat i8255_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
t_stat i8255_reset (DEVICE *dptr)
{
// if ((dptr->flags & DEV_DIS) == 0) { // enabled
i8255_reset_dev(); //software reset
// }
i8255_reset_dev(); //software reset
return SCPE_OK;
}

38
Intel-Systems/common/i8259.c
View file

@ -92,18 +92,9 @@ UNIT i8259_unit[] = {
};
REG i8259_reg[] = {
{ HRDATA (IRR0, i8259_unit[0].u3, 8) }, /* i8259 0 */
{ HRDATA (ISR0, i8259_unit[0].u4, 8) },
{ HRDATA (IMR0, i8259_unit[0].u5, 8) },
{ HRDATA (IRR1, i8259_unit[1].u3, 8) }, /* i8259 1 */
{ HRDATA (ISR1, i8259_unit[1].u4, 8) },
{ HRDATA (IMR1, i8259_unit[1].u5, 8) },
{ HRDATA (IRR1, i8259_unit[2].u3, 8) }, /* i8259 2 */
{ HRDATA (ISR1, i8259_unit[2].u4, 8) },
{ HRDATA (IMR1, i8259_unit[2].u5, 8) },
{ HRDATA (IRR1, i8259_unit[3].u3, 8) }, /* i8259 3 */
{ HRDATA (ISR1, i8259_unit[3].u4, 8) },
{ HRDATA (IMR1, i8259_unit[3].u5, 8) },
{ URDATAD(IRR0,i8259_unit[0].u3,16,8,0,4,0,"IRR0") },
{ URDATAD(ISR0,i8259_unit[0].u4,16,8,0,4,0,"ISR0") },
{ URDATAD(IMR0,i8259_unit[0].u5,16,8,0,4,0,"IMR0") },
{ NULL }
};
@ -112,14 +103,13 @@ DEBTAB i8259_debug[] = {
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ "XACK", DEBUG_xack },
{ NULL }
};
MTAB i8259_mod[] = {
{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, i8259_show_param, NULL,
"show configured parametes for i8259" },
"show configured parameters for i8259" },
{ 0 }
};
@ -130,7 +120,7 @@ DEVICE i8259_dev = {
i8259_unit, //units
i8259_reg, //registers
i8259_mod, //modifiers
I8259_NUM, //numunits
4, //numunits
16, //aradix
16, //awidth
1, //aincr
@ -162,7 +152,7 @@ DEVICE i8259_dev = {
t_stat i8259_cfg(uint16 base, uint16 devnum, uint8 dummy)
{
i8259_baseport[devnum] = base & 0xff;
i8259_baseport[devnum] = base & BYTEMASK;
sim_printf(" i8259%d: installed at base port 0%02XH\n",
devnum, i8259_baseport[devnum]);
reg_dev(i8259a, i8259_baseport[devnum], devnum, 0);
@ -213,10 +203,16 @@ t_stat i8259_reset (DEVICE *dptr)
{
uint8 devnum;
for (devnum=0; devnum<i8259_num+1; devnum++) {
i8259_unit[devnum].u3 = 0x00; /* IRR */
i8259_unit[devnum].u4 = 0x00; /* ISR */
i8259_unit[devnum].u5 = 0x00; /* IMR */
for (devnum=0; devnum < 4; devnum++) {
if (devnum < i8259_num) {
i8259_unit[devnum].flags = 0;
i8259_unit[devnum].u3 = 0x00; /* IRR */
i8259_unit[devnum].u4 = 0x00; /* ISR */
i8259_unit[devnum].u5 = 0x00; /* IMR */
} else {
sim_cancel (&i8259_unit[devnum]);
i8259_unit[devnum].flags = UNIT_DIS;
}
}
return SCPE_OK;
}

5
Intel-Systems/common/ieprom.c
View file

@ -73,7 +73,7 @@ MTAB EPROM_mod[] = {
// { MTAB_XTD | MTAB_VDV, 0, NULL, "BASE", &isbc464_set_base,
// NULL, NULL, "Sets the ROM base for EPROM" },
{ MTAB_XTD|MTAB_VDV, 0, "PARAM", NULL, NULL, &EPROM_show_param, NULL,
"Parameters" },
"show configured parameters for iEPROM" },
{ 0 }
};
@ -83,8 +83,6 @@ DEBTAB EPROM_debug[] = {
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "XACK", DEBUG_xack },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ NULL }
};
@ -153,6 +151,7 @@ t_stat EPROM_clr(void)
t_stat EPROM_reset (DEVICE *dptr)
{
EPROM_clr();
return SCPE_OK;
}

10
Intel-Systems/common/ioc-cont.c
View file

@ -115,14 +115,12 @@ DEBTAB ioc_cont_debug[] = {
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "XACK", DEBUG_xack },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ NULL }
};
MTAB ioc_cont_mod[] = {
{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, ioc_cont_show_param, NULL,
"show configured parametes for ioc_cont" },
"show configured parameters for ioc_cont" },
{ 0 }
};
@ -157,9 +155,9 @@ DEVICE ioc_cont_dev = {
t_stat ioc_cont_cfg(uint16 base, uint16 devnum, uint8 dummy)
{
sim_printf(" ioc-cont: at base port 0%02XH\n",
base & 0xFF);
ioc_cont_baseport = base & 0xff;
sim_printf(" ioc-cont: installed at base port 0%02XH\n",
base & BYTEMASK);
ioc_cont_baseport = base & BYTEMASK;
reg_dev(ioc_cont0, base, 0, 0);
reg_dev(ioc_cont1, base + 1, 0, 0);
return SCPE_OK;

10
Intel-Systems/common/ipc-cont.c
View file

@ -70,14 +70,12 @@ DEBTAB ipc_cont_debug[] = {
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "XACK", DEBUG_xack },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ NULL }
};
MTAB ipc_cont_mod[] = {
{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, ipc_cont_show_param, NULL,
"show configured parametes for ipc_cont" },
"show configured parameters for ipc_cont" },
{ 0 }
};
@ -112,9 +110,9 @@ DEVICE ipc_cont_dev = {
t_stat ipc_cont_cfg(uint16 base, uint16 devnum, uint8 dummy)
{
sim_printf(" ipc-cont: at port 0%02XH\n",
base & 0xFF);
ipc_cont_baseport = base & 0xff;
sim_printf(" ipc-cont: installed at base port 0%02XH\n",
base & BYTEMASK);
ipc_cont_baseport = base & BYTEMASK;
reg_dev(ipc_cont, base, 0, 0);
return SCPE_OK;
}

8
Intel-Systems/common/iram8.c
View file

@ -70,7 +70,7 @@ MTAB RAM_mod[] = {
{ MTAB_XTD | MTAB_VDV, 0, NULL, "SIZE", &RAM_set_size,
NULL, NULL, "Sets the size for RAM"},
{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, RAM_show_param, NULL,
"show configured parametes for RAM" },
"show configured parameters for RAM" },
{ 0 }
};
@ -80,8 +80,6 @@ DEBTAB RAM_debug[] = {
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "XACK", DEBUG_xack },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ NULL }
};
@ -212,14 +210,14 @@ uint8 RAM_get_mbyte(uint16 addr)
uint8 val;
val = *((uint8 *)RAM_unit.filebuf + (addr - RAM_unit.u3));
return (val & 0xFF);
return (val & BYTEMASK);
}
/* put a byte into memory */
void RAM_put_mbyte(uint16 addr, uint8 val)
{
*((uint8 *)RAM_unit.filebuf + (addr - RAM_unit.u3)) = val & 0xFF;
*((uint8 *)RAM_unit.filebuf + (addr - RAM_unit.u3)) = val & BYTEMASK;
return;
}

5
Intel-Systems/common/irq.c
View file

@ -78,8 +78,7 @@ DEBTAB irq_debug[] = {
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ "XACK", DEBUG_xack },
{ NULL }
};
@ -119,7 +118,7 @@ DEVICE irq_dev = {
t_stat irq_reset(DEVICE *dptr)
{
// if (SBC_reset(NULL) == 0) {
sim_printf(" Interrupt: Reset\n");
// sim_printf(" Interrupt: Reset\n");
sim_activate (&irq_unit, irq_unit.wait); /* activate unit */
return SCPE_OK;
// } else {

19
Intel-Systems/common/isbc064.c
View file

@ -37,8 +37,6 @@
#include "system_defs.h"
#define BASE_ADDR u3
#define isbc064_NAME "Intel iSBC 064 RAM Board"
/* prototypes */
@ -107,8 +105,6 @@ DEBTAB isbc064_debug[] = {
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "XACK", DEBUG_xack },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ NULL }
};
@ -155,7 +151,7 @@ t_stat isbc064_cfg(uint16 base, uint16 size, uint8 dummy)
return SCPE_MEM;
}
sim_printf(" SBC064: Enabled 0%04XH bytes at base 0%04XH\n",
isbc064_dev.units->capac, isbc064_dev.units->BASE_ADDR);
isbc064_dev.units->capac, isbc064_dev.units->u3);
return SCPE_OK;
}
@ -205,8 +201,8 @@ t_stat isbc064_set_base(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
sim_printf("SBC064: Base error\n");
return SCPE_ARG;
} else {
isbc064_unit.BASE_ADDR = size * 1024;
sim_printf("SBC064: Base=%04XH\n", isbc064_unit.BASE_ADDR);
isbc064_unit.u3 = size * 1024;
sim_printf("SBC064: Base=%04XH\n", isbc064_unit.u3);
return SCPE_OK;
}
}
@ -219,7 +215,7 @@ t_stat isbc064_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
{
fprintf(st, "Device %s, Base address=0%04XH, Size=0%04XH ",
((isbc064_dev.flags & DEV_DIS) == 0) ? "Enabled" : "Disabled",
isbc064_unit.BASE_ADDR, isbc064_unit.capac);
isbc064_unit.u3, isbc064_unit.capac);
return SCPE_OK;
}
@ -229,6 +225,7 @@ t_stat isbc064_reset (DEVICE *dptr)
{
if (dptr == NULL)
return SCPE_ARG;
isbc064_unit.u3 = 0; //BASE=0
return SCPE_OK;
}
@ -238,15 +235,15 @@ uint8 isbc064_get_mbyte(uint16 addr)
{
uint8 val;
val = *((uint8 *)isbc064_unit.filebuf + (addr - isbc064_unit.BASE_ADDR));
return (val & 0xFF);
val = *((uint8 *)isbc064_unit.filebuf + (addr - isbc064_unit.u3));
return (val & BYTEMASK);
}
/* put a byte into memory */
void isbc064_put_mbyte(uint16 addr, uint8 val)
{
*((uint8 *)isbc064_unit.filebuf + (addr - isbc064_unit.BASE_ADDR)) = val & 0xFF;
*((uint8 *)isbc064_unit.filebuf + (addr - isbc064_unit.u3)) = val & BYTEMASK;
return;
}

10
Intel-Systems/common/isbc201.c
View file

@ -290,7 +290,7 @@ MTAB isbc201_mod[] = {
{ MTAB_XTD | MTAB_VDV, 0, NULL, "INT", &isbc201_set_int,
NULL, NULL, "Sets the interrupt number for iSBC201"},
{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, &isbc201_show_param, NULL,
"show configured parametes for iSBC201" },
"show configured parameters for iSBC201" },
{ 0 }
};
@ -300,8 +300,6 @@ DEBTAB isbc201_debug[] = {
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "XACK", DEBUG_xack },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ NULL }
};
@ -349,7 +347,7 @@ t_stat isbc201_cfg(uint16 baseport, uint16 devnum, uint8 intnum)
uptr->u6 = i; //fdd unit number
uptr->flags &= ~UNIT_ATT;
}
fdc201.baseport = baseport & 0xff; //set port
fdc201.baseport = baseport & BYTEMASK; //set port
fdc201.intnum = intnum; //set interrupt
fdc201.verb = 0; //clear verb
reg_dev(isbc201r0, fdc201.baseport, 0, 0); //read status
@ -392,11 +390,11 @@ t_stat isbc201_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
if (val & UNIT_WPMODE) { /* write protect */
uptr->flags |= val;
if (fdc201.verb)
sim_printf(" sbc201: WP\n");
sim_printf(" sbc201%d: WP\n", uptr->u6);
} else { /* read write */
uptr->flags &= ~val;
if (fdc201.verb)
sim_printf(" sbc201: RW\n");
sim_printf(" sbc201%d: RW\n", uptr->u6);
}
return SCPE_OK;
}

27
Intel-Systems/common/isbc202.c
View file

@ -284,7 +284,7 @@ MTAB isbc202_mod[] = {
{ MTAB_XTD | MTAB_VDV, 0, NULL, "INT", &isbc202_set_int,
NULL, NULL, "Sets the interrupt number for iSBC202"},
{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, &isbc202_show_param, NULL,
"show configured parametes for iSBC202" },
"show configured parameters for iSBC202" },
{ 0 }
};
@ -294,8 +294,6 @@ DEBTAB isbc202_debug[] = {
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "XACK", DEBUG_xack },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ NULL }
};
@ -343,14 +341,14 @@ t_stat isbc202_cfg(uint16 baseport, uint16 devnum, uint8 intnum)
uptr->u6 = i; //fdd unit number
uptr->flags &= ~UNIT_ATT;
}
fdc202.baseport = baseport & 0xff; //set port
fdc202.baseport = baseport & BYTEMASK; //set port
fdc202.intnum = intnum; //set interrupt
fdc202.verb = 0; //clear verb
reg_dev(isbc202r0, fdc202.baseport, 0, 0); //read status
reg_dev(isbc202r1, fdc202.baseport + 1, 0, 0); //read rslt type/write IOPB addr-l
reg_dev(isbc202r2, fdc202.baseport + 2, 0, 0); //write IOPB addr-h and start
reg_dev(isbc202r3, fdc202.baseport + 3, 0, 0); //read rstl byte
reg_dev(isbc202r7, fdc202.baseport + 7, 0, 0); //write reset fdc201
reg_dev(isbc202r7, fdc202.baseport + 7, 0, 0); //write reset fdc202
isbc202_reset_dev(); //software reset
// if (fdc202.verb)
sim_printf(" sbc202: Enabled base port at 0%02XH, Interrupt #=%02X, %s\n",
@ -366,7 +364,7 @@ t_stat isbc202_clr(void)
unreg_dev(fdc202.baseport + 1); //read rslt type/write IOPB addr-l
unreg_dev(fdc202.baseport + 2); //write IOPB addr-h and start
unreg_dev(fdc202.baseport + 3); //read rstl byte
unreg_dev(fdc202.baseport + 7); //write reset fdc201
unreg_dev(fdc202.baseport + 7); //write reset fdc202
// if (fdc202.verb)
sim_printf(" sbc202: Disabled\n");
return SCPE_OK;
@ -374,7 +372,7 @@ t_stat isbc202_clr(void)
/* isbc202 set mode = Write protect */
t_stat isbc202_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
t_stat isbc202_set_mode(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
{
if (uptr == NULL)
return SCPE_ARG;
@ -384,11 +382,11 @@ t_stat isbc202_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
if (val & UNIT_WPMODE) { /* write protect */
uptr->flags |= val;
// if (fdc202.verb)
sim_printf(" SBC202: WP\n");
sim_printf(" SBC202%d: WP\n", uptr->u6);
} else { /* read write */
uptr->flags &= ~val;
// if (fdc202.verb)
sim_printf(" SBC202: RW\n");
sim_printf(" SBC202%d: RW\n", uptr->u6);
}
return SCPE_OK;
}
@ -409,7 +407,7 @@ t_stat isbc202_set_port(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
reg_dev(isbc202r1, fdc202.baseport + 1, 0, 0); //read rslt type/write IOPB addr-l
reg_dev(isbc202r2, fdc202.baseport + 2, 0, 0); //write IOPB addr-h and start
reg_dev(isbc202r3, fdc202.baseport + 3, 0, 0); //read rstl byte
reg_dev(isbc202r7, fdc202.baseport + 7, 0, 0); //write reset fdc201
reg_dev(isbc202r7, fdc202.baseport + 7, 0, 0); //write reset fdc202
return SCPE_OK;
}
@ -549,7 +547,7 @@ t_stat isbc202_attach (UNIT *uptr, CONST char *cptr)
uint8 isbc202r0(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read ststus*/
return fdc202.stat;
return fdc202.stat;
}
return 0;
}
@ -631,14 +629,17 @@ void isbc202_diskio(void)
fddnum = (di & 0x30) >> 4;
uptr = isbc202_dev.units + fddnum;
fbuf = (uint8 *) uptr->filebuf;
//check for not ready
switch(fddnum) {
if (fdc202.verb)
sim_printf("\n SBC202: FDD %d - nr=%02XH ta=%02XH sa=%02XH IOPB=%04XH PCX=%04XH",
fddnum, nr, ta, sa, fdc202.iopb, PCX);
switch(fddnum) { //check ready status
case 0:
if ((fdc202.stat & RDY0) == 0) {
fdc202.rtype = ROK;
fdc202.rbyte0 = RB0NR;
fdc202.intff = 1; //set interrupt FF
sim_printf("\n SBC202: FDD %d - Ready error", fddnum);
return;
}
break;
case 1:

15
Intel-Systems/common/isbc206.c
View file

@ -262,7 +262,7 @@ MTAB isbc206_mod[] = {
{ MTAB_XTD | MTAB_VDV, 0, NULL, "INT", &isbc206_set_int,
NULL, NULL, "Sets the interrupt number for iSBC206"},
{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, &isbc206_show_param, NULL,
"show configured parametes for iSBC206" },
"show configured parameters for iSBC206" },
{ 0 }
};
@ -272,8 +272,6 @@ DEBTAB isbc206_debug[] = {
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "XACK", DEBUG_xack },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ NULL }
};
@ -320,7 +318,7 @@ t_stat isbc206_cfg(uint16 baseport, uint16 devnum, uint8 intnum)
uptr = isbc206_dev.units + i;
uptr->u6 = i; //fdd unit number
}
hdc206.baseport = baseport & 0xff; //set port
hdc206.baseport = baseport & BYTEMASK; //set port
hdc206.intnum = intnum; //set interrupt
hdc206.verb = 0; //clear verb
reg_dev(isbc206r0, hdc206.baseport, 0, 0); //read status
@ -381,8 +379,13 @@ t_stat isbc206_set_port(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
return SCPE_ARG;
result = sscanf(cptr, "%02x", &size);
hdc206.baseport = size;
if (hdc206.verb)
// if (hdc206.verb)
sim_printf("SBC206: Base port=%04X\n", hdc206.baseport);
reg_dev(isbc206r0, hdc206.baseport, 0, 0); //read status
reg_dev(isbc206r1, hdc206.baseport + 1, 0, 0); //read rslt type/write IOPB addr-l
reg_dev(isbc206r2, hdc206.baseport + 2, 0, 0); //write IOPB addr-h and start
reg_dev(isbc206r3, hdc206.baseport + 3, 0, 0); //read rstl byte
reg_dev(isbc206r7, hdc206.baseport + 7, 0, 0); //write reset fdc202
return SCPE_OK;
}
@ -396,7 +399,7 @@ t_stat isbc206_set_int(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
return SCPE_ARG;
result = sscanf(cptr, "%02x", &size);
hdc206.intnum = size;
if (hdc206.verb)
// if (hdc206.verb)
sim_printf("SBC206: Interrupt number=%04X\n", hdc206.intnum);
return SCPE_OK;
}

54
Intel-Systems/common/isbc208.c
View file

@ -471,6 +471,8 @@
#define isbc208_NAME "Intel iSBC 208 Floppy Disk Controller Board"
#define SBC208_INT INT_1
/* internal function prototypes */
t_stat isbc208_cfg(uint16 baseport, uint16 size, uint8 devnum);
@ -647,9 +649,7 @@ DEBTAB isbc208_debug[] = {
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ "REG", DEBUG_reg },
{ "XACK", DEBUG_xack },
{ NULL }
};
@ -860,8 +860,8 @@ t_stat isbc208_svc (UNIT *uptr)
ssize = 128 << secn; // size of sector (bytes)
bpt = ssize * spt; // bytes/track
bpc = bpt * 2; // bytes/cylinder
// sim_printf("208 Read: FDD=%d h=%d s=%d t=%d n=%d secsiz=%d spt=%d PCX=%04X\n",
// drv, h, sec, cyl, secn, ssize, spt, PCX);
sim_printf("208 Read: FDD=%d h=%d s=%d t=%d n=%d secsiz=%d spt=%d PCX=%04X\n",
drv, h, sec, cyl, secn, ssize, spt, PCX);
if ((fddst[uptr->u6] & RDY) == 0) { // drive not ready
i8272_r0 = IC_ABNORM | NR | hed | drv; /* command done - Not ready error*/
i8272_r3 = fddst[uptr->u6];
@ -933,7 +933,7 @@ t_stat isbc208_svc (UNIT *uptr)
/*
fp = fopen(uptr->filename, "wb"); // write out modified image
for (i=0; i<uptr->capac; i++) {
c = *(isbc208_buf[uptr->u6] + i) & 0xFF;
c = *(isbc208_buf[uptr->u6] + i) & BYTEMASK;
fputc(c, fp);
}
fclose(fp);
@ -1192,7 +1192,7 @@ uint8 isbc208_r0(t_bool io, uint8 data, uint8 devnum)
return (i8237_r0 >> 8);
} else { /* low byte */
i8237_rD++;
return (i8237_r0 & 0xFF);
return (i8237_r0 & BYTEMASK);
}
} else { /* write baseport & current address CH 0 */
if (i8237_rD) { /* high byte */
@ -1200,7 +1200,7 @@ uint8 isbc208_r0(t_bool io, uint8 data, uint8 devnum)
i8237_r0 |= (data << 8);
} else { /* low byte */
i8237_rD++;
i8237_r0 = data & 0xFF;
i8237_r0 = data & BYTEMASK;
}
return 0;
}
@ -1214,7 +1214,7 @@ uint8 isbc208_r1(t_bool io, uint8 data, uint8 devnum)
return (i8237_r1 >> 8);
} else { /* low byte */
i8237_rD++;
return (i8237_r1 & 0xFF);
return (i8237_r1 & BYTEMASK);
}
} else { /* write baseport & current address CH 0 */
if (i8237_rD) { /* high byte */
@ -1222,7 +1222,7 @@ uint8 isbc208_r1(t_bool io, uint8 data, uint8 devnum)
i8237_r1 |= (data << 8);
} else { /* low byte */
i8237_rD++;
i8237_r1 = data & 0xFF;
i8237_r1 = data & BYTEMASK;
}
return 0;
}
@ -1236,7 +1236,7 @@ uint8 isbc208_r2(t_bool io, uint8 data, uint8 devnum)
return (i8237_r2 >> 8);
} else { /* low byte */
i8237_rD++;
return (i8237_r2 & 0xFF);
return (i8237_r2 & BYTEMASK);
}
} else { /* write baseport & current address CH 1 */
if (i8237_rD) { /* high byte */
@ -1244,7 +1244,7 @@ uint8 isbc208_r2(t_bool io, uint8 data, uint8 devnum)
i8237_r2 |= (data << 8);
} else { /* low byte */
i8237_rD++;
i8237_r2 = data & 0xFF;
i8237_r2 = data & BYTEMASK;
}
return 0;
}
@ -1258,7 +1258,7 @@ uint8 isbc208_r3(t_bool io, uint8 data, uint8 devnum)
return (i8237_r3 >> 8);
} else { /* low byte */
i8237_rD++;
return (i8237_r3 & 0xFF);
return (i8237_r3 & BYTEMASK);
}
} else { /* write baseport & current address CH 1 */
if (i8237_rD) { /* high byte */
@ -1266,7 +1266,7 @@ uint8 isbc208_r3(t_bool io, uint8 data, uint8 devnum)
i8237_r3 |= (data << 8);
} else { /* low byte */
i8237_rD++;
i8237_r3 = data & 0xFF;
i8237_r3 = data & BYTEMASK;
}
return 0;
}
@ -1280,7 +1280,7 @@ uint8 isbc208_r4(t_bool io, uint8 data, uint8 devnum)
return (i8237_r4 >> 8);
} else { /* low byte */
i8237_rD++;
return (i8237_r4 & 0xFF);
return (i8237_r4 & BYTEMASK);
}
} else { /* write baseport & current address CH 2 */
if (i8237_rD) { /* high byte */
@ -1288,7 +1288,7 @@ uint8 isbc208_r4(t_bool io, uint8 data, uint8 devnum)
i8237_r4 |= (data << 8);
} else { /* low byte */
i8237_rD++;
i8237_r4 = data & 0xFF;
i8237_r4 = data & BYTEMASK;
}
return 0;
}
@ -1302,7 +1302,7 @@ uint8 isbc208_r5(t_bool io, uint8 data, uint8 devnum)
return (i8237_r5 >> 8);
} else { /* low byte */
i8237_rD++;
return (i8237_r5 & 0xFF);
return (i8237_r5 & BYTEMASK);
}
} else { /* write baseport & current address CH 2 */
if (i8237_rD) { /* high byte */
@ -1310,7 +1310,7 @@ uint8 isbc208_r5(t_bool io, uint8 data, uint8 devnum)
i8237_r5 |= (data << 8);
} else { /* low byte */
i8237_rD++;
i8237_r5 = data & 0xFF;
i8237_r5 = data & BYTEMASK;
}
return 0;
}
@ -1324,7 +1324,7 @@ uint8 isbc208_r6(t_bool io, uint8 data, uint8 devnum)
return (i8237_r6 >> 8);
} else { /* low byte */
i8237_rD++;
return (i8237_r6 & 0xFF);
return (i8237_r6 & BYTEMASK);
}
} else { /* write baseport & current address CH 3 */
if (i8237_rD) { /* high byte */
@ -1332,7 +1332,7 @@ uint8 isbc208_r6(t_bool io, uint8 data, uint8 devnum)
i8237_r6 |= (data << 8);
} else { /* low byte */
i8237_rD++;
i8237_r6 = data & 0xFF;
i8237_r6 = data & BYTEMASK;
}
return 0;
}
@ -1346,7 +1346,7 @@ uint8 isbc208_r7(t_bool io, uint8 data, uint8 devnum)
return (i8237_r7 >> 8);
} else { /* low byte */
i8237_rD++;
return (i8237_r7 & 0xFF);
return (i8237_r7 & BYTEMASK);
}
} else { /* write baseport & current address CH 3 */
if (i8237_rD) { /* high byte */
@ -1354,7 +1354,7 @@ uint8 isbc208_r7(t_bool io, uint8 data, uint8 devnum)
i8237_r7 |= (data << 8);
} else { /* low byte */
i8237_rD++;
i8237_r7 = data & 0xFF;
i8237_r7 = data & BYTEMASK;
}
return 0;
}
@ -1365,7 +1365,7 @@ uint8 isbc208_r8(t_bool io, uint8 data, uint8 devnum)
if (io == 0) { /* read status register */
return (i8237_r8);
} else { /* write command register */
i8237_r9 = data & 0xFF;
i8237_r9 = data & BYTEMASK;
return 0;
}
}
@ -1375,7 +1375,7 @@ uint8 isbc208_r9(t_bool io, uint8 data, uint8 devnum)
if (io == 0) {
return 0;
} else { /* write request register */
i8237_rC = data & 0xFF;
i8237_rC = data & BYTEMASK;
return 0;
}
}
@ -1420,7 +1420,7 @@ uint8 isbc208_rB(t_bool io, uint8 data, uint8 devnum)
if (io == 0) {
return 0;
} else { /* write mode register */
i8237_rA = data & 0xFF;
i8237_rA = data & BYTEMASK;
return 0;
}
}
@ -1480,7 +1480,7 @@ uint8 isbc208_r12(t_bool io, uint8 data, uint8 devnum)
if (io == 0) { /* read interrupt status */
return (isbc208_i);
} else { /* write controller auxillary port */
isbc208_a = data & 0xFF;
isbc208_a = data & BYTEMASK;
return 0;
}
}
@ -1500,7 +1500,7 @@ uint8 isbc208_r14(t_bool io, uint8 data, uint8 devnum)
if (io == 0) {
return 0;
} else { /* Low-Byte Segment Address Register */
isbc208_sr = data & 0xFF;
isbc208_sr = data & BYTEMASK;
return 0;
}
}

12
Intel-Systems/common/isbc464.c
View file

@ -76,7 +76,7 @@ MTAB isbc464_mod[] = {
{ MTAB_XTD | MTAB_VDV, 0, NULL, "BASE", &isbc464_set_base,
NULL, NULL, "Sets the ROM base for iSBC464" },
{ MTAB_XTD|MTAB_VDV, 0, "PARAM", NULL, NULL, &isbc464_show_param, NULL,
"Parameter" },
"show configured parameters for SBC 464" },
{ 0 }
};
@ -86,8 +86,6 @@ DEBTAB isbc464_debug[] = {
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "XACK", DEBUG_xack },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ NULL }
};
@ -231,8 +229,8 @@ t_stat isbc464_reset (DEVICE *dptr)
if (dptr == NULL)
return SCPE_ARG;
if (isbc464_onetime) {
isbc464_dev.units->capac = SBC464_SIZE; //set default size
isbc464_dev.units->BASE_ADDR = SBC464_BASE; //set default base
// isbc464_dev.units->capac = SBC464_SIZE; //set default size
// isbc464_dev.units->BASE_ADDR = SBC464_BASE; //set default base
isbc464_onetime = 0;
}
if ((dptr->flags & DEV_DIS) == 0) { //already enabled
@ -246,7 +244,7 @@ t_stat isbc464_reset (DEVICE *dptr)
} else { //disabled
if (isbc464_dev.units->filebuf)
free(isbc464_dev.units->filebuf); //return allocated memory
sim_printf(" sbc464: Disabled\n");
// sim_printf(" sbc464: Disabled\n");
}
return SCPE_OK;
}
@ -272,7 +270,7 @@ uint8 isbc464_get_mbyte(uint16 addr)
uint8 val;
val = *((uint8 *)isbc464_unit.filebuf + (addr - isbc464_unit.BASE_ADDR));
return (val & 0xFF);
return (val & BYTEMASK);
}
/* end of isbc464.c */

27
Intel-Systems/common/mem.c
View file

@ -56,7 +56,8 @@ extern uint8 xack; /* XACK signal */
extern UNIT i8255_unit; //for isbc memory control
extern UNIT ipc_cont_unit;
extern UNIT ioc_cont_unit;
extern uint8 i8255_C[4]; //port C byte I/O
extern uint8 i8255_C[4]; //port C byte I/O
/* get a byte from memory - handle MODEL, RAM, ROM and Multibus memory */
@ -65,7 +66,7 @@ uint8 get_mbyte(uint16 addr)
uint8 val;
SET_XACK(0); /* clear xack */
if ((mem_map <= 1) && (addr >= 0xF800)) { //monitor ROM - always there IPB/IPC
if ((mem_map <= 1) && (addr >= 0xF800)) { //monitor ROM - always there IPB/IPC/800
SET_XACK(1); //set xack
return EPROM_get_mbyte(addr - 0xF000, 0); //top half of EPROM
}
@ -86,10 +87,16 @@ uint8 get_mbyte(uint16 addr)
return RAM_get_mbyte(addr);
}
if (mem_map == 2) { //800
if (((monitor_boot & 0x04) == 0) && (addr >= EPROM_unit[0].u3) && (addr <= (EPROM_unit[0].u3 + EPROM_unit[0].capac)))
return EPROM_get_mbyte(addr, 0);
else if ((addr >= EPROM_unit[1].u3) && (addr <= (EPROM_unit[1].u3 + EPROM_unit[1].capac)))
SET_XACK(1); //set xack
if ((addr >= EPROM_unit[0].u3) && (addr <= (EPROM_unit[0].u3 + EPROM_unit[0].capac))) {
if ((monitor_boot & 0x02) == 0)
return EPROM_get_mbyte(addr, 0);
else
return multibus_get_mbyte(addr);
}
if ((addr >= EPROM_unit[1].u3) && (addr <= (EPROM_unit[1].u3 + EPROM_unit[1].capac))) {
return EPROM_get_mbyte(addr, 1);
}
}
if (mem_map == 3) { //isdk80
if ((addr >= EPROM_unit->u3) && ((uint16)addr <= (EPROM_unit->u3 + EPROM_unit->capac))) {
@ -133,14 +140,18 @@ uint16 get_mword(uint16 addr)
void put_mbyte(uint16 addr, uint8 val)
{
SET_XACK(0); /* set no XACK */
if (addr >= 0xF800) { //monitor ROM - always there IPB/IPC/800
/* put a byte to memory - handle RAM, ROM, I/O, and pcbus memory */
SET_XACK(0); /* clear xack */
if ((mem_map <= 1) && (addr >= 0xF800)) { //monitor ROM - always there IPB/IPC/800
SET_XACK(1); //set xack
return; //do nothing
}
if ((mem_map <= 1) && (addr < 0x1000) && ((ipc_cont_unit.u3 & 0x04) == 0)) { //startup IPB/IPC
SET_XACK(1); //set xack
return; //do nothing
}
if ((mem_map <= 1) && (addr >= 0xE800) && (addr < 0xF000) && ((ipc_cont_unit.u3 & 0x10) == 0)) { //diagnostic ROM IPB/IPC
SET_XACK(1); //set xack
return; //do nothing
}
if (mem_map == 1) { //IPC RAM
@ -186,7 +197,7 @@ void put_mbyte(uint16 addr, uint8 val)
void put_mword(uint16 addr, uint16 val)
{
put_mbyte(addr, val & 0xff);
put_mbyte(addr, val & BYTEMASK);
put_mbyte(addr+1, val >> 8);
}

18
Intel-Systems/common/multibus.c
View file

@ -34,7 +34,6 @@
#include "system_defs.h"
#define BASE_ADDR u3
#define multibus_NAME "Intel Multibus Interface"
/* function prototypes */
@ -81,8 +80,7 @@ DEBTAB multibus_debug[] = {
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ "XACK", DEBUG_xack },
{ NULL }
};
@ -122,7 +120,7 @@ DEVICE multibus_dev = {
t_stat multibus_reset(DEVICE *dptr)
{
// if (SBC_reset(NULL) == 0) {
sim_printf(" Multibus: Reset\n");
// sim_printf(" Multibus: Reset\n");
sim_activate (&multibus_unit, multibus_unit.wait); /* activate unit */
return SCPE_OK;
// } else {
@ -145,15 +143,15 @@ uint8 multibus_get_mbyte(uint16 addr)
{
SET_XACK(0); /* set no XACK */
if ((isbc464_dev.flags & DEV_DIS) == 0) { //ROM is enabled
if (addr >= isbc464_dev.units->BASE_ADDR &&
addr < (isbc464_dev.units->BASE_ADDR + isbc464_dev.units->capac)) {
if (addr >= isbc464_dev.units->u3 &&
addr < (isbc464_dev.units->u3 + isbc464_dev.units->capac)) {
SET_XACK(1); //set xack
return(isbc464_get_mbyte(addr));
}
}
if ((isbc064_dev.flags & DEV_DIS) == 0) { //iSBC 064 is enabled
if (addr >= isbc064_dev.units->BASE_ADDR &&
addr < (isbc064_dev.units->BASE_ADDR + isbc064_dev.units->capac)) {
if (addr >= isbc064_dev.units->u3 &&
addr < (isbc064_dev.units->u3 + isbc064_dev.units->capac)) {
SET_XACK(1); //set xack
return (isbc064_get_mbyte(addr));
}
@ -165,8 +163,8 @@ void multibus_put_mbyte(uint16 addr, uint8 val)
{
SET_XACK(0); /* set no XACK */
if ((isbc064_dev.flags & DEV_DIS) == 0) { //device is enabled
if (addr >= isbc064_dev.units->BASE_ADDR &&
addr < (isbc064_dev.units->BASE_ADDR + isbc064_dev.units->capac)) {
if (addr >= isbc064_dev.units->u3 &&
addr < (isbc064_dev.units->u3 + isbc064_dev.units->capac)) {
SET_XACK(1); //set xack
isbc064_put_mbyte(addr, val);
}

5
Intel-Systems/common/port.c
View file

@ -74,8 +74,7 @@ DEBTAB port_debug[] = {
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ "XACK", DEBUG_xack },
{ NULL }
};
@ -115,7 +114,7 @@ DEVICE port_dev = {
t_stat port_reset(DEVICE *dptr)
{
// if (SBC_reset(NULL) == 0) {
sim_printf(" Port: Reset\n");
// sim_printf(" Port: Reset\n");
sim_activate (&port_unit, port_unit.wait); /* activate unit */
return SCPE_OK;
// } else {

168
Intel-Systems/common/sys.c
View file

@ -76,6 +76,10 @@
#define SYS_80204 11
#define SYS_8024 12
#define SYS_8030 13
#define SYS_8010_0 14
#define SYS_8010_1 15
#define SYS_8010_2 16
#define SYS_8010_3 17
#define sys_name "Intel MDS Configuration Controller"
@ -107,6 +111,9 @@ extern t_stat EPROM_cfg(uint16 base, uint16 size, uint8 devnum);
extern t_stat RAM_cfg(uint16 base, uint16 size, uint8 dummy);
extern t_stat isbc064_cfg(uint16 base, uint16 size, uint8 dummy);
extern t_stat isbc464_cfg(uint16 base, uint16 size, uint8 dummy);
extern t_stat isbc201_cfg(uint16 base, uint16 size, uint8 dummy);
extern t_stat isbc202_cfg(uint16 base, uint16 size, uint8 dummy);
extern t_stat isbc208_cfg(uint16 base, uint16 size, uint8 dummy);
extern t_stat i3214_clr(void);
extern t_stat i8251_clr(void);
extern t_stat i8253_clr(void);
@ -118,12 +125,15 @@ extern t_stat EPROM_clr(void);
extern t_stat RAM_clr(void);
extern t_stat isbc064_clr(void);
extern t_stat isbc464_clr(void);
extern t_stat isbc201_clr(void);
extern t_stat isbc202_clr(void);
extern t_stat isbc208_clr(void);
extern void clr_dev(void);
/* globals */
int model = -1; //force no model
int mem_map = 0; //memory model
int mem_map = 0; //memory model
typedef struct device {
int id;
@ -142,123 +152,154 @@ typedef struct system_model {
SYS_DEV devices[30];
} SYS_MODEL;
#define SYS_NUM 15
#define SYS_NUM 18
SYS_MODEL models[SYS_NUM+1] = {
{MDS_210, "MDS-210 ", 9,
// id name num arg routine routine1 val1 val2 val3
{{ i8251, "I8251", 2, 1, i8251_cfg, i8251_clr, 0xF4, 0xF6 },
{ i8253, "I8253", 1, 1, i8253_cfg, i8253_clr, 0xF0 },
{{ IOC_CONT, "IOC-CONT", 1, 1, ioc_cont_cfg, ioc_cont_clr, 0xC0 },
{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
{ i8253, "I8253", 1, 1, i8253_cfg, i8253_clr, 0xF0 },
{ i8251, "I8251", 2, 1, i8251_cfg, i8251_clr, 0xF4, 0xF6 },
{ i8259, "I8259", 2, 1, i8259_cfg, i8259_clr, 0xFA, 0xFC },
{ IOC_CONT, "IOC-CONT", 1, 1, ioc_cont_cfg, ioc_cont_clr, 0xC0 },
{ IPC_CONT, "IPC-CONT", 1, 1, ipc_cont_cfg, ipc_cont_clr, 0xFF },
{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x0FFF },
{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x0000, 0x7FFF },
{ SBC464, "SBC464", 1, 2, isbc464_cfg, isbc464_clr, 0xA800, 0x47FF }},
},
{MDS_220, "MDS-220 ", 8,
{{ i8251, "I8251", 2, 1, i8251_cfg, i8251_clr, 0xF4, 0xF6 },
{ i8253, "I8253", 1, 1, i8253_cfg, i8253_clr, 0xF0 },
{{ IOC_CONT, "IOC-CONT", 1, 1, ioc_cont_cfg, ioc_cont_clr, 0xC0 },
{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
{ i8253, "I8253", 1, 1, i8253_cfg, i8253_clr, 0xF0 },
{ i8251, "I8251", 2, 1, i8251_cfg, i8251_clr, 0xF4, 0xF6 },
{ i8259, "I8259", 2, 1, i8259_cfg, i8259_clr, 0xFA, 0xFC },
{ IOC_CONT, "IOC-CONT", 1, 1, ioc_cont_cfg, ioc_cont_clr, 0xC0 },
{ IPC_CONT, "IPC-CONT", 1, 1, ipc_cont_cfg, ipc_cont_clr, 0xFF },
{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x0FFF },
{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x0000, 0x7FFF }}
},
{MDS_225, "MDS-225 ", 8,
{{ i8251, "I8251", 2, 1, i8251_cfg, i8251_clr, 0xF4, 0xF6 },
{ i8253, "I8253", 1, 1, i8253_cfg, i8253_clr, 0xF0 },
{{ IOC_CONT, "IOC-CONT", 1, 1, ioc_cont_cfg, ioc_cont_clr, 0xC0 },
{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
{ i8253, "I8253", 1, 1, i8253_cfg, i8253_clr, 0xF0 },
{ i8251, "I8251", 2, 1, i8251_cfg, i8251_clr, 0xF4, 0xF6 },
{ i8259, "I8259", 2, 1, i8259_cfg, i8259_clr, 0xFA, 0xFC },
{ IOC_CONT, "IOC-CONT", 1, 1, ioc_cont_cfg, ioc_cont_clr, 0xC0 },
{ IPC_CONT, "IPC-CONT", 1, 1, ipc_cont_cfg, ipc_cont_clr, 0xFF },
{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x0FFF },
{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x0000, 0xFFFF }},
},
{MDS_230, "MDS-230 ", 9,
{{ i8251, "I8251", 2, 1, i8251_cfg, i8251_clr, 0xF4, 0xF6 },
{ i8253, "I8253", 1, 1, i8253_cfg, i8253_clr, 0xF0 },
{{ IOC_CONT, "IOC-CONT", 1, 1, ioc_cont_cfg, ioc_cont_clr, 0xC0 },
{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
{ i8253, "I8253", 1, 1, i8253_cfg, i8253_clr, 0xF0 },
{ i8251, "I8251", 2, 1, i8251_cfg, i8251_clr, 0xF4, 0xF6 },
{ i8259, "I8259", 2, 1, i8259_cfg, i8259_clr, 0xFA, 0xFC },
{ IOC_CONT, "IOC-CONT", 1, 1, ioc_cont_cfg, ioc_cont_clr, 0xC0 },
{ IPC_CONT, "IPC-CONT", 1, 1, ipc_cont_cfg, ipc_cont_clr, 0xFF },
{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x0FFF },
{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x0000, 0x7FFF },
{ SBC064, "SBC064", 1, 2, isbc064_cfg, isbc064_clr, 0x8000, 0x7FFF }},
},
{MDS_800, "MDS-800 ", 5,
{{ i3214, "I3214", 1, 1, i3214_cfg, i3214_clr, 0xFC },
{ i8251, "I8251", 2, 1, i8251_cfg, i8251_clr, 0xF4, 0xF6 },
{{ i8251, "I8251", 2, 1, i8251_cfg, i8251_clr, 0xF4, 0xF6 },
{ i3214, "I3214", 1, 1, i3214_cfg, i3214_clr, 0xFC },
{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x00FF },
{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0xF800, 0x07FF },
{ SBC064, "SBC064", 1, 2, isbc064_cfg, isbc064_clr, 0x0000, 0x7FFF }},
{ SBC064, "SBC064", 1, 2, isbc064_cfg, isbc064_clr, 0x0000, 0xFFFF }},
},
{MDS_810, "MDS-810 ", 6,
{{ i3214, "I3214", 1, 1, i3214_cfg, i3214_clr, 0xFC },
{ i8251, "I8251", 2, 1, i8251_cfg, i8251_clr, 0xF4, 0xF6 },
{{ i8251, "I8251", 2, 1, i8251_cfg, i8251_clr, 0xF4, 0xF6 },
{ i3214, "I3214", 1, 1, i3214_cfg, i3214_clr, 0xFC },
{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x00FF },
{ EPROM, "EPROM2", 1, 2, EPROM_cfg, EPROM_clr, 0xF800, 0x07FF },
{ SBC064, "SBC064", 1, 2, isbc064_cfg, isbc064_clr, 0x0000, 0x7FFF },
{ SBC464, "SBC464", 1, 2, isbc464_cfg, isbc464_clr, 0xA800, 0x47FF }},
},
{SDK_80, "SDK-80 ", 4,
{{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xFA },
{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xF4, 0xEC },
{{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xEC, 0xF4 },
{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xFA },
{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x0FFF },
{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x1000, 0x03FF }},
},
{SYS_8010, "SYS-80/10 ", 4,
{{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
{{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x0FFF },
{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x3c00, 0x03FF }},
},
{SYS_8010A, "SYS-80/10A ", 4,
{{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
{{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x1FFF },
{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x3c00, 0x03FF }},
},
{SYS_8010B, "SYS-80/10B ", 4,
{{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x3FFF },
{{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x1FFF },
{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x3c00, 0x03FF }},
},
{SYS_8020, "SYS-80/20 ", 6,
{{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
{{ i8259, "I8259", 1, 1, i8259_cfg, i8259_clr, 0xDA },
{ i8253, "I8253", 1, 1, i8253_cfg, i8253_clr, 0xDC },
{ i8255, "I8255", 1, 1, i8255_cfg, i8255_clr, 0xE8 },
{ i8259, "I8259", 1, 1, i8259_cfg, i8259_clr, 0xDA },
{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x1FFF },
{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x3800, 0x07FF }},
},
{SYS_8020-4, "SYS-80/20-4", 6,
{{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
{SYS_80204, "SYS-80/20-4 ", 6,
{{ i8259, "I8259", 1, 1, i8259_cfg, i8259_clr, 0xDA },
{ i8253, "I8253", 1, 1, i8253_cfg, i8253_clr, 0xDC },
{ i8255, "I8255", 1, 1, i8255_cfg, i8255_clr, 0xE8 },
{ i8259, "I8259", 1, 1, i8259_cfg, i8259_clr, 0xDA },
{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x1FFF },
{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x3000, 0x0FFF }},
},
{SYS_8024, "SYS-80/24 ", 6,
{{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
{{ i8259, "I8259", 1, 1, i8259_cfg, i8259_clr, 0xDA },
{ i8253, "I8253", 1, 1, i8253_cfg, i8253_clr, 0xDC },
{ i8255, "I8255", 1, 1, i8255_cfg, i8255_clr, 0xE8 },
{ i8259, "I8259", 1, 1, i8259_cfg, i8259_clr, 0xDA },
{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE8 },
{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x1FFF },
{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x3c00, 0x03FF }},
},
{SYS_8030, "SYS-80/30 ", 6,
{{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
{{ i8259, "I8259", 1, 1, i8259_cfg, i8259_clr, 0xDA },
{ i8253, "I8253", 1, 1, i8253_cfg, i8253_clr, 0xDC },
{ i8255, "I8255", 1, 1, i8255_cfg, i8255_clr, 0xE8 },
{ i8259, "I8259", 1, 1, i8259_cfg, i8259_clr, 0xDA },
{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE8 },
{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x1FFF },
{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x2000, 0x3FFF }},
},
{SYS_8010_0, "SYS-80/10-0", 5,
{{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x0FFF },
{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x3c00, 0x03FF },
{ SBC064, "SBC064", 1, 2, isbc064_cfg, isbc064_clr, 0x0000, 0xFFFF }},
},
{SYS_8010_1, "SYS-80/10-1", 6,
{{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x0FFF },
{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x3c00, 0x03FF },
{ SBC064, "SBC064", 1, 2, isbc064_cfg, isbc064_clr, 0x0000, 0xFFFF },
{ SBC201, "SBC201", 1, 1, isbc201_cfg, isbc201_clr, 0x78 }},
},
{SYS_8010_2, "SYS-80/10-2", 6,
{{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x0FFF },
{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x3c00, 0x03FF },
{ SBC064, "SBC064", 1, 2, isbc064_cfg, isbc064_clr, 0x0000, 0xFFFF },
{ SBC202, "SBC202", 1, 1, isbc202_cfg, isbc202_clr, 0x78 }},
},
{SYS_8010_3, "SYS-80/10-3 ", 6,
{{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x0FFF },
{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x3c00, 0x03FF },
{ SBC064, "SBC064", 1, 2, isbc064_cfg, isbc064_clr, 0x0000, 0xFFFF },
{ SBC208, "SBC208", 1, 1, isbc208_cfg, isbc208_clr, 0x40 }},
},
{0}
};
@ -282,8 +323,6 @@ DEBTAB sys_debug[] = {
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "XACK", DEBUG_xack },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ NULL }
};
@ -328,7 +367,7 @@ t_stat sys_cfg(uint16 base, uint16 devnum, uint8 dummy)
DEVICE *dptr;
if (model == (-1)) return SCPE_ARG; //no valid config
sim_printf("sys_cfg: Configure %s:\n", models[model].name);
sim_printf("sys_cfg: Configuring an %s:\n", models[model].name);
switch (model) { //set memory map type
case 0: //mds-210
mem_map = 0; //ipb
@ -372,6 +411,18 @@ t_stat sys_cfg(uint16 base, uint16 devnum, uint8 dummy)
case 13: //sys-8030
mem_map = 4; //sys-8030
break;
case 14: //sys-8010-0
mem_map = 4; //sys-8010-0
break;
case 15: //sys-8010-1
mem_map = 4; //sys-8010-1
break;
case 16: //sys-8010-2
mem_map = 4; //sys-8010-2
break;
case 17: //sys-8010-3
mem_map = 4; //sys-8010-3
break;
default:
return SCPE_ARG;
}
@ -391,13 +442,14 @@ t_stat sys_cfg(uint16 base, uint16 devnum, uint8 dummy)
break;
case 3: //three arguments
models[model].devices[i].cfg_routine (models[model].devices[i].val[j],
models[model].devices[i].val[j+1], models[model].devices[i].val[j+1] & 0xff);
models[model].devices[i].val[j+1], models[model].devices[i].val[j+1] & BYTEMASK);
break;
default:
return SCPE_ARG;
}
}
}
//reset_all (0);
return SCPE_OK;
}
@ -428,7 +480,7 @@ t_stat sys_reset(DEVICE *dptr)
{
if (dptr == NULL)
return SCPE_ARG;
sim_printf("SYS Reset\n");
// sim_printf("SYS Reset\n");
sys_cfg(0, 0, 0);
return SCPE_OK;
}
@ -447,7 +499,7 @@ t_stat sys_set_model (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
if (!strncmp(cptr, models[i].name, strlen(cptr))) { //find the system
model = models[i].id;
strncpy(sim_name, models[i].name, 11);
printf("sys_set_model: Configuring %s\n", sim_name);
printf("sys_set_model: Configuring an %s\n", sim_name);
switch (model) { //set memory map type
case 0: //mds-210
mem_map = 0; //ipb
@ -491,6 +543,18 @@ t_stat sys_set_model (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
case 13: //sys-8030
mem_map = 4; //sys-8030
break;
case 14: //sys-8010-0
mem_map = 4; //sys-8010-0
break;
case 15: //sys-8010-1
mem_map = 4; //sys-8010-1
break;
case 16: //sys-8010-2
mem_map = 4; //sys-8010-2
break;
case 17: //sys-8010-3
mem_map = 4; //sys-8010-3
break;
default:
return SCPE_ARG;
}
@ -510,13 +574,14 @@ t_stat sys_set_model (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
break;
case 3: //three arguments
models[model].devices[i].cfg_routine (models[model].devices[i].val[j],
models[model].devices[i].val[j+1], models[model].devices[i].val[j+1] & 0xff);
models[model].devices[i].val[j+1], models[model].devices[i].val[j+1] & BYTEMASK);
break;
default:
return SCPE_ARG;
}
}
}
reset_all (0);
return SCPE_OK;
}
}
@ -530,12 +595,11 @@ t_stat sys_show_model (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
if (uptr == NULL)
return SCPE_ARG;
return SCPE_OK;
fprintf(st, "%s: %d\n", models[model].name, models[model].num);
fprintf(st, "%s:%d devices\n", models[model].name, models[model].num);
for (i=0; i<models[model].num; i++) {
fprintf(st, " %s:", models[model].devices[i].name);
fprintf(st, " %d", models[model].devices[i].num);
fprintf(st, " %d", models[model].devices[i].args);
fprintf(st, " %d devices", models[model].devices[i].num);
fprintf(st, " %d args", models[model].devices[i].args);
for (j=0; j<models[model].devices[i].num; j++) {
if (models[model].devices[i].args == 2)
fprintf(st, " 0%04XH 0%04XH", models[model].devices[i].val[j],

86
Intel-Systems/common/zx200a.c
View file

@ -266,8 +266,8 @@ UNIT zx200a_unit[] = {
};
REG zx200a_reg[] = {
{ HRDATA (STAT0, zx200a.SDstat, 8) }, /* zx200a 0 SD status */
{ HRDATA (STAT0, zx200a.DDstat, 8) }, /* zx200a 0 DD status */
{ HRDATA (SSTAT0, zx200a.SDstat, 8) }, /* zx200a 0 SD status */
{ HRDATA (DSTAT0, zx200a.DDstat, 8) }, /* zx200a 0 DD status */
{ HRDATA (RTYP0, zx200a.rtype, 8) }, /* zx200a 0 result type */
{ HRDATA (RBYT0A, zx200a.rbyte0, 8) }, /* zx200a 0 result byte 0 */
{ HRDATA (RBYT0B, zx200a.rbyte1, 8) }, /* zx200a 0 result byte 1 */
@ -286,7 +286,7 @@ MTAB zx200a_mod[] = {
{ MTAB_XTD | MTAB_VDV, 0, NULL, "INT", &zx200a_set_int,
NULL, NULL, "Sets the interrupt number for ZX-200A"},
{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, &zx200a_show_param, NULL,
"show configured parametes for ZX-200A" },
"show configured parameters for ZX-200A" },
{ 0 }
};
@ -296,8 +296,6 @@ DEBTAB zx200a_debug[] = {
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "XACK", DEBUG_xack },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ NULL }
};
@ -332,6 +330,8 @@ DEVICE zx200a_dev = {
&zx200a_desc //device description
};
/* Service routines to handle simulator functions */
/* zx200a set mode = Write protect */
t_stat zx200a_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
@ -352,8 +352,6 @@ t_stat zx200a_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
return SCPE_OK;
}
/* Service routines to handle simulator functions */
// set base address parameter
t_stat zx200a_set_port(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
@ -364,8 +362,21 @@ t_stat zx200a_set_port(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
return SCPE_ARG;
result = sscanf(cptr, "%02x", &size);
zx200a.baseport = size;
if (zx200a.verb)
sim_printf("ZX200A: Base port=%04X\n", zx200a.baseport);
// if (zx200a.verb)
sim_printf("ZX200A: Installed at base port=%04X\n", zx200a.baseport);
reg_dev(zx200ar0DD, zx200a.baseport, 0, 0); //read status
reg_dev(zx200ar1DD, zx200a.baseport + 1, 0, 0); //read rslt type/write IOPB addr-l
reg_dev(zx200ar2DD, zx200a.baseport + 2, 0, 0); //write IOPB addr-h and start
reg_dev(zx200ar3, zx200a.baseport + 3, 0, 0); //read rstl byte
reg_dev(zx200ar7, zx200a.baseport + 7, 0, 0); //write reset fdc202
reg_dev(zx200ar0SD, zx200a.baseport, 0, 0); //read status
reg_dev(zx200ar1SD, zx200a.baseport + 1, 0, 0); //read rslt type/write IOPB addr-l
reg_dev(zx200ar2SD, zx200a.baseport + 2, 0, 0); //write IOPB addr-h and start
reg_dev(zx200ar3, zx200a.baseport + 3, 0, 0); //read rstl byte
reg_dev(zx200ar7, zx200a.baseport + 7, 0, 0); //write reset fdc202
// if (zx200a.verb)
sim_printf(" ZX200A: Enabled base port at 0%02XH Interrupt #=%02X %s\n",
zx200a.baseport, zx200a.intnum, zx200a.verb ? "Verbose" : "Quiet" );
return SCPE_OK;
}
@ -379,7 +390,7 @@ t_stat zx200a_set_int(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
return SCPE_ARG;
result = sscanf(cptr, "%02x", &size);
zx200a.intnum = size;
if (zx200a.verb)
// if (zx200a.verb)
sim_printf("ZX200A: Interrupt number=%04X\n", zx200a.intnum);
return SCPE_OK;
}
@ -430,8 +441,8 @@ t_stat zx200a_reset(DEVICE *dptr)
if (dptr == NULL)
return SCPE_ARG;
if (zx200a_onetime) {
zx200a.baseport = ZX200A_BASE; //set default base
zx200a.intnum = ZX200A_INT; //set default interrupt
// zx200a.baseport = ZX200A_BASE; //set default base
// zx200a.intnum = ZX200A_INT; //set default interrupt
zx200a.verb = 0; //set verb = 0
zx200a_onetime = 0;
// one-time initialization for all FDDs for this FDC instance
@ -445,7 +456,7 @@ t_stat zx200a_reset(DEVICE *dptr)
reg_dev(zx200ar0DD, zx200a.baseport + 1, 0, 0); //read rslt type/write IOPB addr-l
reg_dev(zx200ar0DD, zx200a.baseport + 2, 0, 0); //write IOPB addr-h and start
reg_dev(zx200ar3, zx200a.baseport + 3, 0, 0); //read rstl byte
reg_dev(zx200ar7, zx200a.baseport + 7, 0, 0); //write reset fdc201
reg_dev(zx200ar7, zx200a.baseport + 7, 0, 0); //write reset zx200a
reg_dev(zx200ar0SD, zx200a.baseport + 16, 0, 0); //read status
reg_dev(zx200ar1SD, zx200a.baseport + 17, 0, 0); //read rslt type/write IOPB addr-l
reg_dev(zx200ar2SD, zx200a.baseport + 18, 0, 0); //write IOPB addr-h and start
@ -466,7 +477,7 @@ t_stat zx200a_reset(DEVICE *dptr)
unreg_dev(zx200a.baseport + 18); //write IOPB addr-h and start
unreg_dev(zx200a.baseport + 19); //read rstl byte
unreg_dev(zx200a.baseport + 23); //write reset fdc201
// if (zx200a.verb)
if (zx200a.verb)
sim_printf(" ZX200A: Disabled\n");
}
return SCPE_OK;
@ -594,8 +605,7 @@ uint8 zx200ar1SD(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read operation */
zx200a.intff = 0; //clear interrupt FF
if (zx200a.intff)
zx200a.SDstat &= ~FDCINT;
zx200a.SDstat &= ~FDCINT;
zx200a.rtype = ROK;
return zx200a.rtype;
} else { /* write control port */
@ -608,8 +618,7 @@ uint8 zx200ar1DD(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read operation */
zx200a.intff = 0; //clear interrupt FF
if (zx200a.intff)
zx200a.DDstat &= ~FDCINT;
zx200a.DDstat &= ~FDCINT;
zx200a.rtype = ROK;
return zx200a.rtype;
} else { /* write control port */
@ -620,9 +629,9 @@ uint8 zx200ar1DD(t_bool io, uint8 data, uint8 devnum)
uint8 zx200ar2SD(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read data port */
if (io == 0) { /* read data port */
;
} else { /* write data port */
} else { /* write data port */
zx200a.iopb |= (data << 8);
zx200a_diskio();
if (zx200a.intff)
@ -633,9 +642,9 @@ uint8 zx200ar2SD(t_bool io, uint8 data, uint8 devnum)
uint8 zx200ar2DD(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read data port */
if (io == 0) { /* read data port */
;
} else { /* write data port */
} else { /* write data port */
zx200a.iopb |= (data << 8);
zx200a_diskio();
if (zx200a.intff)
@ -646,8 +655,8 @@ uint8 zx200ar2DD(t_bool io, uint8 data, uint8 devnum)
uint8 zx200ar3(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read data port */
if (zx200a.rtype == 0) {
if (io == 0) { /* read data port */
if (zx200a.rtype == ROK) {
return zx200a.rbyte0;
} else {
if (zx200a.rdychg) {
@ -656,7 +665,7 @@ uint8 zx200ar3(t_bool io, uint8 data, uint8 devnum)
return zx200a.rbyte0;
}
}
} else { /* write data port */
} else { /* write data port */
; //stop diskette operation
}
return 0;
@ -665,9 +674,9 @@ uint8 zx200ar3(t_bool io, uint8 data, uint8 devnum)
/* reset ZX-200A */
uint8 zx200ar7(t_bool io, uint8 data, uint8 devnum)
{
if (io == 0) { /* read data port */
if (io == 0) { /* read data port */
;
} else { /* write data port */
} else { /* write data port */
zx200a_reset_dev();
}
return 0;
@ -696,13 +705,16 @@ void zx200a_diskio(void)
fddnum = (di & 0x30) >> 4;
uptr = zx200a_dev.units + fddnum;
fbuf = (uint8 *) uptr->filebuf;
if (zx200a.verb)
sim_printf("\n zx200a: FDD %d - nr=%02XH ta=%02XH sa=%02XH IOPB=%04XH PCX=%04XH",
fddnum, nr, ta, sa, zx200a.iopb, PCX);
//check for not ready
switch(fddnum) {
case 0:
if ((zx200a.DDstat & RDY0) == 0) {
zx200a.rtype = ROK;
zx200a.rbyte0 = RB0NR;
zx200a.intff = 1; //set interrupt FF
zx200a.intff = 1; //set interrupt FF
sim_printf("\n zx200a: Ready error on drive %d", fddnum);
return;
}
@ -711,7 +723,7 @@ void zx200a_diskio(void)
if ((zx200a.DDstat & RDY1) == 0) {
zx200a.rtype = ROK;
zx200a.rbyte0 = RB0NR;
zx200a.intff = 1; //set interrupt FF
zx200a.intff = 1; //set interrupt FF
sim_printf("\n zx200a: Ready error on drive %d", fddnum);
return;
}
@ -720,7 +732,7 @@ void zx200a_diskio(void)
if ((zx200a.DDstat & RDY2) == 0) {
zx200a.rtype = ROK;
zx200a.rbyte0 = RB0NR;
zx200a.intff = 1; //set interrupt FF
zx200a.intff = 1; //set interrupt FF
sim_printf("\n zx200a: Ready error on drive %d", fddnum);
return;
}
@ -729,7 +741,7 @@ void zx200a_diskio(void)
if ((zx200a.DDstat & RDY3) == 0) {
zx200a.rtype = ROK;
zx200a.rbyte0 = RB0NR;
zx200a.intff = 1; //set interrupt FF
zx200a.intff = 1; //set interrupt FF
sim_printf("\n zx200a: Ready error on drive %d", fddnum);
return;
}
@ -738,7 +750,7 @@ void zx200a_diskio(void)
if ((zx200a.SDstat & RDY0) == 0) {
zx200a.rtype = ROK;
zx200a.rbyte0 = RB0NR;
zx200a.intff = 1; //set interrupt FF
zx200a.intff = 1; //set interrupt FF
sim_printf("\n zx200a: Ready error on drive %d", fddnum);
return;
}
@ -747,7 +759,7 @@ void zx200a_diskio(void)
if ((zx200a.SDstat & RDY1) == 0) {
zx200a.rtype = ROK;
zx200a.rbyte0 = RB0NR;
zx200a.intff = 1; //set interrupt FF
zx200a.intff = 1; //set interrupt FF
sim_printf("\n zx200a: Ready error on drive %d", fddnum);
return;
}
@ -764,7 +776,7 @@ void zx200a_diskio(void)
)) {
zx200a.rtype = ROK;
zx200a.rbyte0 = RB0ADR;
zx200a.intff = 1; //set interrupt FF
zx200a.intff = 1; //set interrupt FF
sim_printf("\n ZX200A: FDD %d - Address error sa=%02X nr=%02X ta=%02X PCX=%04X",
fddnum, sa, nr, ta, PCX);
return;
@ -779,7 +791,7 @@ void zx200a_diskio(void)
)) {
zx200a.rtype = ROK;
zx200a.rbyte0 = RB0ADR;
zx200a.intff = 1; //set interrupt FF
zx200a.intff = 1; //set interrupt FF
sim_printf("\n ZX200A: FDD %d - Address error sa=%02X nr=%02X ta=%02X PCX=%04X",
fddnum, sa, nr, ta, PCX);
return;
@ -815,11 +827,11 @@ void zx200a_diskio(void)
if(uptr->flags & UNIT_WPMODE) {
zx200a.rtype = ROK;
zx200a.rbyte0 = RB0WP;
zx200a.intff = 1; //set interrupt FF
zx200a.intff = 1; //set interrupt FF
sim_printf("\n zx200a: Write protect error 1 on drive %d", fddnum);
return;
}
fmtb = get_mbyte(ba); //get the format byte
fmtb = get_mbyte(ba); //get the format byte
if (zx200a.fdd[fddnum].dd == 1) {
//calculate offset into DD disk image
dskoff = ((ta * MAXSECDD) + (sa - 1)) * 128;

4
Visual Studio Projects/Intel-MDS.vcproj
View file

@ -95,6 +95,8 @@
/>
<Tool
Name="VCPostBuildEventTool"
Description="Running Available Tests"
CommandLine="Post-Build-Event.cmd Intel-Systems &quot;$(TargetDir)$(TargetName).exe&quot;"
/>
</Configuration>
<Configuration
@ -184,6 +186,8 @@
/>
<Tool
Name="VCPostBuildEventTool"
Description="Running Available Tests"
CommandLine="Post-Build-Event.cmd Intel-Systems &quot;$(TargetDir)$(TargetName).exe&quot;"
/>
</Configuration>
</Configurations>