Previously sim_interval was adjusted by 1 plus the total number of bytes
referenced in string instructions (SCANC, SPANC, LOCC, SKPC, CMPC3,
CMPC5, MOVC3, MOVC5). Since the amount of data that a string
instruction can reference is arbitrarily large (32bit size), the adjustment
to sim_interval could be ridiculously excessive. This can result in wild
variances in clock calibration when large string data are referenced.
- Upgrade BESM6 from experimental to be included in the 'make all'
- Add imds-225 to make all
- The cdc1700 simulator is currently the only experimental simulator
This will support arbitrary location and naming of the simh submodule in the
parent repo's working directory.
It probably won't work for sub sub modules. Suggestions welcome.
a) Added sim_debug statements, formatted console messages.
b) Removed old debugging statements and redundant byte/word mask operations.
c) Added more device commands.
d) Added zx-200a and changed nulldev to return 0 vice 0xff.
e) Added commands and corrected RTYPE and RBYTE behavior so ISIS-II would boot.
f) Corrected device calls in SBC_reset, corrected get_mbyte and put_mbyte to
match control bits from ipc_cont.c.
Previously, disk capacity was increased if the drive was smaller than the
contained file system(s). Now the drive capacity will be increased or
decreased to reflect the contained file system(s) size.
The BuildROMs project now runs the BuildROMs program that was most
recently built (Debug or Release). This will identify ROM data inconsistencies
that may exist at build time.
When building other projects which may depend on ROM data, the BuildROMs
is run as a sanity check and if it fails we make sure that we hadn't run an out
of date Release build version of the BuildROMs binary.
The console mode needs to be set to properly interpret and generate ANSI
escape sequences. It is not 100% VT100 compatible, but this is MUCH better
than without any support.
Various boot ROM activities, including testing the Interval Timers, presume
that ROM based code execute instructions at 1 instruction per usec.
To accommodate this, we not only throttle memory accesses to ROM space,
but we also use instruction based delays when the interval timers are
programmed from the ROM for short duration delays.
- Add support to query remaining usecs on pending events.
- Generalized the sim_interval adjustment in sim_idle to allow more than
a single decrement.
- More overhead reduction when idling.
- Carry usec values as double through out to fully support long wall clock
delays.
The original idling model called sim_idle() within the context of a scheduled
event running on the CPU unit. The overhead of scheduling and the related
dispatch serve no specific purpose.
Meanwhile, the 'work' involved in determing if idling is possible is about
equivalent to the work of executing an additional instruction. Therefore
sim_idle is invoked with an argument which causes the sim_interval to be
adjusted by 1 on each call that doesn't actually perform an idle sleep. This
adjustment keeps the calibrated instruction execution rate consistent with
other purely non-idle instruction mixes.
Clock ticks for these simulatrs are performed by programmatic setup of the
interval timer device (TMR) and have nothing to do with the TODR which
increments at 100Hz, but doesn't generate ticks to the simulated system.
Windows 10 finally supports ANSI escape sequences in console applications.
Simulators may output appropriate sequences and get useful results, however,
timing of the bytes in the output stream to the console device matters.
This change buffers the data in escape sequences for up to 8ms or until another
escape sequence is presented for output. Once the 8ms elapses, then all output
characters are presented to the windows console subsystem together so they
can be properly interpreted.
