80 commits

Author	SHA1	Message	Date
Folkert van Heusden	c3545a2f2a	TRAP handling	2025-04-07 07:27:50 +02:00
Folkert van Heusden	9eee7acc94	16b fixes	2025-04-06 23:00:16 +02:00
Folkert van Heusden	15b397aed7	also intercept PWriteB	2025-04-06 22:10:48 +02:00
Folkert van Heusden	6089dedd9d	prevent double entries in mem-write table	2025-04-06 19:53:35 +02:00
Folkert van Heusden	7ea9e4442b	keep track of memory writes	2025-04-06 19:40:07 +02:00
Folkert van Heusden	e409fad0c5	Allow TRAPs to be executed when requested.	2025-04-06 19:07:33 +02:00
Folkert van Heusden	3671049405	Generate testset using simh	2025-04-03 08:50:59 +02:00
Bob Supnik	86a995b863	PDP11: numerous 11/70 compatibility fixes	2023-01-31 13:06:04 -05:00
Lars Brinkhoff	4daf07bfe2	PDP11: Add option for 216K memory. ... The Small ITS timesharing system prefers this amount.	2022-10-14 10:53:42 +02:00
Paul Koning	253b8ec358	PDP11: Fix PC breakpoint check ... Don't modify the CPU state when checking for physical address match on PC address breakpoints. Reported and verified by Lars.	2022-10-10 13:38:09 -04:00
Mark Pizzolato	93e86f31f0	PDP11: Fix Coverity identified issue in HELP CPU	2022-03-10 17:07:11 -08:00
Mark Pizzolato	c808256e87	PDP11: Fix model indexes after model table previously got reordered ... As reported in #1073	2021-08-24 10:47:01 -07:00
Mark Pizzolato	efc79d710a	PDP11: Update 11/40 and 11/45 models to reflect MMU was an option	2021-08-15 12:13:20 -07:00
Mark Pizzolato	3bf02304da	PDP11: Populate remaining internal device help from pdp11_doc.doc	2021-08-14 23:21:31 -07:00
Mark Pizzolato	4b03e1493a	PDP11: Fix typo in cpu_boot routine	2021-06-08 13:12:01 -07:00
Mark Pizzolato	4ce23275e0	PDP11: Add default CPU BOOT to ROM if ROM is enabled and reasonably configured	2021-05-30 15:51:15 -07:00
Mark Pizzolato	5c48229ce4	Qbus & Unibus VAX: Add a SHOW QBA|UBA MAP{=n} command to display the bus map	2020-08-29 08:16:58 -07:00
Mark Pizzolato	f75f28aa21	TIMER: Add mechanism to pre-calibrate the instruction execution rate	2019-05-28 23:56:58 -07:00
Paul Koning	096f9dbd71	PDP11: Fix PSW handling for breakpoints and other aborts ... Fixes #701. The issue is more general than just breakpoints, it potentially affects any exception dealt with by the ABORT macro.	2019-05-15 20:14:33 -04:00
Mark Pizzolato	a95a835b98	PDP11: Fix typo in formatting instruction history including the SP	2019-04-16 15:55:54 -07:00
Bob Supnik	cdfb7c0878	PDP11: Add SP to instruction history	2019-04-15 22:01:08 -07:00
Lars Brinkhoff	d01cd826b3	PDP11: Allow setting core size to 8K, 24K, 40K, and 56K.	2018-07-28 20:47:09 -07:00
Mark Pizzolato	6b361a9faf	PDP11, PDP15, UC15: Merge simh v3.10 functionality from Supnik-Current branch	2018-06-04 10:43:00 -07:00
Mike Hill	4c746682f1	PDP11: Correct the address of MMR3 in a comment	2017-03-03 05:01:03 +01:00
Mark Pizzolato	50ee02a2c7	PDP11: Fix psw_mode map in PSW register bitfield	2017-02-09 09:59:45 -08:00
Paul Koning	998cf5c122	PDP11: Add initial UC15 support from Bob Supnik	2017-02-04 12:19:41 -08:00
Mark Pizzolato	cf1e7b9cca	SCP, PDP11: Added HELP CPU BREAK to display info about breakpoint types	2016-10-06 13:25:54 -07:00
Paul Koning	89ffed467f	PDP11: Add new breakpoint types for data and physical address ... Add support for physical and virtual address variants for the existing instruction (PC) breakpoint, and add memory read and memory write breakpoints.	2016-09-13 15:22:35 -04:00
Mark Pizzolato	8eb36720bc	PDP11: Fix ambiguous -D decimal vs data space reference - Add -T for data	2016-08-30 13:10:56 -07:00
Mark Pizzolato	0352e0fd7b	PDP11: Move history entry pointer initialization out of instruction loop. ... This will be slightly more efficient for the normal case where history isn't being recorded.	2016-08-25 14:28:38 -07:00
Paul Koning	66fb70b768	PDP11: Record the actual source and destination values for history. ... Previously, the history would always use a register value as source or destination as if the mode were zero, even when it wasn't. Also, now the destination value reflects the destination after instruction execution rather than before.	2016-08-25 14:28:38 -07:00
Mark Pizzolato	e2a8f0fcdc	PDP11: Fixed NEXT command to work when the MMU is enabled	2016-08-24 21:19:09 -07:00
Mark Pizzolato	5531ccb175	ALL: Massive 'const' cleanup ... These changes facilitate more robust parameter type checking and helps to identify unexpected coding errors. Most simulators can now also be compiled with a C++ compiler without warnings. Additionally, these changes have also been configured to facilitate easier backporting of simulator and device simulation modules to run under the simh v3.9+ SCP framework.	2016-05-15 15:25:33 -07:00
Mark Pizzolato	71e745b0c8	PDP11: Fixed bug in history virtual addressing (Bob Supnik) ... The problem has to do with the difference in how the PSW is stored when the simulator is running (it's all in pieces) or stopped (it's collected in PSW). cpu_ex is a console routine and expects the PSW to be stored in PSW, but when history is collected, it's not. In particular, cm (current mode) is in local variable cm. cpu_ex with /v calls relocC, which derives the current mode from the switches: - if /ksup, use kernel/supervisor/user/previous mode (from PSW); otherwise, use current mode from PSW - if /d, use data space; otherwise, use instruction space relocC is doing current mode i-space, which is what's wanted... except that it's deriving current mode from PSW, rather than cm, which is where it's stored while the simulator is running. It's fairly likely that PSW is long obsolete by the time the history is invoked.	2016-03-06 06:27:15 -08:00
Mark Pizzolato	e054a78398	PDP11: Add descriptions to register names and bitfields to the PSW register.	2016-01-18 07:02:06 -08:00
Mark Pizzolato	6582aeead2	SCP. PDP11: Add ESC and ENQ to the default set of console output characters in 7P mode. ... Revert change to add ESC and ENQ to printable characters for all simulators and make that change only for the PDP11.	2016-01-02 05:07:18 -08:00
Mark Pizzolato	59947e8ceb	PDP11: Addition of option to disable BEVENT for 11/03 and 11/23 CPUs (Bob Supnik's latest state).	2015-12-30 12:01:58 -08:00
Mark Pizzolato	ac837e5be2	PDP11: Add auto configure and build_dib_tab to cpu_reset. ... The mapping of addresses in the I/O page needs to be populated before it can be referenced. This change allows commands at the initial sim> prompt to touch device registers with EXAMINE and DEPOSIT as discussed in #261	2015-12-29 10:11:39 -08:00
Mark Pizzolato	7256e0908c	PDP11: Simplified idle call logic to leave the idle decision to sim_idle(). ... Removed the unused references to wait_enable which the comments suggest was related to an old style idle.	2014-12-19 08:45:47 -08:00
Mark Pizzolato	235ce92ff2	PDP11: Correct proper boot support for PDP11 devices when booting via a Remote Console Master session	2014-10-28 10:19:39 -07:00
Mark Pizzolato	178116c978	PDP11: Added proper boot support for PDP11 devices when booting via a Remote Console Master session	2014-10-28 10:06:30 -07:00
Mark Pizzolato	c548b34772	Compiler suggested cleanups.	2014-10-27 17:14:28 -07:00
Mark Pizzolato	611a7e94f0	SCP: Added a Remote Console Master Mode. ... This capability will allow a GDB RSB stub to be created to support dynamic debugging of code running in a simulator. This capability will also allow a complete front panel emulation system to operate a simulator. This capability is engaged in a simulator by: sim> set remote telnet=remoteconsoleport# sim> set console telnet=consoleport# sim> set remote master Master mode will provide a TCP session which accepts SCP commands that allow full control of the simulator.	2014-10-26 15:15:31 -07:00
Mark Pizzolato	3256c10c77	General cleanup migrate to using sim_printf vs separate calls to printf and fprintf(sim_log).	2014-10-22 17:12:14 -07:00
Mark Pizzolato	3946eb710e	VAX, PDP11, PDP10: Added a explanation of the capabilities and limitations of the NEXT command which is output the first time a NEXT command is entered. ... Also added CHMK, CHME, CHMS and CHMU to the set of instructions which are considered subroutine call initiators in the VAX simulator.	2014-04-19 05:45:29 -07:00
Mark Pizzolato	e7a934904c	PDP11: Added support for the NEXT command to step over subroutine calls.	2014-04-17 13:07:37 -07:00
Mark Pizzolato	2daa41ecb3	PDP11: Fixed bug in CSM (John Dundas) ... John Dundas said: Bob and all, I ran across what I believe to be a bug in the CSM code: case 070: /* CSM */ if (CPUT (HAS_CSM) && (MMR3 & MMR3_CSM) || (cm != MD_KER)) { According to the Architecture Handbook, CSM may be executed only if the MMR3 bit is set AND the mode is not Kernel. Changing the code to: case 070: /* CSM */ if (CPUT (HAS_CSM) && (MMR3 & MMR3_CSM) && (cm != MD_KER)) { also has the effect of making the ZKDKB0 diagnostic much happier. Thanks, John -- John A. Dundas III	2013-12-06 10:54:56 -08:00
Mark Pizzolato	3519c6c74b	PDP11: Added support for PC values to be displayed in debug output. ... This required a simulator specific implementation since the PDP11 PC register isn't stored in a normal memory location. It is loaded from a temporary location upon simulator instruction execution startup (and saved to that location when instuction execution stops). In order to reference the PC value while executing instructions (for debug output), this extended access model is required.	2013-11-17 08:55:29 -08:00
Mark Pizzolato	f0d41f15d7	PDP11: Fix to correctly set PS value on CPU reset to reflect the model specific ways real hardware behaved. (from Bob Supnik) ... Here's a PDP11 SIMH bug as old as the simulator itself: the reset_cpu routine sets the PS to 340 (interrupts disabled). This causes some versions of Lunar Lander not to work. In fact, the initial state of the PS is not architecturally standardized: 04: cleared (from schematics) 05: cleared (from manual) 20: cleared (from schematics) 34: cleared (from schematics), set to 340 on boot? 40: cleared (from schematics) 44: cleared on init, set to 340 on boot (from schematics, manual) 45: cleared (from schematics) 60: cleared (from schematics) 70: cleared (from schematics) T11: set to 340 (from spec) LSI11, F11: 4 mode behavior (from memory on power recovery, cleared on GO, 340 on boot, mode 3 undefined) J11: 4 mode behavior (from memory on power recovery, cleared on GO, 340 on boot, 340 on jump to custom PROM) The story seems to be this. All non-VLSI PDP11s used TTL chips to implement the PS, either discrete flip-flops, or 4b registers, or both. Starting with the first system, the 11/20, they were wired clear on the processor INIT signal (power-up or front panel START switch), so that all internal state started as 0. This worked fine, because START also reset the Unibus and cleared all interrupt enables. So even though the processor was as IPL = 0, no interrupts were possible. Then along came the LSI11... The LSI11 implemented a line-time clock with NO INTERRUPT DISABLE. Thus, if IPL was left at 0 and a bootstrap routine from a slow device was started (e.g., a floppy drive), the clock would tick, and an interrupt would occur, before the bootstrap routine finished. Because no vectors were set up, the processor would crash. So the LSI11 started the practice, carried over to all later PDP11 VLSI chips, of setting the PS to 340 before jumping to a boot ROM. The T11 did this in all modes of startup, because its only startup behavior was to jump to a "boot" routine. It did not have a console of any kind. Accordingly, it appears that the cpu_reset routine needs to set the PS based on the processor model. Further, all boot routines need to set the PS to 0 or 340 based on the processor model. (It's probably safe for boot routines just to set the PS to 340, but it's not technically accurate.)	2013-10-27 05:30:13 -07:00
Mark Pizzolato	4064cc079a	This fixes the problem that MMR1 is recording changes to R7 (PC), which it should not. (issue #44) ... It does not fix the problem that MMR1 is not used for floating point instructions. I don't know if I will fix the FP MMR1 problem. It does not seem to impact running software. It is consistent with the architecture spec - just not with the actual J11 implementation. The J11 microcode has a variety of exception exits for FP conditions, and I have to trace which ones invoke fix-up, and which do not.	2013-06-02 06:52:32 -07:00