The 3B2 emulator did not have support for traps, rendering debugging
under the simulator fairly useless. This change adds support for
trap handling. The 'sdb' UNIX debugger under SVR3 should now work
correctly.
Two critical issues are fixed with this commit:
1. The MMU cache was being corrupted by writing the 'Last Used'
bit into the wrong half of the PD cache (low word vs. high word)
2. The MMU cache was being too aggressively flushed on SRAMA
write, because the wrong length was being used. In addition,
the code was walking off the end of the cache array when
flushing any section other than section 0, potentially causing
memory corruption.
This commit improves the integrated disk (ID) controller's behavior,
enabling full support for up to two 72MB (emulated WREN II)
integrated winchester disks.
Clock reset was not being handled gracefully at all, leading some
diagnostic tests not to pass, or not to pass consistently.
This change will "kick" the system clock whenever the timer divider is
reset, so the new divider is picked up immediately.
