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Author SHA1 Message Date
Richard Cornwell
7acb4554bb KA10: Removed PACK definition, add polling if async eth fails. 2020-03-12 00:10:15 -04:00
Mark Pizzolato
b3214fcb59 ETHER: Emit advice when asynch operation is attempted without USE_READER_THREAD 2020-03-10 19:53:25 -07:00
Mark Pizzolato
77edf89ef5 SCP: Add macro's to support packed structures for network traffic 2020-03-10 11:26:23 -07:00
Mark Pizzolato
c30c88c24f Visual Studio Projects: Fix PDP10-KL to link against the proper libraries 2020-03-10 00:18:19 -07:00
Mark Pizzolato
e949197fb7 Visual Studio Projects: Build the PDP10-KL simulator with pthreads enabled 2020-03-09 23:58:07 -07:00
Mark Pizzolato
09896679bb SCP: Add SHOW DO to display the DO file nesting state 2020-03-09 23:38:48 -07:00
Author: Richard Cornwell
c686f75894 KA10: Added support for KL10A/B. 2020-03-09 23:07:47 -07:00
Richard Cornwell
c7d529c4db DISPLAY: Added III display device. 2020-03-09 20:25:55 -04:00
Mark Pizzolato
42411b2e18 Visual Studio Projects: Fix ECLIPSE project to actually build the ECLIPSE 2020-03-08 21:42:48 -07:00
Mark Pizzolato
550837b15b TIMER: Prefer a stable calibrated clock which ticks slower than the host 2020-03-08 21:11:30 -07:00
Mark Pizzolato
036e3bb933 SCP: Fix Coverity generated warnings 2020-03-08 18:44:33 -07:00
Mark Pizzolato
0170b7c6ab SCP: Convert more SHOW and debug output to use sim_vm_interval_units 2020-03-08 11:43:30 -07:00
Mark Pizzolato
b2272c8cd6 SCP: Add ability to "DO <stdin>" 
This allows a running script to nest a procedure call get input from
stdin and return to the running script (or executing simulator).
 2020-03-08 09:52:41 -07:00
Mark Pizzolato
aa72b1e0ab Visual Studio Projects: Remove references to PCRE Posix 
Also Fixed the the B5500 simulator still had the HAVE_PCREPOSIX_H
instead of HAVE_PCRE_H.
 2020-03-08 00:08:45 -08:00
Mark Pizzolato
de335bfd6a ETHER: Silence Coverity indicated potential issues 2020-03-07 22:36:24 -08:00
Mark Pizzolato
7d079990df eclipse: Build requires USE_INT64 2020-03-07 21:28:51 -08:00
Mark Pizzolato
56f186135c TIMER: Fix startup/restart logic that accounts for time at the sim> promt 2020-03-07 21:24:03 -08:00
Mark Pizzolato
4b45b04c29 SCP: Enable Runtime REGister entry validation and checking during build 2020-03-07 20:17:36 -08:00
Mark Pizzolato
09ce5a62e3 PDP6, KA10, KI10: Update register definitions for checking 2020-03-07 20:01:26 -08:00
Mark Pizzolato
f8f7ba3492 I1401, I7094, ID16, ID32, HP2100 and S3: Correct register definitions for checking 2020-03-07 19:59:04 -08:00
Mark Pizzolato
7ee3af8b9d I7000: Update register definitions for checking 2020-03-07 19:56:55 -08:00
Mark Pizzolato
f2435c91f4 B5500: Update register definitions for checking 2020-03-07 19:55:49 -08:00
Mark Pizzolato
7015ad395c SCP: sim_timer_init must only run early, and potential NULL dereference 2020-03-07 19:54:25 -08:00
Mark Pizzolato
938aa58f3a SCP: Provide ways for VM to specify sim_interval adjustment and step units 
This affects the output of some SCP commands (including help).  The
results are cosmetic, but allows the simulator to provide correct descriptive
information.
 2020-03-07 10:13:18 -08:00
Mark Pizzolato
42bb47d961 TIMER: Be sure to empty the event queue at timer initialization 
If a reset_all_p() happens before the timing subsystem is initialized,
events can be queued with unreasonable timing measurements.
 2020-03-07 07:05:46 -08:00
Mark Pizzolato
e6d8d593b4 VAX750, VAX8200: Update UBA device map register REG initializers 2020-03-06 16:42:04 -08:00
Mark Pizzolato
80d9393b83 alpha, HP2100, ID16, ID32, I7094, PDP11 and VAX: Fix array REG definitions 
Array REGister definitions have been made consistent by passing the
name of the array object.  This allows proper sizing assessment
to occur in the register validation logic.

Some previously described array REGister initializers were not really
arrays.  Some were structures and others were merely pointers to
someplace in memory that it was desirable to view as a scalar array.

Structures or other blob data should now use SAVEDATA.  Virtual
arrays intended to be interpret some part of memory as scalar data
now use VBRDATA initializers.
 2020-03-06 16:29:17 -08:00
Peter Schorn
5a293ac4ff AltairZ80: Additional register updates 2020-03-06 15:34:03 -08:00
Mark Pizzolato
565596a5af ETHER: Minor adjustments for building on the simh 3.x codebase 2020-03-06 15:32:12 -08:00
Mark Pizzolato
b76fd3ed44 SCP: Preparing for dynamic testing of simulator REGister definitions at startup 2020-03-06 15:28:52 -08:00
Mark Pizzolato
2e41007e0d AltairZ80: Adjust REG array descriptors (BRDATA) to provide array object addrs 
No address value are changed, by a pointer the the array object is
explicitly provided which allows validation logic to determine the
size of the array object rather than merely it's first element.
 2020-03-03 07:50:33 -08:00
Peter Schorn
504aad14cf AltairZ80: Update clock register definitions 2020-03-03 02:31:51 -08:00
Mark Pizzolato
7757ecada3 I7000: Updated register definitions. 2020-03-02 09:08:13 -05:00
Mark Pizzolato
74d61d2d87 B5500: Updated register definitions. 2020-03-02 09:07:24 -05:00
Mark Pizzolato
f07015078c PDP11 and VAX: Fix TD device IBUF and OBUF register definitions 2020-03-01 12:12:46 -08:00
Mark Pizzolato
90eddfc733 alpha, HP2100, ID16, ID32, PDP11 and VAX: Normalize array REG definitions 
Array REGister definitions have been made consistent by passing the
address of the whole array object.  This allows proper sizing assessment
to occur in the register validation logic.
 2020-03-01 12:11:13 -08:00
Mark Pizzolato
7b75c89aaf Interdata 16 & 32: Fix DP device width of RTIME, STIME, and WTIME definitions 2020-03-01 12:09:47 -08:00
Mark Pizzolato
762bb93199 alpha: Fix DMAPEN register definition 2020-03-01 12:09:13 -08:00
Mark Pizzolato
12d6c1fce4 PDP11: Fix INT register definitions in PTR and PTP devices 2020-03-01 12:08:24 -08:00
Mark Pizzolato
6da28c516f VAX730, VAX750: Remove invalid REGister definitions in console TU58 (TD) device 2020-03-01 12:07:34 -08:00
Mark Pizzolato
471dbc5f66 B5500: Fix Windows build to define USE_INT64 2020-02-28 08:08:33 -08:00
Mark Pizzolato
93aa0de425 I7094: Reorganize BUF REGisters to avoid dynamic buffer allocation 
This allows building with dynamic runtime register definition checking
 2020-02-28 07:47:44 -08:00
Mark Pizzolato
b8bf4de34d PDP11 Unibus and Qbus VAX: Correct additional REGs in RQ device 2020-02-28 07:44:41 -08:00
Mark Pizzolato
e06a5d7821 AltairZ80: Fix spelling in register description 2020-02-26 22:03:01 -08:00
Mark Pizzolato
ba7316ea8a IBM1130: Correct the width of the ILSW registers 2020-02-26 21:55:51 -08:00
Seth Morabito
814ce9ea2a 3b2: Fix incorrect register width 
Several registers in the TIMERS device were described
as being 16 bits wide, when they are in fact 8 bits wide.
 2020-02-26 17:27:11 -08:00
Richard Cornwell
6aafb375eb KA10: Updated register definitions. 2020-02-26 20:10:42 -05:00
Richard Cornwell
418ac042db B5500: Updated definition of Q register. 2020-02-26 20:10:02 -05:00
Mark Pizzolato
3b802f644d PDP11, Unibus and Qbus VAX: Correct REG sizes in RQ, TQ and XQ devices 2020-02-26 13:30:21 -08:00
Mark Pizzolato
146f05d1f7 SCP: Cleanup compiler warning about potential buffer truncation 2020-02-25 00:17:49 -08:00