Added BASE option to auxcpu to move memory region.
Fix errors in Card Reader/Card Punch translation and operation.
Fixed problems with ITS quantum timer.
Added support for System Concepts DC10 disk controller (Lars).
Fixed errors in Line Printer control codes.
Added support for Lines per page to LP10.
Fixed issues with 7 track tapes on TM10.
Updated user guides
This will not change much, but it may be useful for sane idling depending
on the way the running OS actually uses the interval timer for clock ticks.
Some discussion about this in #713
Avoid the common situation on with this simulator whereby the programmatic
interval timer is being used for intervals which change often. The internal
calibrated timing routines depend on consistent rate for the calibrated device.
As discussed in #699
This avoids a divide by zero which is never right, but it is unclear
what the real hardware did. It wouldn't be useful in any case.
As discussed in #486
Most history routines defined a local sim_eval of the proper length, but the
erroneous ones were fixed length machines that defined an integer variable
instead of an integer array of length 1. The VAX used the global sim_eval.
The changes follow the VAX practice.
As discussed in #378
The fixes include:
1. Tightening up the "magic" code so that it can now tell EXE, SAV, and RIM
formats apart.
2. Skipping the loader itself for both RIM10B and ITS RIM. (PDP10 Macro manual
says that RIM10B always includes the loader.) 3. Distinguishing ITS RIM from
RIM10B by the length of the loader block.
4. Adding the slight differences in processing between ITS RIM and RIM10B.
There is no documentation change. -R or the extension .RIM still invoke the
RIM loader, and the code tells ITS and RIM10B apart.
These changes facilitate more robust parameter type checking and helps
to identify unexpected coding errors.
Most simulators can now also be compiled with a C++ compiler without
warnings.
Additionally, these changes have also been configured to facilitate easier
backporting of simulator and device simulation modules to run under the
simh v3.9+ SCP framework.
If the nested indirect/execute limit (INDMAX, XCTMAX) is set to 0, the simulator will loop indefinitely in an indirect address or execute loop, testing for interrupts before each memory reference. Thus, on an infinite loop, the simulator will never complete the instruction, but the instruction is interruptible. So for example, under TOPS-10:
.r ddt
1/ 0 jrstf @1
1$g
^C
^C
.
The JRSTF will never finish, but it can be interrupted by any device, and double ^C will return control to the command line.
If INDMAX or XCTMAX is non-zero, the previous behavior of limiting loops to a specific depth is retained. However, the default value is now 0.
This closes issue #218.
Conflicts:
doc/pdp10_doc.doc
Vector values contained in device information blocks are the true bus relative vector values. CPU specific biased vector values are produced by the respective vector fetching logic and vector values are limited to 9 bits with <1:0> = 0 as specified in both the Unibus and Qbus documents.
