- Periodic "python cmake/generate.py" to sync with makefile changes.
- Ensure that AIO_CCDEFS (makefile) and USES_AIO (CMake generate.py) are
present for PDP-10 simulators. Otherwise, user gets a warning message
when the simulator starts about network support and asynchronous I/O.
Adds the following devices to AltairZ80:
TUART0: Cromemco FDC controller TUART console port at I/O address 0x00.
TUART1: Cromemco TU-ART port A at I/O address 0x20.
TUART2: Cromemco TU-ART port B at I/I address 0x50.
These devices are fully TMXR capable.
I was having problems with the JAIR device keeping up with received
data at 57.6K.
This PR makes the following changes to the JAIR devices:
- Refactors the service routines into STAT, TX and RX units
- Adds a 128-byte input ring buffer
- Corrects a null pointer exception
- Adds overrun status bit implementation
- Removes a tab with spaces
Changing the CPU type or MEMORY size/configuration causes memory
resources mapped by other devices to be removed. This is not made
clear by "HELP CPU" and the user has no feedback that this is
happening.
This PR does the following:
1) HELP SET CPU shows that SET CPU MEMORY requires a value.
2) Feedback is provided if the value is omitted or not properly formatted.
3) Unmapped memory resources caused by a SET CPU command are displayed
on the SIMH console.
4) Adds a SET CPU RESIZEMEMORY command that resizes system memory
without unmapping other device memory resources.
The MEM dump command would not display past SET CPU xK memory
size. This prevented displaying ROMs or other RAM windows when
a lower amount of memory was specified. This PR changes MEM to
always display a minimum of a 64K regardless of main RAM size.
Josh's Altair/IMSAI Replacement (JAIR) is a single board computer
(SBC) for the S100 bus. I created this device to assist a friend
with getting IMP and CBBS working on his JAIR. Without having a
JAIR myself, AltairZ80 to the rescue!
The following devices are added:
JAIR - The main JAIR board I/O and ROM
JAIRS0 - Serial Port 0 (COM1)
JAIRS1 - Serial Port 1 (COM2)
JAIRP - Parallel Port
This was a bit challenging because the JAIR uses an on-board SD
card with FAT file system to hold its BIOS and CP/M disk images.
The ATTACH command is used to mount SD card images to the
simulator. The simulator emulates the SD card interface for
read/writing SD card sectors. These images are easily mounted on
a Mac making moving files around easy. I do not know about Windows.
These same images can be written to an SD card and used with real
JAIR hardware, which may be useful for JAIR owners.
The serial and parallel ports fully support TMXR. Host serial ports
and sockets may be attached to these devices.
I am working on a GitHub repository containing an SD card image and
init script that will boot CP/M 2.2 on the JAIR simulator.
Is this device one that should be added to AltairZ80?
The Sol-20 provides 1K RAM at C800. This was discovered to be missing
when issuing a "SET CPU 24K" command. Without the CPU providing RAM
at C800, the Sol-20 would not function. This PR corrects the problem
by having the SOL20 device provide its own 1K RAM at C800.
Adds 6850 DCD status latch to M2SIO devices.
Adds vector interrupt support to M2SIO devices.
Removes CTS inactive transmit disable from PMMI device.
Adds IMSAI-style programmed output to CPU/SIO devices.
SET CPU PO will display "PO: AREG" upon an "OUT 0FFH"
instruction.
SET CPU NOPO will disable the function (default).
Corrects problem with Mode 0 interrupts.
When the CPU receives an interrupt, it pushes the current
program counter on the stack. The current implementation
of Mode 0 was performing interrupt processing after fetching
the next opcode from RAM, which also increases the PC by 1.
This caused PC+1 to be pushed on the stack. The interrupt
processing is now done prior to fetching the next opcode,
preserving the correct program counter.
* CMake build infrastructure
The squashed commit that builds and packages releases for the SIMH
simulator suite with CMake, version 3.14 or newer.
See README-CMake.md for documentation.
After adding the sim_clock_precalibrate_commands, the PC was not zero
at the sim> prompt after loading altairz80.
Set CPU_S to zero in cpu_reset to address this issue.
While working on the AltairZ80 documentation, I found some problems
with the SOL20 registers and fixed some formatting issues.
Added static and "vdm1_" prefix to "charset" variable in s100_vdm1.c
This PR adds support for the Processor Technology VDM-1 display adapter and Sol-20 computer system. The VDM-1 was integrated into the Sol-20 but has been separated out into its own device.
This PR adds the following devices to the AltairZ80 simulator:
VDM1 - Processor Technology VDM-1 display adapter
SOL20 - Processor Technology SOL20 with SOLOS ROMs
SOL20K - SOL20 Keyboard (callback from VDM1)
SOL20T - SOL20 Tape (reads/writes cassette file images)
SOL20S - SOL20 Serial Port (TMXR capable)
SOL20P - SOL20 Printer Port (TMXR capable)
Used to initialize SCP timers to prevent problems during simulator startup
when THROTTLE is being used.
/*
* This sequence of instructions is a mix that mimics
* a resonable instruction set that is a close estimate
* to the calibrated result.
*/
static const char *cpu_clock_precalibrate_commands[] = {
"-m 100 LXI H,200H",
"-m 103 MVI B,0",
"-m 105 DCR B",
"-m 106 MOV M,B",
"-m 107 INX H",
"-m 108 JNZ 0105H",
"-m 10B JMP 0100H",
"PC 100",
NULL};
Proper initialization of the ADCS6 unit data structure depended on the
ADCS6 device being enabled. In cases where the ADCS6 unit was not
enabled, non-debug builds may crash on some host platforms depending on
compiler/memory layout.
As pointed out by @markpizz , the only allowed macro to initialize UNIT
structures is the UDATA macro.
Setting additional UNIT data structure items should be set through explicit
initialization code in the DEVICE reset routine.
AltairZ80 uses 0 for the VM-specific HLT instruction stop code.
SCP defines SCPE_OK as 0.
SCP uses 0 to mean all errors ("ON ERROR").
The command "ON 0" will generate "%SIM-ERROR: Invalid argument: 0".
This PR changes the HALT stop code from 0 to 5.
