Commit graph

237 commits

Author SHA1 Message Date
Howard M. Harte
7094222ada AltairZ80: SCP300F: Add support for MS-DOS 2.00.
* Add support for 8259 interrupt controller.
* Add support for Cromemco and Tarbell Monitor ROMs.
* To allow port 0xFE to be used by the simh_dev.
* Use the CPU's SR instead of a SCP300F-specific one.
* 9513 RTC support.
2022-11-27 14:38:05 -05:00
Patrick Linstruth
8b181a360c AltairZ80: PMMI device DTR/RTS default changes and support for sockets 2022-11-23 11:23:20 -05:00
Patrick Linstruth
e2d422c2d3 AltairZ80: Add support for Morrow Micro Decision
Moved MMD and MMDM devices under Morrow Devices comment.
2022-11-23 11:22:51 -05:00
Patrick Linstruth
7a5432d9e2 AltairZ80: Add "MEM" and "REG" simulator-specific commands
sim> mem df00
DF00 C3 5C E2 C3 58 E2 7F 00 43 6F 70 79 72 69 67 68 .\..X...Copyrigh
DF10 74 20 31 39 37 39 20 28 63 29 20 62 79 20 44 69 t 1979 (c) by Di
DF20 67 69 74 61 6C 20 52 65 73 65 61 72 63 68 20 20 gital Research
DF30 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00     ............
DF40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
DF50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
DF60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ....s...ub...m..
DF70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ..I..tT...e.....
DF80 00 00 00 00 00 00 00 00 08 DF 00 00 5F 0E 02 C3 d....4...l.._0.r
DF90 05 00 C5 CD 8C DF C1 C9 3E 0D CD 92 DF 3E 0A C3 .d..M...>....>..
DFA0 92 DF 3E 20 C3 92 DF C5 CD 98 DF E1 7E B7 C8 23 ..> ..a.....~..#
DFB0 E5 CD 8C DF E1 C3 AC DF 0E 0D C3 05 00 5F 0E 0E ...r........._..
DFC0 C3 05 00 CD 05 00 32 EE E6 3C C9 0E 0F C3 C3 DF ...K..2..<..'.s.
DFD0 AF 32 ED E6 11 CD E6 C3 CB DF 0E 10 C3 C3 DF 0E .2...a...p.P....
DFE0 11 C3 C3 DF 0E 12 C3 C3 DF 11 CD E6 C3 DF DF 0E ...r...0..v.....
DFF0 13 C3 05 00 CD 05 00 B7 C9 0E 14 C3 F4 DF 11 CD .....a.l........

sim> reg
C0Z1M0E1I1 A=02 B=007F D=DF06 H=EA0E S=EA37 P=FA6B ANI 01h
sim> set on
sim> on error reg
sim> s

Step expired, PC: 0FA6D (JZ 0FA69h)
C0Z1M0E1I1 A=00 B=007F D=DF06 H=EA0E S=EA37 P=FA6D JZ 0FA69h
sim> s

Step expired, PC: 0FA69 (IN 10h)
C0Z1M0E1I1 A=00 B=007F D=DF06 H=EA0E S=EA37 P=FA69 IN 10h
sim> s

Step expired, PC: 0FA6B (ANI 01h)
C0Z1M0E1I1 A=02 B=007F D=DF06 H=EA0E S=EA37 P=FA6B ANI 01h
2022-11-23 11:22:12 -05:00
Howard M. Harte
33aad32550 AltairZ80: TDD: Remove unused variable. 2022-11-19 13:48:34 -05:00
Howard M. Harte
f578ce76a7 AltairZ80: DJHDC: Conditionalize interrupt support. 2022-11-19 13:48:34 -05:00
Howard M. Harte
61a520a978 AltairZ80: Morrow HDC-DMA Hard Disk Controller. 2022-11-15 12:21:58 -05:00
Howard M. Harte
f77485ca99 AltairZ80: Add Tarbell Double-Density FDC
This controller is based the wd179x, adding a couple of Tarbell-specific
registers.
2022-11-15 12:21:58 -05:00
Howard M. Harte
3719b46524 AltairZ80: SIO: Fix warning for type mismatch.
Fix warning introduced in PR#108
2022-11-10 10:45:46 -05:00
Howard M. Harte
71913f26eb AltairZ80: SIO: Add setFCBAddressCmd to simh_dev.
* Allows setting the FCB address used to send filenames between the host
  and guest operating systems.
* Increment the SIMH device version to SIMH005.
2022-11-07 09:22:14 -05:00
Howard M. Harte
e91fbebe3d AltairZ80: i86: Don't clear segment override on REPE/REPNE
MASM generates REP CS:MOVSW as:

REP
CS:
MOVSW

The Seattle Computer Products 8086 assembler allows the segment override
as a discrete opcode.  This means that:

CS:
REP
MOVSW

is also possible, and in fact used in the SCP Monitor v1.6.

The i86 emulator was clearing the override flags when REPE/REPNE,
is encountered, which causes the segment override to be lost.
Verifying the behavior of a real 80286 processor in an IBM PC/AT
(5170) using MS-DOS 6.22 DEBUG shows that both instruction sequences
yield the desired segment override.
2022-11-06 16:41:51 -05:00
Howard M. Harte
e1d27aa167 AltairZ80: i86: Fix bug in AAD instruction. 2022-11-06 16:41:51 -05:00
Howard M. Harte
7a273d70d7 AltairZ80: wd179x: Improve debugging for WRITE_TRACK. 2022-11-01 21:08:27 -07:00
Howard M. Harte
4cfedd1930 AltairZ80: s100_hdc1001: fix bug in format. 2022-11-01 21:08:20 -07:00
Howard M. Harte
ef6667b05c
Fix AltairZ80 compilation with Visual Studio 2008 (#85)
* AltairZ80: SS1: Fix disable after reset.

The CompuPro System Support 1 could not be disabled after enabled and
used due to timers causing it to be busy.  Reset properly so that "set
ss1 disabled" works after reset.

* AltairZ80: wd179x: Properly reset 179x state.

* AltairZ80: M68K: Fix compile with VS2008.

* Musashi: Fix compilation with Visual Studio 2008.

* AltairZ80: M68K: Resolve warnings in softfloat.

* AltairZ80: Add headers to .vcproj
2022-10-24 17:15:51 -04:00
Howard M. Harte
c6a6c72c63 AltairZ80: Reconcile license with open-simh. 2022-10-09 09:10:27 -07:00
Peter Schorn
3a7ec4788f AltairZ80: M68K: Fix hang with 'expect' 2022-10-08 00:25:25 -07:00
Howard M. Harte
1110802bb1 AltairZ80: M68K: Changes for SIMH.
Build: Compiled with VS 2022, Clang, gcc.
Test: Boot and run CP/M-68K from: https://schorn.ch/cpm/zip/cpm68k.zip
2022-10-08 00:25:04 -07:00
Howard M. Harte
ab21cbab7a AltairZ80: M68K: Update to Musashi 4.10
Includes up through commit fc7a6fc602e2fbcd24851670a5242358765feacf from
https://github.com/kstenerud/Musashi
2022-10-08 00:24:59 -07:00
Howard M. Harte
9fa55d0013 AltairZ80: M68K: Move Musashi to m68k directory.
The M68K CPU is from https://github.com/kstenerud/Musashi.  Move into
its own directory to facilitate easier synchronization with upstream
Musashi.
2022-10-08 00:24:49 -07:00
Howard M. Harte
86f65093bc AltairZ80: s100_hdc1001: Resolve CID 1515006. 2022-03-14 22:43:56 -07:00
Peter Schorn
8f3a2057e1 AltairZ80: Fix Coverity identified issues in s100_jd2d.c 2022-03-14 14:55:50 +01:00
Howard M. Harte
2cede2fb99 AltairZ80: HDC-1001: Resolve CID 1514860, 1514861. 2022-03-08 12:31:04 -08:00
Howard M. Harte
e293731e35 AltairZ80: Resolve CID 1514796. 2022-03-08 12:29:49 -08:00
Peter Schorn
ab6c2c043e AltairZ80: Improved vector interrupt implementation 2021-12-04 20:42:03 +01:00
Howard M. Harte
08a0ad2d88 2SIO: add support for interrupts.
Add vectored interrupt support for the Altair 2SIO card.
2021-10-11 08:50:29 -07:00
Howard M. Harte
81afea160c AltairZ80: Add support for Z80 Mode 2 interrupts.
Add support for Z80 Mode 2 interrupts to altairz80_cpu.c
Also implement interrupts for the WD179x floppd controller.
2021-10-11 08:50:20 -07:00
Peter Schorn
105975feb4 AltairZ80: Fix reset routine for DJ2D device 2021-08-31 08:48:35 +02:00
Howard M. Harte
9865180990 wd179x: Keep WD179X_INFO_PUB in sync. 2021-07-27 20:28:21 -07:00
Howard M. Harte
d743cf9f45 wd179x: Add support for wd1795/7 side select output. 2021-07-25 17:35:54 -07:00
Peter Schorn
65542cd46d AltairZ80: Fix showdata in MDS-AD device 2021-02-28 08:20:45 +01:00
Howard M. Harte
6c72231177 AltairZ80: Add MDS-AD support for single-density
The North Star MDS-AD disk controller supports both single- and
double-density operation.  While mixed-density is supported by the
controller, it is not supported by AltairZ80 due to a limitation of the
.nsi image file format.  The .nsi image file format requires all sectors
to be of the same density.
2021-02-15 13:48:47 -08:00
Howard M. Harte
f0dd8184d8 AltairZ80: Fix North Star MDS-AD for NSDOS
The "Window" bit was getting cleared too late, causing the "next" sector
to be written under North Star DOS.  Due to differences between CP/M and
North Star disk access routines, this was not an issue under CP/M.

Test: Verify that North Star DOS and CP/M can format, copy and verify an
entire disk.

North Star Disk Operating System, Version 2.1.1, at  100
+GO DT 2
SINGLE(S) OR DOUBLE(D) DENSITY TEST? D
BOTH SIDES (Y OR N)? Y
LOAD DISKETTE THEN PRESS RETURN TO BEGIN TEST
PASS COMPLETE
PASS COMPLETE
PASS COMPLETE
PASS COMPLETE
PASS COMPLETE
CONTROL-C STOP
+GO CD 1 2
COPY BOTH SIDES (Y OR N)? Y
LOAD DISKETTES AND PRESS RETURN WHEN READY.
COPY COMPLETED.
+GO CK 1
DISKETTE CHECK, VERSION 1
CHECK CODE: 46513
+GO CK 2
DISKETTE CHECK, VERSION 1
CHECK CODE: 46513
+
2021-02-15 11:01:07 -08:00
Peter Schorn
ddea510008 AltairZ80: Updated ICOM device 2021-02-09 13:34:53 +01:00
Peter Schorn
9f064db561 AltairZ80: Updated Morrow Disk Jockey disk controller and minor code cleanup 2021-01-18 20:43:56 +01:00
Howard M. Harte
dc0236bc77 AltairZ80: vfdhd: Fix unit detach. 2021-01-17 12:20:33 -08:00
Howard M. Harte
cc464d4acb AltairZ80: mdfc: Fix unit detach. 2021-01-16 14:20:03 -08:00
Peter Schorn
2911b3a440 AltairZ80: Added Morrow Disk Jockey disk controller 2021-01-03 14:24:30 +01:00
Peter Schorn
5f2470904b AltairZ80: Updated M2SIO device 2020-12-17 09:31:53 +01:00
Howard M. Harte
c32b3ab054 AltairZ80: HDC-1001: Complete the implementation.
The ADC HDC-1001 in SIMH was incomplete and non-functional.

Finish the simulation to be functional under CP/M 2.2, CP/M 3.0,
and OASIS 5.6.
2020-12-13 16:18:50 -08:00
Howard M. Harte
0eb14db0a7 AltairZ80: wd179x: Improve accuracy of the simulation.
* Properly handle the case when a disk is not attached.
    * Add register access for debugging.
    * Assert DRQ as well as IRQ for software that checks DRQ.
    * Add API to get the number of heads for the currently-selected
      disk.
    * Follow SIMH conventions for debug logging.
    * Add ability to debug IMD from the wd179x debug settings.

Tests:
    * Format and disk access on Cromemco CP/M 2.2, CDOS, 86-DOS,
      MS-DOS 1.25, OASIS 5.6.
2020-12-13 15:41:08 -08:00
Howard M. Harte
898d7cbdbb AltairZ80: Add Z80 Interrupt Mode register (IM.) 2020-12-12 20:43:21 -08:00
Howard M. Harte
d0c009504b AltairZ80: Add support for the AB Digital B810.
The AB Digital Design B810 RAM card is a 256K Dynamic RAM card
with onboard refresh logic.  AltairZ80 support emulates four of
these cards for a total of 16 banks.

As used for the OASIS operating system, the B810 is configured
with common memory at the low addresses (0000h-3FFFh) with 16
banks of 48K from 4000h-FFFFh.

In order to have the common memory appear from 0000-3FFFh, set
the COMMONLOW register to 1:

D COMMONLOW 1
2020-12-12 20:43:07 -08:00
Peter Schorn
5211c1134a AltairZ80: New iCOM device, PTP port command, code cleanup 2020-11-28 14:02:01 +01:00
Peter Schorn
199adf7641 AltairZ80: Additional updates for SCP internal time base 2020-10-30 09:52:56 +01:00
Mark Pizzolato
263e0e7ed5 AltairZ80, BESM6, I7094: Adopt internal SCP internal time base 2020-10-29 13:28:41 -07:00
Peter Schorn
85858b1287 AltairZ80: Removal of unnecessary variable in s100_pmmi.c 2020-10-09 09:13:09 +02:00
Patrick Linstruth
91bce50a5f AltairZ80: Adds support for the Tarbell 2022 double density controller
The 'tarbell' device now supports Tarbell model 1011 single density
and model 2022 double density floppy disk controllers. The model is
selected using the "SET TARBELL MODEL={SD|DD}" command. Also removed
some unused local variables.
2020-10-07 09:15:35 -07:00
Peter Schorn
8aaf4598d0 AltairZ80: Minor code clean up to avoid compiler warning 2020-09-08 08:55:25 +02:00
Mark Pizzolato
ae825c9afb All: Declare sim_stop_messages as an array SCPE_BASE long
This avoids a potential invalid pointer dereference when formatting
the return value from sim_instr() if it is < SCPE_BASE but greater
than the previously defined static array size.sizeof

Update simh.doc to reflect this generic change.
2020-09-02 15:56:07 -07:00