The three CPU modes -- normal, monitor and user were represented by two binary flags (nml_mode and usr_mode). The code is simpler and easier to read if the three modes are represented by one three-valued variable, cpu_mode. In addition, record the CPU mode in the instruction history record, and add the mode to the history display.
In addition, add an optional flag to the SET CPU HISTORY=n command to *not* record instructions executed in a particular CPU mode. Flags are -n, -m and -u for normal, monitor and user mode respectively. For example, SET -m CPU HISTORY=n will only record instructions executed in normal or user mode, and will not record instructions executed in monitor mode. This change aids user-mode program debugging by not filling the history with monitor-mode service functions and interrupt activity.
Add new instruction class -- I_V_SPP for SYSPOPs and definitions for the standard ones provided by the time sharing system. Add instruction name annotation to the opc_val array.
The goals here being to simplify calling code while getting consistent output delivered everywhere it may be useful.
Modified most places which explicitly used sim_log or merely called printf to now avoid doing that and merely call sim_printf().
Instead of conditionally compiling in bootstrap support depending upon attached channel, determine dynamically based on RAD's current assignment to channel W or channel E. This allows using "set rad channel=W" for purposes of bootstrapping, and then relocating the RAD with "set rad channel=E" for running a TSS monitor that expects to find the RAD on channel E.
Normally the RAD is connected to the E channel and there is no bootstrap capability (because of hardwired WIM instruction). However, for completeness, add code to allow booting from the RAD if it is connected to the W channel. Add RAD_CHAN definition to define which controller the RAD is connected to.
Improve parentheses in bootstrap code that allows an optional word count (while also permitting the canonical bootstrap sequence).
The canonical boot sequence uses WIM 0,2 in location 5 and an initial load address in location 11 (and in the X register). This is limiting for devices like RAD that do not report an end-of-file, or for paper tape that report EOF too late and cause the WIM to fail. A simple load address in location 11, with bit 9 set to satisfy the BRX, doesn't do any word counting. The BRX always branches back to location 5.
This change allows a true negative word count to be placed in location 11 to work with a WIM XXXXX,2 where XXXXX is one location past the region to be loaded by the boot sequence. XXXXX plus the negative count in location 11 (buf[3]+buf[7]) initially points to the first location to be loaded, and the BRX will not branch when the word count is exhausted (register X=0) allowing the branch to the start address to be executed.
Old allowable boot sequence:
location 2 = WIM 12,2
location 3 = BRX 2
location 4 = LDX 11
location 5 = WIM 0,2
location 6 = SKS 21000
location 7 = BRX 5
location 10 = BRU Transfer Address
location 11 = Load address with bit 9 set to force BRX to branch
New allowable boot sequence:
location 2 = WIM 12,2
location 3 = BRX 2
location 4 = LDX 11
location 5 = WIM [end load address + 1],2
location 6 = SKS 21000
location 7 = BRX 5
location 10 = BRU Transfer Address
location 11 = Negative count to number of words to load
Received better fix from Mark Pizzolato for the problem of having 120 clock interrupts per second instead of 60. Tested for several hours and verified that wall-clock time matches TSS monitor time.
Document new breakpoint types and display and input of packed SDS internal ASCII characters. Add note describing memory map options for display and input discovered in code. Word change tracking enabled.
