Adds 6850 DCD status latch to M2SIO devices.
Adds vector interrupt support to M2SIO devices.
Removes CTS inactive transmit disable from PMMI device.
Adds IMSAI-style programmed output to CPU/SIO devices.
SET CPU PO will display "PO: AREG" upon an "OUT 0FFH"
instruction.
SET CPU NOPO will disable the function (default).
Corrects problem with Mode 0 interrupts.
When the CPU receives an interrupt, it pushes the current
program counter on the stack. The current implementation
of Mode 0 was performing interrupt processing after fetching
the next opcode from RAM, which also increases the PC by 1.
This caused PC+1 to be pushed on the stack. The interrupt
processing is now done prior to fetching the next opcode,
preserving the correct program counter.
This commit adds two new devices, "M2SIO0" and "M2SIO1", to the AltairZ80
VM. These two independent devices emulate "raw" 88-2SIO ports that can
be used instead of the "SIO" device for attaching socket and serial
ports using TMXR.
