614 lines
23 KiB
C
614 lines
23 KiB
C
/*************************************************************************
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* *
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* Copyright (c) 2021-2023 Howard M. Harte. *
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* https://github.com/hharte *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining *
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* a copy of this software and associated documentation files (the *
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* "Software"), to deal in the Software without restriction, including *
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* without limitation the rights to use, copy, modify, merge, publish, *
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* distribute, sublicense, and/or sell copies of the Software, and to *
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* permit persons to whom the Software is furnished to do so, subject to *
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* the following conditions: *
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* *
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* The above copyright notice and this permission notice shall be *
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* included in all copies or substantial portions of the Software. *
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, *
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF *
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON- *
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* INFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE *
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN *
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN *
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE *
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* SOFTWARE. *
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* *
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* Except as contained in this notice, the names of The Authors shall *
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* not be used in advertising or otherwise to promote the sale, use or *
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* other dealings in this Software without prior written authorization *
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* from the Authors. *
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* *
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* Module Description: *
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* IBC/Integrated Business Computers SMD Hard Disk Controller module *
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* for SIMH. *
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* *
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*************************************************************************/
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#include "altairz80_defs.h"
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#include "sim_imd.h"
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/* Debug flags */
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#define ERROR_MSG (1 << 0)
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#define CMD_MSG (1 << 1)
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#define RD_DATA_MSG (1 << 2)
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#define WR_DATA_MSG (1 << 3)
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#define FIFO_MSG (1 << 4)
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#define REG_MSG (1 << 5)
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#define VERBOSE_MSG (1 << 6)
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#define IBC_SMD_MAX_DRIVES 2 /* Maximum number of drives supported */
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#define IBC_SMD_MAX_SECLEN 1024 /* Maximum of 1024 bytes per sector */
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#define IBC_SMD_MAX_CYLS 1024
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#define IBC_SMD_MAX_HEADS 8
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#define IBC_SMD_MAX_SPT 256
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#define DEV_NAME "IBCSMD"
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#define IBC_SMD_STATUS_ERROR (1 << 0)
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#define IBC_SMD_ERROR_ID_NOT_FOUND (1 << 4)
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#define IBC_SMD_CMD_00 0x00
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#define IBC_SMD_CMD_SELECT_UNIT 0x10
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#define IBC_SMD_CMD_SET_CYL 0x20
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#define IBC_SMD_CMD_SET_HEAD 0x40
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#define IBC_SMD_CMD_REZERO 0x80
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#define IBC_SMD_CMD_WRITE_SECT 0x81
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#define IBC_SMD_CMD_READ_SECT 0x88
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#define IBC_SMD_REG_ERROR 0x0 /* Read */
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#define IBC_SMD_REG_ARG0 0x0 /* Write */
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#define IBC_SMD_REG_ARG1 0x1 /* Write */
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#define IBC_SMD_REG_CMD 0x2 /* Write */
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#define IBC_SMD_REG_SEC 0x3 /* Write */
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#define IBC_SMD_REG_STATUS 0x7
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#define IBC_SMD_REG_DATA 0x4
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#define IBC_SMD_REG_SECID 0x7
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typedef struct {
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UNIT *uptr;
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uint8 readonly; /* Drive is read-only? */
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uint16 sectsize; /* sector size */
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uint16 nsectors; /* number of sectors/track */
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uint16 nheads; /* number of heads */
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uint16 ncyls; /* number of cylinders */
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uint16 cur_cyl; /* Current cylinder */
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uint8 cur_head; /* Current Head */
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uint8 cur_sect; /* current starting sector of transfer */
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uint8 ready; /* Is drive ready? */
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} IBC_SMD_DRIVE_INFO;
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typedef struct {
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PNP_INFO pnp; /* Plug and Play */
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uint8 intenable; /* Interrupt Enable */
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uint8 intvector; /* Interrupt Vector */
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uint8 sel_drive; /* Currently selected drive */
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uint8 arg0; /* IBC SMD Argument 0 Register */
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uint8 arg1; /* IBC SMD Argument 1 Register */
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uint8 cmd; /* IBC SMD Command Register */
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uint8 sec; /* IBC SMD Sector Register */
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uint8 status_reg; /* Status Register */
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uint8 error_reg; /* Error Register */
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uint8 retries; /* Number of retries to attempt */
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uint8 ndrives; /* Number of drives attached to the controller */
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uint8 sectbuf[IBC_SMD_MAX_SECLEN];
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uint16 secbuf_index;
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IBC_SMD_DRIVE_INFO drive[IBC_SMD_MAX_DRIVES];
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} IBC_SMD_INFO;
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static IBC_SMD_INFO ibc_smd_info_data = { { 0x0, 0, 0x40, 8 } };
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static IBC_SMD_INFO *ibc_smd_info = &ibc_smd_info_data;
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extern uint32 PCX;
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extern int32 vectorInterrupt; /* Interrupt pending */
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extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
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int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
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extern int32 find_unit_index(UNIT *uptr);
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#define UNIT_V_IBC_SMD_VERBOSE (UNIT_V_UF + 1) /* verbose mode, i.e. show error messages */
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#define UNIT_IBC_SMD_VERBOSE (1 << UNIT_V_IBC_SMD_VERBOSE)
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#define IBC_SMD_CAPACITY (512*4*16*512) /* Default Disk Capacity Quantum 2020 */
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static t_stat ibc_smd_reset(DEVICE *ibc_smd_dev);
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static t_stat ibc_smd_attach(UNIT *uptr, CONST char *cptr);
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static t_stat ibc_smd_detach(UNIT *uptr);
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static t_stat ibc_smd_unit_set_geometry(UNIT* uptr, int32 value, CONST char* cptr, void* desc);
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static t_stat ibc_smd_unit_show_geometry(FILE* st, UNIT* uptr, int32 value, CONST void* desc);
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static int32 ibcsmddev(const int32 port, const int32 io, const int32 data);
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static uint8 IBC_SMD_Read(const uint32 Addr);
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static uint8 IBC_SMD_Write(const uint32 Addr, uint8 cData);
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static t_stat IBC_SMD_doCommand(void);
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static const char* ibc_smd_description(DEVICE *dptr);
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static UNIT ibc_smd_unit[] = {
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{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, IBC_SMD_CAPACITY) },
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{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, IBC_SMD_CAPACITY) },
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{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, IBC_SMD_CAPACITY) },
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{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, IBC_SMD_CAPACITY) }
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};
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static REG ibc_smd_reg[] = {
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{ HRDATAD (SMD_ERROR, ibc_smd_info_data.error_reg, 8, "SMD Error Register"), },
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{ HRDATAD (SMD_STATUS, ibc_smd_info_data.status_reg, 8, "SMD Status Register"), },
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{ HRDATAD (SMD_ARG0, ibc_smd_info_data.arg0, 8, "SMD ARG0 Register"), },
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{ HRDATAD (SMD_ARG1, ibc_smd_info_data.arg1, 8, "SMD ARG1 Register"), },
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{ HRDATAD (SMD_CMD, ibc_smd_info_data.cmd, 8, "SMD Command Register"), },
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{ HRDATAD (SMD_SEC, ibc_smd_info_data.sec, 8, "SMD Sector Register"), },
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{ FLDATAD (INTENABLE, ibc_smd_info_data.intenable, 1, "SMD Interrupt Enable"), },
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{ DRDATAD (INTVECTOR, ibc_smd_info_data.intvector, 8, "SMD Interrupt Vector"), },
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{ NULL }
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};
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#define IBC_SMD_NAME "IBC SMD Hard Disk Controller"
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static const char* ibc_smd_description(DEVICE *dptr) {
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if (dptr == NULL) {
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return NULL;
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}
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return IBC_SMD_NAME;
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}
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static MTAB ibc_smd_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE",
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&set_iobase, &show_iobase, NULL, "Sets disk controller I/O base address" },
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{ MTAB_XTD|MTAB_VUN|MTAB_VALR, 0, "GEOMETRY", "GEOMETRY",
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&ibc_smd_unit_set_geometry, &ibc_smd_unit_show_geometry, NULL,
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"Set disk geometry C:nnnn/H:n/S:nnn/N:nnnn" },
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{ 0 }
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};
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/* Debug Flags */
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static DEBTAB ibc_smd_dt[] = {
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{ "ERROR", ERROR_MSG, "Error messages" },
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{ "REG", REG_MSG, "Register messages" },
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{ "CMD", CMD_MSG, "Command messages" },
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{ "READ", RD_DATA_MSG, "Read messages" },
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{ "WRITE", WR_DATA_MSG, "Write messages" },
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{ "FIFO", FIFO_MSG, "FIFO messages" },
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{ "VERBOSE", VERBOSE_MSG, "Verbose messages" },
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{ NULL, 0 }
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};
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DEVICE ibc_smd_dev = {
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DEV_NAME, ibc_smd_unit, ibc_smd_reg, ibc_smd_mod,
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IBC_SMD_MAX_DRIVES, 10, 31, 1, IBC_SMD_MAX_DRIVES, IBC_SMD_MAX_DRIVES,
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NULL, NULL, &ibc_smd_reset,
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NULL, &ibc_smd_attach, &ibc_smd_detach,
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&ibc_smd_info_data, (DEV_DISABLE | DEV_DIS | DEV_DEBUG), ERROR_MSG,
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ibc_smd_dt, NULL, NULL, NULL, NULL, NULL, &ibc_smd_description
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};
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/* Reset routine */
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static t_stat ibc_smd_reset(DEVICE *dptr)
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{
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PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;
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if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */
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sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &ibcsmddev, "ibcsmddev", TRUE);
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} else {
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/* Connect IBC_SMD at base address */
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if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &ibcsmddev, "ibcsmddev", FALSE) != 0) {
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sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
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return SCPE_ARG;
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}
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}
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ibc_smd_info->status_reg = 0xd1;
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ibc_smd_info->error_reg = 0x80;
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ibc_smd_info->sel_drive = 0;
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return SCPE_OK;
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}
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/* Attach routine */
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static t_stat ibc_smd_attach(UNIT *uptr, CONST char *cptr)
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{
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t_stat r = SCPE_OK;
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IBC_SMD_DRIVE_INFO *pDrive;
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int i = 0;
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i = find_unit_index(uptr);
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if (i == -1) {
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return (SCPE_IERR);
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}
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pDrive = &ibc_smd_info->drive[i];
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/* Defaults for the Quantum 2020 Drive */
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pDrive->ready = 0;
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if (pDrive->ncyls == 0) {
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/* If geometry was not specified, default to Quantum 2020 */
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pDrive->ncyls = 512;
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pDrive->nheads = 4;
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pDrive->nsectors = 16;
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pDrive->sectsize = 512;
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}
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r = attach_unit(uptr, cptr); /* attach unit */
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if ( r != SCPE_OK) /* error? */
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return r;
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/* Determine length of this disk */
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if(sim_fsize(uptr->fileref) != 0) {
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uptr->capac = sim_fsize(uptr->fileref);
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} else {
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uptr->capac = (pDrive->ncyls * pDrive->nsectors * pDrive->nheads * pDrive->sectsize);
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}
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pDrive->uptr = uptr;
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/* Default for new file is DSK */
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uptr->u3 = IMAGE_TYPE_DSK;
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if(uptr->capac > 0) {
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r = assignDiskType(uptr);
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if (r != SCPE_OK) {
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ibc_smd_detach(uptr);
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return r;
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}
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}
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sim_debug(VERBOSE_MSG, &ibc_smd_dev, DEV_NAME "%d, attached to '%s', type=DSK, len=%d\n",
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i, cptr, uptr->capac);
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pDrive->readonly = (uptr->flags & UNIT_RO) ? 1 : 0;
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ibc_smd_info->error_reg = 0;
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pDrive->ready = 1;
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ibc_smd_info->status_reg = 0;
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return SCPE_OK;
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}
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/* Detach routine */
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static t_stat ibc_smd_detach(UNIT *uptr)
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{
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IBC_SMD_DRIVE_INFO *pDrive;
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t_stat r;
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int32 i;
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i = find_unit_index(uptr);
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if (i == -1) {
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return (SCPE_IERR);
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}
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pDrive = &ibc_smd_info->drive[i];
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pDrive->ready = 0;
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sim_debug(VERBOSE_MSG, &ibc_smd_dev, "Detach " DEV_NAME "%d\n", i);
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r = detach_unit(uptr); /* detach unit */
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if ( r != SCPE_OK)
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return r;
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return SCPE_OK;
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}
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/* Set geometry of the disk drive */
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static t_stat ibc_smd_unit_set_geometry(UNIT* uptr, int32 value, CONST char* cptr, void* desc)
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{
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IBC_SMD_DRIVE_INFO* pDrive;
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int32 i;
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int32 result;
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uint16 newCyls, newHeads, newSPT, newSecLen;
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i = find_unit_index(uptr);
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if (i == -1) {
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return (SCPE_IERR);
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}
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pDrive = &ibc_smd_info->drive[i];
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if (cptr == NULL)
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return SCPE_ARG;
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result = sscanf(cptr, "C:%hd/H:%hd/S:%hd/N:%hd", &newCyls, &newHeads, &newSPT, &newSecLen);
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if (result != 4)
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return SCPE_ARG;
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/* Validate Cyl, Heads, Sector, Length */
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if (newCyls < 1 || newCyls > IBC_SMD_MAX_CYLS) {
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sim_debug(ERROR_MSG, &ibc_smd_dev, DEV_NAME "%d: Number of cylinders must be 1-%d.\n",
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ibc_smd_info->sel_drive, IBC_SMD_MAX_CYLS);
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return SCPE_ARG;
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}
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if (newHeads < 1 || newHeads > IBC_SMD_MAX_HEADS) {
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sim_debug(ERROR_MSG, &ibc_smd_dev, DEV_NAME "%d: Number of heads must be 1-%d.\n",
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ibc_smd_info->sel_drive, IBC_SMD_MAX_HEADS);
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return SCPE_ARG;
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}
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if (newSPT < 1 || newSPT > IBC_SMD_MAX_SPT) {
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sim_debug(ERROR_MSG, &ibc_smd_dev, DEV_NAME "%d: Number of sectors per track must be 1-%d.\n",
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ibc_smd_info->sel_drive, IBC_SMD_MAX_SPT);
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return SCPE_ARG;
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}
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if (newSecLen != 512 && newSecLen != 256 && newSecLen != 128) {
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sim_debug(ERROR_MSG, &ibc_smd_dev,DEV_NAME "%d: Sector length must be 128, 256, or 512.\n",
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ibc_smd_info->sel_drive);
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return SCPE_ARG;
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}
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pDrive->ncyls = newCyls;
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pDrive->nheads = newHeads;
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pDrive->nsectors = newSPT;
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pDrive->sectsize = newSecLen;
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return SCPE_OK;
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}
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/* Show geometry of the disk drive */
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static t_stat ibc_smd_unit_show_geometry(FILE* st, UNIT* uptr, int32 value, CONST void* desc)
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{
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IBC_SMD_DRIVE_INFO* pDrive;
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int32 i;
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i = find_unit_index(uptr);
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if (i == -1) {
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return (SCPE_IERR);
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}
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pDrive = &ibc_smd_info->drive[i];
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fprintf(st, "C:%d/H:%d/S:%d/N:%d",
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pDrive->ncyls, pDrive->nheads, pDrive->nsectors, pDrive->sectsize);
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return SCPE_OK;
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}
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/* IBC SMD I/O Dispatch */
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static int32 ibcsmddev(const int32 port, const int32 io, const int32 data)
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{
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if(io) {
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IBC_SMD_Write(port, (uint8)data);
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return 0;
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} else {
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return(IBC_SMD_Read(port));
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}
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}
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/* I/O Write to IBC SMD Registers */
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static uint8 IBC_SMD_Write(const uint32 Addr, uint8 cData)
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{
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switch(Addr & 7) {
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case IBC_SMD_REG_ARG0:
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switch (cData) {
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case 0x00:
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ibc_smd_info->error_reg = 0x0;
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break;
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case 0x01:
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ibc_smd_info->error_reg = 0x20;
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break;
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case IBC_SMD_CMD_READ_SECT:
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ibc_smd_info->error_reg = 0x30;
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break;
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default:
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ibc_smd_info->error_reg = 0x30;
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break;
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}
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ibc_smd_info->arg0 = cData;
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sim_debug(REG_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT
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" WR SMD_ARG0 0x%02x=0x%02x\n", PCX, Addr, cData);
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break;
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case IBC_SMD_REG_ARG1:
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ibc_smd_info->arg1 = cData;
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sim_debug(REG_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT
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" WR SMD_ARG1 0x%02x=0x%02x\n", PCX, Addr, cData);
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break;
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case IBC_SMD_REG_CMD:
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ibc_smd_info->cmd = cData;
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sim_debug(REG_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT
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" WR SMD_CMD 0x%02x=0x%02x\n", PCX, Addr, cData);
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IBC_SMD_doCommand();
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break;
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case IBC_SMD_REG_SEC:
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ibc_smd_info->sec = cData;
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sim_debug(REG_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT
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" WR SMD_SEC 0x%02x=0x%02x\n", PCX, Addr, cData);
|
|
break;
|
|
case IBC_SMD_REG_SECID:
|
|
sim_debug(REG_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT
|
|
" WR SECID 0x%02x=0x%02x\n", PCX, Addr, cData);
|
|
ibc_smd_info->secbuf_index = 0;
|
|
break;
|
|
case IBC_SMD_REG_DATA:
|
|
sim_debug(FIFO_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT
|
|
" WR FIFO 0x%02x=0x%02x\n", PCX, Addr, cData);
|
|
ibc_smd_info->sectbuf[ibc_smd_info->secbuf_index] = cData;
|
|
ibc_smd_info->secbuf_index++;
|
|
break;
|
|
default:
|
|
sim_debug(ERROR_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT
|
|
" Unhandled WR 0x%02x=0x%02x\n", PCX, Addr, cData);
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* I/O Read from IBC SMD Registers */
|
|
static uint8 IBC_SMD_Read(const uint32 Addr)
|
|
{
|
|
uint8 cData = 0xFF;
|
|
|
|
switch (Addr & 7) {
|
|
case IBC_SMD_REG_ERROR:
|
|
cData = ibc_smd_info->error_reg;
|
|
sim_debug(REG_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT
|
|
" RD ERROR 0x%02x=0x%02x\n", PCX, Addr, cData);
|
|
break;
|
|
case 0x1:
|
|
cData = 0x7f;
|
|
sim_debug(ERROR_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT
|
|
" RD Unknown 0x%02x=0x%02x\n", PCX, Addr, cData);
|
|
case IBC_SMD_REG_DATA:
|
|
cData = ibc_smd_info->sectbuf[ibc_smd_info->secbuf_index];
|
|
sim_debug(FIFO_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT
|
|
" RD DATA[0x%02x]=0x%02x\n", PCX, ibc_smd_info->secbuf_index, cData);
|
|
ibc_smd_info->secbuf_index++;
|
|
break;
|
|
case IBC_SMD_REG_STATUS:
|
|
cData = ibc_smd_info->status_reg;
|
|
sim_debug(REG_MSG, &ibc_smd_dev,DEV_NAME ": " ADDRESS_FORMAT
|
|
" RD STATUS 0x%02x=0x%02x\n", PCX, Addr, cData);
|
|
break;
|
|
default:
|
|
sim_debug(ERROR_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT
|
|
" Unhandled RD 0x%02x=0x%02x\n", PCX, Addr, cData);
|
|
break;
|
|
}
|
|
|
|
return (cData);
|
|
}
|
|
|
|
/* Validate that Cyl, Head, Sector are valid for the current
|
|
* disk drive geometry.
|
|
*/
|
|
static int IBC_SMD_Validate_CHSN(IBC_SMD_DRIVE_INFO* pDrive)
|
|
{
|
|
int status = SCPE_OK;
|
|
|
|
/* Check to make sure we're operating on a valid C/H/S/N. */
|
|
if ((pDrive->cur_cyl >= pDrive->ncyls) ||
|
|
(pDrive->cur_head >= pDrive->nheads) ||
|
|
(pDrive->cur_sect >= pDrive->nsectors))
|
|
{
|
|
/* Set error bit in status register. */
|
|
ibc_smd_info->status_reg |= IBC_SMD_STATUS_ERROR;
|
|
|
|
/* Set ID_NOT_FOUND bit in error register. */
|
|
ibc_smd_info->error_reg |= IBC_SMD_ERROR_ID_NOT_FOUND;
|
|
|
|
sim_debug(ERROR_MSG, &ibc_smd_dev,DEV_NAME "%d: " ADDRESS_FORMAT
|
|
" C:%d/H:%d/S:%d: ID Not Found (check disk geometry.)\n", ibc_smd_info->sel_drive, PCX,
|
|
pDrive->cur_cyl,
|
|
pDrive->cur_head,
|
|
pDrive->cur_sect);
|
|
|
|
status = SCPE_IOERR;
|
|
}
|
|
else {
|
|
/* Clear ID_NOT_FOUND bit in error register. */
|
|
ibc_smd_info->error_reg &= ~IBC_SMD_ERROR_ID_NOT_FOUND;
|
|
}
|
|
|
|
return (status);
|
|
}
|
|
|
|
/* Perform SMD Disk Command */
|
|
static t_stat IBC_SMD_doCommand(void)
|
|
{
|
|
t_stat r = SCPE_OK;
|
|
IBC_SMD_DRIVE_INFO* pDrive = &ibc_smd_info->drive[ibc_smd_info->sel_drive];
|
|
uint8 cmd = ibc_smd_info->cmd;
|
|
|
|
switch (cmd) {
|
|
case IBC_SMD_CMD_00:
|
|
break;
|
|
case IBC_SMD_CMD_SELECT_UNIT:
|
|
ibc_smd_info->sel_drive = (ibc_smd_info->arg0 >> 4) & 1;
|
|
sim_debug(CMD_MSG, &ibc_smd_dev, DEV_NAME "%d: " ADDRESS_FORMAT
|
|
" 0x%02x: Select Unit %d\n",
|
|
ibc_smd_info->sel_drive, PCX,
|
|
cmd, ibc_smd_info->arg0 >> 4);
|
|
break;
|
|
case IBC_SMD_CMD_SET_CYL: /* Set Cyl */
|
|
pDrive->cur_cyl = ibc_smd_info->arg0 << 8;
|
|
pDrive->cur_cyl |= ibc_smd_info->arg1;
|
|
sim_debug(CMD_MSG, &ibc_smd_dev, DEV_NAME "%d: " ADDRESS_FORMAT
|
|
" 0x%02x: Set Cylinder %d\n",
|
|
ibc_smd_info->sel_drive, PCX,
|
|
cmd, pDrive->cur_cyl);
|
|
break;
|
|
case IBC_SMD_CMD_SET_HEAD: /* Set Head */
|
|
pDrive->cur_head = ibc_smd_info->arg1;
|
|
sim_debug(CMD_MSG, &ibc_smd_dev, DEV_NAME "%d: " ADDRESS_FORMAT
|
|
" 0x%02x: Set Head %d\n",
|
|
ibc_smd_info->sel_drive, PCX,
|
|
cmd, pDrive->cur_head);
|
|
break;
|
|
case IBC_SMD_CMD_REZERO:
|
|
sim_debug(CMD_MSG, &ibc_smd_dev, DEV_NAME "%d: " ADDRESS_FORMAT
|
|
" 0x%02x: Rezero %d\n",
|
|
ibc_smd_info->sel_drive, PCX,
|
|
cmd, ibc_smd_info->arg1);
|
|
ibc_smd_info->status_reg = 0xd1;
|
|
break;
|
|
case IBC_SMD_CMD_READ_SECT:
|
|
case IBC_SMD_CMD_WRITE_SECT:
|
|
{
|
|
uint32 xfr_len;
|
|
uint32 file_offset;
|
|
|
|
pDrive->cur_sect = ibc_smd_info->sec;
|
|
ibc_smd_info->secbuf_index = 0;
|
|
ibc_smd_info->sectbuf[0] = (pDrive->cur_cyl >> 8) & 0xFF;
|
|
ibc_smd_info->sectbuf[1] = pDrive->cur_cyl & 0xFF;
|
|
ibc_smd_info->sectbuf[2] = pDrive->cur_head;
|
|
ibc_smd_info->sectbuf[3] = pDrive->cur_sect;
|
|
|
|
/* Abort the read/write operation if C/H/S/N is not valid. */
|
|
if (IBC_SMD_Validate_CHSN(pDrive) != SCPE_OK) break;
|
|
|
|
/* Calculate file offset */
|
|
file_offset = (pDrive->cur_cyl * pDrive->nheads * pDrive->nsectors); /* Full cylinders */
|
|
file_offset += (pDrive->cur_head * pDrive->nsectors); /* Add full heads */
|
|
file_offset += (pDrive->cur_sect); /* Add sectors for current request */
|
|
file_offset *= pDrive->sectsize; /* Convert #sectors to byte offset */
|
|
|
|
xfr_len = pDrive->sectsize;
|
|
|
|
if (0 != (r = sim_fseek((pDrive->uptr)->fileref, file_offset, SEEK_SET)))
|
|
break;
|
|
|
|
if (cmd == IBC_SMD_CMD_READ_SECT) { /* Read */
|
|
sim_debug(RD_DATA_MSG, &ibc_smd_dev, DEV_NAME "%d: " ADDRESS_FORMAT
|
|
" RD SECTOR C:%04d/H:%d/S:%04d, offset=%5x, len=%d\n",
|
|
ibc_smd_info->sel_drive, PCX,
|
|
pDrive->cur_cyl, pDrive->cur_head, pDrive->cur_sect,
|
|
file_offset, xfr_len);
|
|
if (sim_fread(&ibc_smd_info->sectbuf[4], 1, xfr_len, (pDrive->uptr)->fileref) != xfr_len) {
|
|
r = SCPE_IOERR;
|
|
}
|
|
}
|
|
else { /* Write */
|
|
sim_debug(WR_DATA_MSG, &ibc_smd_dev, DEV_NAME "%d: " ADDRESS_FORMAT
|
|
" WR SECTOR C:%04d/H:%d/S:%04d offset=%5x, len=%d\n",
|
|
ibc_smd_info->sel_drive, PCX,
|
|
pDrive->cur_cyl, pDrive->cur_head, pDrive->cur_sect,
|
|
file_offset, xfr_len);
|
|
if (sim_fwrite(&ibc_smd_info->sectbuf[4], 1, xfr_len, (pDrive->uptr)->fileref) != xfr_len) {
|
|
r = SCPE_IOERR;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
default:
|
|
sim_debug(ERROR_MSG, &ibc_smd_dev, DEV_NAME "%d: " ADDRESS_FORMAT
|
|
" UNKNOWN COMMAND 0x%02x\n",
|
|
ibc_smd_info->sel_drive, PCX,
|
|
cmd);
|
|
break;
|
|
}
|
|
return r;
|
|
}
|