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Finish migration for simulators to use generic clock co-scheduling and sim_activate_after for scheduled delays

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This commit is contained in:
Mark Pizzolato 2013-01-22 05:41:27 -08:00
parent 83c1d80194
commit 9fc6aa73d6
21 changed files with 35 additions and 46 deletions
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3
H316/h316_stddev.c
View file

@ -872,7 +872,8 @@ t_stat clk_svc (UNIT *uptr)
M[M_CLK] = (M[M_CLK] + 1) & DMASK; /* increment mem ctr */ M[M_CLK] = (M[M_CLK] + 1) & DMASK; /* increment mem ctr */
if (M[M_CLK] == 0) /* = 0? set flag */ if (M[M_CLK] == 0) /* = 0? set flag */
SET_INT (INT_CLK); SET_INT (INT_CLK);
sim_activate (&clk_unit, sim_rtc_calb (clk_tps)); /* reactivate */ sim_rtc_calb (clk_tps); /* recalibrate */
sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
return SCPE_OK; return SCPE_OK;
} }

7
HP2100/hp2100_defs.h
View file

@ -453,13 +453,6 @@ struct dib { /* Device information bl
extern uint32 SR; /* S register (for IBL) */ extern uint32 SR; /* S register (for IBL) */
extern uint32 dev_prl [2], dev_irq [2], dev_srq [2]; /* I/O signal vectors */ extern uint32 dev_prl [2], dev_irq [2], dev_srq [2]; /* I/O signal vectors */
/* Simulator state */
extern FILE *sim_deb;
extern FILE *sim_log;
extern int32 sim_step;
extern int32 sim_switches;
/* CPU functions */ /* CPU functions */
extern t_stat ibl_copy (const BOOT_ROM rom, int32 dev); extern t_stat ibl_copy (const BOOT_ROM rom, int32 dev);

3
I7094/i7094_clk.c
View file

@ -74,7 +74,8 @@ if ((clk_dev.flags & DEV_DIS) == 0) { /* clock enabled? */
WriteP (CLK_CTR, ctr); WriteP (CLK_CTR, ctr);
if (ctr == 0) /* overflow? req trap */ if (ctr == 0) /* overflow? req trap */
chtr_clk = 1; chtr_clk = 1;
sim_activate (uptr, sim_rtcn_calb (CLK_TPS, TMR_CLK)); /* reactivate unit */ sim_rtcn_calb (CLK_TPS, TMR_CLK); /* calibrate clock */
sim_activate_after (uptr, 1000000/CLK_TPS); /* reactivate unit */
} }
return SCPE_OK; return SCPE_OK;
} }

2
NOVA/nova_clk.c
View file

@ -140,7 +140,7 @@ if ( DEV_IS_BUSY(INT_CLK) )
DEV_UPDATE_INTR ; DEV_UPDATE_INTR ;
} }
t = sim_rtc_calb (clk_tps[clk_sel]); /* calibrate delay */ t = sim_rtc_calb (clk_tps[clk_sel]); /* calibrate delay */
sim_activate (&clk_unit, t); /* reactivate unit */ sim_activate_after (uptr, 1000000/clk_tps[clk_sel]); /* reactivate unit */
if (clk_adj[clk_sel] > 0) /* clk >= 60Hz? */ if (clk_adj[clk_sel] > 0) /* clk >= 60Hz? */
tmxr_poll = t * clk_adj[clk_sel]; /* poll is longer */ tmxr_poll = t * clk_adj[clk_sel]; /* poll is longer */
else else

2
PDP1/pdp1_clk.c
View file

@ -101,7 +101,7 @@ t_stat clk_svc (UNIT *uptr)
if (clk_dev.flags & DEV_DIS) /* disabled? */ if (clk_dev.flags & DEV_DIS) /* disabled? */
return SCPE_OK; return SCPE_OK;
tmxr_poll = sim_rtcn_calb (CLK_TPS, TMR_CLK); /* calibrate clock */ tmxr_poll = sim_rtcn_calb (CLK_TPS, TMR_CLK); /* calibrate clock */
sim_activate (&clk_unit, tmxr_poll); /* reactivate unit */ sim_activate_after (uptr, 1000000/CLK_TPS); /* reactivate unit */
clk_cntr = clk_cntr + CLK_CNTS; /* incr counter */ clk_cntr = clk_cntr + CLK_CNTS; /* incr counter */
if ((clk_cntr % CLK_C32MS) == 0) /* 32ms interval? */ if ((clk_cntr % CLK_C32MS) == 0) /* 32ms interval? */
dev_req_int (clk32ms_sbs); /* req intr */ dev_req_int (clk32ms_sbs); /* req intr */

2
PDP11/pdp11_cpu.c
View file

@ -253,8 +253,6 @@ typedef struct {
/* Global state */ /* Global state */
extern FILE *sim_log;
uint16 *M = NULL; /* memory */ uint16 *M = NULL; /* memory */
int32 REGFILE[6][2] = { {0} }; /* R0-R5, two sets */ int32 REGFILE[6][2] = { {0} }; /* R0-R5, two sets */
int32 STACKFILE[4] = { 0 }; /* SP, four modes */ int32 STACKFILE[4] = { 0 }; /* SP, four modes */

5
PDP11/pdp11_rq.c
View file

@ -699,7 +699,6 @@ static struct ctlrtyp ctlr_tab[] = {
}; };
extern int32 int_req[IPL_HLVL]; extern int32 int_req[IPL_HLVL];
extern int32 tmr_poll, clk_tps;
int32 rq_itime = 200; /* init time, except */ int32 rq_itime = 200; /* init time, except */
int32 rq_itime4 = 10; /* stage 4 */ int32 rq_itime4 = 10; /* stage 4 */
@ -1429,7 +1428,7 @@ if (cp->csta < CST_UP) { /* still init? */
sim_debug (DBG_REQ, dptr, "initialization complete\n"); sim_debug (DBG_REQ, dptr, "initialization complete\n");
cp->csta = CST_UP; /* we're up */ cp->csta = CST_UP; /* we're up */
cp->sa = 0; /* clear SA */ cp->sa = 0; /* clear SA */
sim_activate (dptr->units + RQ_TIMER, tmr_poll * clk_tps); sim_activate_after (dptr->units + RQ_TIMER, 1000000);
if ((cp->saw & SA_S4H_LF) if ((cp->saw & SA_S4H_LF)
&& cp->perr) rq_plf (cp, cp->perr); && cp->perr) rq_plf (cp, cp->perr);
cp->perr = 0; cp->perr = 0;
@ -1495,7 +1494,7 @@ MSC *cp = rq_ctxmap[uptr->cnum];
DEVICE *dptr = rq_devmap[uptr->cnum]; DEVICE *dptr = rq_devmap[uptr->cnum];
sim_debug (DBG_TRC, rq_devmap[cp->cnum], "rq_tmrsvc\n"); sim_debug (DBG_TRC, rq_devmap[cp->cnum], "rq_tmrsvc\n");
sim_activate (uptr, tmr_poll * clk_tps); /* reactivate */ sim_activate_after (uptr, 1000000); /* reactivate */
for (i = 0; i < RQ_NUMDR; i++) { /* poll */ for (i = 0; i < RQ_NUMDR; i++) { /* poll */
nuptr = dptr->units + i; nuptr = dptr->units + i;
if ((nuptr->flags & UNIT_ATP) && /* ATN pending? */ if ((nuptr->flags & UNIT_ATP) && /* ATN pending? */

2
PDP11/pdp11_stddev.c
View file

@ -444,7 +444,7 @@ clk_csr = clk_csr | CSR_DONE; /* set done */
if ((clk_csr & CSR_IE) || clk_fie) if ((clk_csr & CSR_IE) || clk_fie)
SET_INT (CLK); SET_INT (CLK);
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */ t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate (&clk_unit, t); /* reactivate unit */ sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
tmr_poll = t; /* set timer poll */ tmr_poll = t; /* set timer poll */
tmxr_poll = t; /* set mux poll */ tmxr_poll = t; /* set mux poll */
return SCPE_OK; return SCPE_OK;

8
PDP11/pdp11_tq.c
View file

@ -245,7 +245,6 @@ static struct drvtyp drv_tab[] = {
/* Data */ /* Data */
extern int32 int_req[IPL_HLVL]; extern int32 int_req[IPL_HLVL];
extern int32 tmr_poll, clk_tps;
uint32 tq_sa = 0; /* status, addr */ uint32 tq_sa = 0; /* status, addr */
uint32 tq_saw = 0; /* written data */ uint32 tq_saw = 0; /* written data */
@ -713,7 +712,7 @@ if (tq_csta < CST_UP) { /* still init? */
sim_debug (DBG_REQ, &tq_dev, "initialization complete\n"); sim_debug (DBG_REQ, &tq_dev, "initialization complete\n");
tq_csta = CST_UP; /* we're up */ tq_csta = CST_UP; /* we're up */
tq_sa = 0; /* clear SA */ tq_sa = 0; /* clear SA */
sim_activate (&tq_unit[TQ_TIMER], tmr_poll * clk_tps); sim_activate_after (&tq_unit[TQ_TIMER], 1000000);
if ((tq_saw & SA_S4H_LF) && tq_perr) if ((tq_saw & SA_S4H_LF) && tq_perr)
tq_plf (tq_perr); tq_plf (tq_perr);
tq_perr = 0; tq_perr = 0;
@ -786,7 +785,7 @@ UNIT *nuptr;
sim_debug(DBG_TRC, &tq_dev, "tq_tmrsvc\n"); sim_debug(DBG_TRC, &tq_dev, "tq_tmrsvc\n");
sim_activate (uptr, tmr_poll * clk_tps); /* reactivate */ sim_activate_after (uptr, 1000000); /* reactivate */
for (i = 0; i < TQ_NUMDR; i++) { /* poll */ for (i = 0; i < TQ_NUMDR; i++) { /* poll */
nuptr = tq_dev.units + i; nuptr = tq_dev.units + i;
if ((nuptr->flags & UNIT_ATP) && /* ATN pending? */ if ((nuptr->flags & UNIT_ATP) && /* ATN pending? */
@ -1193,10 +1192,9 @@ if ((uptr = tq_getucb (lu))) { /* unit exist? */
sts = tq_mot_valid (uptr, OP_POS); /* validity checks */ sts = tq_mot_valid (uptr, OP_POS); /* validity checks */
if (sts == ST_SUC) { /* ok? */ if (sts == ST_SUC) { /* ok? */
uptr->cpkt = pkt; /* op in progress */ uptr->cpkt = pkt; /* op in progress */
tq_rwtime = 2 * tmr_poll * clk_tps; /* 2 second rewind time */
if ((tq_pkt[pkt].d[CMD_MOD] & MD_RWD) && /* rewind? */ if ((tq_pkt[pkt].d[CMD_MOD] & MD_RWD) && /* rewind? */
(!(tq_pkt[pkt].d[CMD_MOD] & MD_IMM))) /* !immediate? */ (!(tq_pkt[pkt].d[CMD_MOD] & MD_IMM))) /* !immediate? */
sim_activate (uptr, tq_rwtime); /* use 2 sec rewind execute time */ sim_activate_after (uptr, 2000000); /* use 2 sec rewind execute time */
else { /* otherwise */ else { /* otherwise */
uptr->iostarttime = sim_grtime(); uptr->iostarttime = sim_grtime();
sim_activate (uptr, 0); /* use normal execute time */ sim_activate (uptr, 0); /* use normal execute time */

4
PDP11/pdp11_xq.c
View file

@ -2483,7 +2483,7 @@ t_stat xq_reset(DEVICE* dptr)
xq_csr_set_clr(xq, XQ_CSR_OK, 0); xq_csr_set_clr(xq, XQ_CSR_OK, 0);
/* start service timer */ /* start service timer */
sim_activate_abs(&xq->unit[1], (tmr_poll * clk_tps) / 4); sim_activate_after(&xq->unit[1], 250000);
/* stop the receiver */ /* stop the receiver */
eth_clr_async(xq->var->etherface); eth_clr_async(xq->var->etherface);
@ -2672,7 +2672,7 @@ t_stat xq_tmrsvc(UNIT* uptr)
} }
/* resubmit service timer */ /* resubmit service timer */
sim_activate(uptr, (tmr_poll * clk_tps) / 4); sim_activate_after(uptr, 250000);
return SCPE_OK; return SCPE_OK;
} }

8
PDP11/pdp11_xu.c
View file

@ -99,8 +99,7 @@
#include "pdp11_xu.h" #include "pdp11_xu.h"
extern int32 tmxr_poll, tmr_poll, clk_tps, cpu_astop; extern int32 tmxr_poll;
extern FILE *sim_log;
t_stat xu_rd(int32* data, int32 PA, int32 access); t_stat xu_rd(int32* data, int32 PA, int32 access);
t_stat xu_wr(int32 data, int32 PA, int32 access); t_stat xu_wr(int32 data, int32 PA, int32 access);
@ -583,7 +582,6 @@ t_stat xu_tmrsvc(UNIT* uptr)
{ {
CTLR* xu = xu_unit2ctlr(uptr); CTLR* xu = xu_unit2ctlr(uptr);
const ETH_MAC mop_multicast = {0xAB, 0x00, 0x00, 0x02, 0x00, 0x00}; const ETH_MAC mop_multicast = {0xAB, 0x00, 0x00, 0x02, 0x00, 0x00};
const int one_second = clk_tps * tmr_poll;
/* send identity packet when timer expires */ /* send identity packet when timer expires */
if (--xu->var->idtmr <= 0) { if (--xu->var->idtmr <= 0) {
@ -596,7 +594,7 @@ t_stat xu_tmrsvc(UNIT* uptr)
upd_stat16 (&xu->var->stats.secs, 1); upd_stat16 (&xu->var->stats.secs, 1);
/* resubmit service timer */ /* resubmit service timer */
sim_activate(uptr, one_second); sim_activate_after(uptr, 1000000);
return SCPE_OK; return SCPE_OK;
} }
@ -677,7 +675,7 @@ t_stat xu_sw_reset (CTLR* xu)
sim_clock_coschedule (&xu->unit[0], tmxr_poll); sim_clock_coschedule (&xu->unit[0], tmxr_poll);
/* start service timer */ /* start service timer */
sim_activate_abs(&xu->unit[1], tmr_poll * clk_tps); sim_activate_after (&xu->unit[1], 1000000);
} }
/* clear load_server address */ /* clear load_server address */

2
PDP18B/pdp18b_stddev.c
View file

@ -427,7 +427,7 @@ int32 t;
t = sim_rtc_calb (clk_tps); /* calibrate clock */ t = sim_rtc_calb (clk_tps); /* calibrate clock */
tmxr_poll = t; /* set mux poll */ tmxr_poll = t; /* set mux poll */
sim_activate (&clk_unit, t); /* reactivate unit */ sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
#if defined (PDP15) #if defined (PDP15)
clk_task_upd (FALSE); /* update task timer */ clk_task_upd (FALSE); /* update task timer */
#endif #endif

2
PDP8/pdp8_clk.c
View file

@ -146,8 +146,8 @@ int32 t;
dev_done = dev_done | INT_CLK; /* set done */ dev_done = dev_done | INT_CLK; /* set done */
int_req = INT_UPDATE; /* update interrupts */ int_req = INT_UPDATE; /* update interrupts */
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */ t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate (&clk_unit, t); /* reactivate unit */
tmxr_poll = t; /* set mux poll */ tmxr_poll = t; /* set mux poll */
sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
return SCPE_OK; return SCPE_OK;
} }

3
VAX/vax610_stddev.c
View file

@ -399,9 +399,10 @@ int32 t;
if (clk_csr & CSR_IE) if (clk_csr & CSR_IE)
SET_INT (CLK); SET_INT (CLK);
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */ t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate (&clk_unit, t); /* reactivate unit */ sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
tmr_poll = t; /* set tmr poll */ tmr_poll = t; /* set tmr poll */
tmxr_poll = t * TMXR_MULT; /* set mux poll */ tmxr_poll = t * TMXR_MULT; /* set mux poll */
AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
return SCPE_OK; return SCPE_OK;
} }

3
VAX/vax630_stddev.c
View file

@ -335,9 +335,10 @@ int32 t;
if (clk_csr & CSR_IE) if (clk_csr & CSR_IE)
SET_INT (CLK); SET_INT (CLK);
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */ t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate (&clk_unit, t); /* reactivate unit */ sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
tmr_poll = t; /* set tmr poll */ tmr_poll = t; /* set tmr poll */
tmxr_poll = t * TMXR_MULT; /* set mux poll */ tmxr_poll = t * TMXR_MULT; /* set mux poll */
AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
return SCPE_OK; return SCPE_OK;
} }

5
VAX/vax730_stddev.c
View file

@ -182,7 +182,6 @@ int32 tmr_use_100hz = 1; /* use 100Hz for timer *
int32 clk_tps = 100; /* ticks/second */ int32 clk_tps = 100; /* ticks/second */
int32 tmxr_poll = CLK_DELAY * TMXR_MULT; /* term mux poll */ int32 tmxr_poll = CLK_DELAY * TMXR_MULT; /* term mux poll */
int32 tmr_poll = CLK_DELAY; /* pgm timer poll */ int32 tmr_poll = CLK_DELAY; /* pgm timer poll */
int32 todr_reg = 0; /* TODR register */
struct todr_battery_info { struct todr_battery_info {
uint32 toy_gmtbase; /* GMT base of set value */ uint32 toy_gmtbase; /* GMT base of set value */
uint32 toy_gmtbasemsec; /* The milliseconds of the set value */ uint32 toy_gmtbasemsec; /* The milliseconds of the set value */
@ -302,7 +301,6 @@ DEVICE tto_dev = {
UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE+UNIT_FIX, sizeof(TOY)), CLK_DELAY };/* 100Hz */ UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE+UNIT_FIX, sizeof(TOY)), CLK_DELAY };/* 100Hz */
REG clk_reg[] = { REG clk_reg[] = {
{ DRDATAD (TODR, todr_reg, 32, "time-of-day register"), PV_LEFT },
{ DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT }, { DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT },
{ DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO }, { DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO },
{ DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT }, { DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT },
@ -798,8 +796,9 @@ tmr_nicr = val;
t_stat clk_svc (UNIT *uptr) t_stat clk_svc (UNIT *uptr)
{ {
tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */ tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate (&clk_unit, tmr_poll); /* reactivate unit */ sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */ tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
if ((tmr_iccs & TMR_CSR_RUN) && tmr_use_100hz) /* timer on, std intvl? */ if ((tmr_iccs & TMR_CSR_RUN) && tmr_use_100hz) /* timer on, std intvl? */
tmr_incr (TMR_INC); /* do timer service */ tmr_incr (TMR_INC); /* do timer service */
return SCPE_OK; return SCPE_OK;

4
VAX/vax750_stddev.c
View file

@ -181,7 +181,6 @@ int32 tmr_use_100hz = 1; /* use 100Hz for timer *
int32 clk_tps = 100; /* ticks/second */ int32 clk_tps = 100; /* ticks/second */
int32 tmxr_poll = CLK_DELAY * TMXR_MULT; /* term mux poll */ int32 tmxr_poll = CLK_DELAY * TMXR_MULT; /* term mux poll */
int32 tmr_poll = CLK_DELAY; /* pgm timer poll */ int32 tmr_poll = CLK_DELAY; /* pgm timer poll */
int32 todr_reg = 0; /* TODR register */
struct todr_battery_info { struct todr_battery_info {
uint32 toy_gmtbase; /* GMT base of set value */ uint32 toy_gmtbase; /* GMT base of set value */
uint32 toy_gmtbasemsec; /* The milliseconds of the set value */ uint32 toy_gmtbasemsec; /* The milliseconds of the set value */
@ -302,7 +301,6 @@ DEVICE tto_dev = {
UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE+UNIT_FIX, sizeof(TOY)), CLK_DELAY };/* 100Hz */ UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE+UNIT_FIX, sizeof(TOY)), CLK_DELAY };/* 100Hz */
REG clk_reg[] = { REG clk_reg[] = {
{ DRDATAD (TODR, todr_reg, 32, "time-of-day register"), PV_LEFT },
{ DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT }, { DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT },
{ DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO }, { DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO },
{ DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT }, { DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT },
@ -794,7 +792,7 @@ tmr_nicr = val;
t_stat clk_svc (UNIT *uptr) t_stat clk_svc (UNIT *uptr)
{ {
tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */ tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate (&clk_unit, tmr_poll); /* reactivate unit */ sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */ tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */ AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
if ((tmr_iccs & TMR_CSR_RUN) && tmr_use_100hz) /* timer on, std intvl? */ if ((tmr_iccs & TMR_CSR_RUN) && tmr_use_100hz) /* timer on, std intvl? */

4
VAX/vax780_stddev.c
View file

@ -198,7 +198,6 @@ int32 tmr_use_100hz = 1; /* use 100Hz for timer *
int32 clk_tps = 100; /* ticks/second */ int32 clk_tps = 100; /* ticks/second */
int32 tmxr_poll = CLK_DELAY * TMXR_MULT; /* term mux poll */ int32 tmxr_poll = CLK_DELAY * TMXR_MULT; /* term mux poll */
int32 tmr_poll = CLK_DELAY; /* pgm timer poll */ int32 tmr_poll = CLK_DELAY; /* pgm timer poll */
int32 todr_reg = 0; /* TODR register */
struct todr_battery_info { struct todr_battery_info {
uint32 toy_gmtbase; /* GMT base of set value */ uint32 toy_gmtbase; /* GMT base of set value */
uint32 toy_gmtbasemsec; /* The milliseconds of the set value */ uint32 toy_gmtbasemsec; /* The milliseconds of the set value */
@ -318,7 +317,6 @@ DEVICE tto_dev = {
UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE+UNIT_FIX, sizeof(TOY)), CLK_DELAY };/* 100Hz */ UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE+UNIT_FIX, sizeof(TOY)), CLK_DELAY };/* 100Hz */
REG clk_reg[] = { REG clk_reg[] = {
{ DRDATAD (TODR, todr_reg, 32, "time-of-day register"), PV_LEFT },
{ DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT }, { DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT },
{ DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO }, { DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO },
{ DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT }, { DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT },
@ -612,7 +610,7 @@ tmr_nicr = val;
t_stat clk_svc (UNIT *uptr) t_stat clk_svc (UNIT *uptr)
{ {
tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */ tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate (&clk_unit, tmr_poll); /* reactivate unit */ sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */ tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */ AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
if ((tmr_iccs & TMR_CSR_RUN) && tmr_use_100hz) /* timer on, std intvl? */ if ((tmr_iccs & TMR_CSR_RUN) && tmr_use_100hz) /* timer on, std intvl? */

6
VAX/vax860_stddev.c
View file

@ -207,7 +207,6 @@ int32 tmr_use_100hz = 1; /* use 100Hz for timer *
int32 clk_tps = 100; /* ticks/second */ int32 clk_tps = 100; /* ticks/second */
int32 tmxr_poll = CLK_DELAY * TMXR_MULT; /* term mux poll */ int32 tmxr_poll = CLK_DELAY * TMXR_MULT; /* term mux poll */
int32 tmr_poll = CLK_DELAY; /* pgm timer poll */ int32 tmr_poll = CLK_DELAY; /* pgm timer poll */
int32 todr_reg = 0; /* TODR register */
struct todr_battery_info { struct todr_battery_info {
uint32 toy_gmtbase; /* GMT base of set value */ uint32 toy_gmtbase; /* GMT base of set value */
uint32 toy_gmtbasemsec; /* The milliseconds of the set value */ uint32 toy_gmtbasemsec; /* The milliseconds of the set value */
@ -344,7 +343,6 @@ DEVICE tto_dev = {
UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE+UNIT_FIX, sizeof(TOY)), CLK_DELAY };/* 100Hz */ UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE+UNIT_FIX, sizeof(TOY)), CLK_DELAY };/* 100Hz */
REG clk_reg[] = { REG clk_reg[] = {
{ DRDATAD (TODR, todr_reg, 32, "time-of-day register"), PV_LEFT },
{ DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT }, { DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT },
{ DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO }, { DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO },
{ DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT }, { DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT },
@ -749,9 +747,9 @@ tmr_nicr = val;
t_stat clk_svc (UNIT *uptr) t_stat clk_svc (UNIT *uptr)
{ {
tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */ tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate (&clk_unit, tmr_poll); /* reactivate unit */ sim_activate_after (&clk_unit, 1000000/clk_tps); /* reactivate unit */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */ tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
todr_reg = todr_reg + 1; /* incr TODR */ AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
if ((tmr_iccs & TMR_CSR_RUN) && tmr_use_100hz) /* timer on, std intvl? */ if ((tmr_iccs & TMR_CSR_RUN) && tmr_use_100hz) /* timer on, std intvl? */
tmr_incr (TMR_INC); /* do timer service */ tmr_incr (TMR_INC); /* do timer service */
return SCPE_OK; return SCPE_OK;

1
scp.h
View file

@ -152,6 +152,7 @@ extern DEVICE *sim_dflt_dev;
extern int32 sim_interval; extern int32 sim_interval;
extern int32 sim_switches; extern int32 sim_switches;
extern int32 sim_quiet; extern int32 sim_quiet;
extern int32 sim_step;
extern FILE *sim_log; /* log file */ extern FILE *sim_log; /* log file */
extern FILEREF *sim_log_ref; /* log file file reference */ extern FILEREF *sim_log_ref; /* log file file reference */
extern FILE *sim_deb; /* debug file */ extern FILE *sim_deb; /* debug file */

5
sim_timer.c
View file

@ -1437,6 +1437,11 @@ else
uptr->next = sim_clock_cosched_queue; uptr->next = sim_clock_cosched_queue;
sim_clock_cosched_queue = uptr; sim_clock_cosched_queue = uptr;
pthread_mutex_unlock (&sim_timer_lock); pthread_mutex_unlock (&sim_timer_lock);
#else
int32 t;
t = sim_activate_time (sim_clock_unit);
return sim_activate (uptr, t? t - 1: interval);
#endif #endif
} }
return SCPE_OK; return SCPE_OK;