- Timers that schedule their ticks with sim_activate_after() now operate
consistently without having to be the single timer used by a simulator.
- Simulators which dynamically enable the operation of a clock when one
wasn't previously wasn't enabled will disable the internal calibrated timer.
- Generate reasonable messages when presented with erroneous throttle input.
- Add throttling recalibration logic if only if target rate drift exceeds 5%
When sim_brk_type_desc isn't populated, the matching breakpoint switches
and matching address are displayed. Fix to use the optional VM provided
address formatting function sim_vm_sprint_addr.
Add discussion of the recommended handling of instruction history
recording. Also recommendations for read and write breakpoints to
cover cases such as I/O registers.
Also extended the optional VM supplied routines to include sim_vm_sprint_addr.
Simulators which provide sim_vm_fprint_addr should also provide
sim_vm_sprint_addr with sim_vm_fprint_addr reworked to leverage
sim_vm_sprint_addr internally. sim_vm_sprint_addr is currently only used by
sim_brk_message() which is an API which a simulator may choose to use if
it supports multiple breakpoint types,
These changes cure a number of issues in RSTS/E, which is more
sensitive to details of emulation than most:
1. Additional KMC opcodes supported for ROMI
2. MCLR now initializes the CSRs per the spec
3. MCLR and ROMI are processed immediately at CSR write rather than
being deferred, because these actions are implemented in the device
hardware rather than in the microprogram.
- Add detailed error message info while parsing breakpoint commands
- Properly limit breakpoint class values to reflect available mask bits
- Declare globally sim_brk_npc since it is a documented API
- Revise simh_breakpoints.doc to reflect current behavior
Previously, the history would always use a register value as source or
destination as if the mode were zero, even when it wasn't. Also, now
the destination value reflects the destination after instruction
execution rather than before.
Rather than use a simh event to increment/decrement the counter register
for each 'clock cycle', compute the time the interrupt will eventually fire
and schedule a single event to deal with that. If the clock counter is
referenced before the interrupt fires, interpolate the value based on the
number of instructions that have actually been executed.
sim_activate_after() is used here, and the time value for the scheduled
activation is a uint32 representing microseconds. The range of values
that the PCLK can programmatically specify could be large enough
to exceed an uint32 when number of microseconds is converted to
a count of instructions. This is an issue that has minimal consequences,
but should be addressed internal to the implementation of
sim_activate_after().
