Adds 6850 DCD status latch to M2SIO devices.
Adds vector interrupt support to M2SIO devices.
Removes CTS inactive transmit disable from PMMI device.
Adds IMSAI-style programmed output to CPU/SIO devices.
SET CPU PO will display "PO: AREG" upon an "OUT 0FFH"
instruction.
SET CPU NOPO will disable the function (default).
Corrects problem with Mode 0 interrupts.
When the CPU receives an interrupt, it pushes the current
program counter on the stack. The current implementation
of Mode 0 was performing interrupt processing after fetching
the next opcode from RAM, which also increases the PC by 1.
This caused PC+1 to be pushed on the stack. The interrupt
processing is now done prior to fetching the next opcode,
preserving the correct program counter.
* CMake build infrastructure
The squashed commit that builds and packages releases for the SIMH
simulator suite with CMake, version 3.14 or newer.
See README-CMake.md for documentation.
After adding the sim_clock_precalibrate_commands, the PC was not zero
at the sim> prompt after loading altairz80.
Set CPU_S to zero in cpu_reset to address this issue.
While working on the AltairZ80 documentation, I found some problems
with the SOL20 registers and fixed some formatting issues.
Added static and "vdm1_" prefix to "charset" variable in s100_vdm1.c
This PR adds support for the Processor Technology VDM-1 display adapter and Sol-20 computer system. The VDM-1 was integrated into the Sol-20 but has been separated out into its own device.
This PR adds the following devices to the AltairZ80 simulator:
VDM1 - Processor Technology VDM-1 display adapter
SOL20 - Processor Technology SOL20 with SOLOS ROMs
SOL20K - SOL20 Keyboard (callback from VDM1)
SOL20T - SOL20 Tape (reads/writes cassette file images)
SOL20S - SOL20 Serial Port (TMXR capable)
SOL20P - SOL20 Printer Port (TMXR capable)
Used to initialize SCP timers to prevent problems during simulator startup
when THROTTLE is being used.
/*
* This sequence of instructions is a mix that mimics
* a resonable instruction set that is a close estimate
* to the calibrated result.
*/
static const char *cpu_clock_precalibrate_commands[] = {
"-m 100 LXI H,200H",
"-m 103 MVI B,0",
"-m 105 DCR B",
"-m 106 MOV M,B",
"-m 107 INX H",
"-m 108 JNZ 0105H",
"-m 10B JMP 0100H",
"PC 100",
NULL};
Proper initialization of the ADCS6 unit data structure depended on the
ADCS6 device being enabled. In cases where the ADCS6 unit was not
enabled, non-debug builds may crash on some host platforms depending on
compiler/memory layout.
As pointed out by @markpizz , the only allowed macro to initialize UNIT
structures is the UDATA macro.
Setting additional UNIT data structure items should be set through explicit
initialization code in the DEVICE reset routine.
AltairZ80 uses 0 for the VM-specific HLT instruction stop code.
SCP defines SCPE_OK as 0.
SCP uses 0 to mean all errors ("ON ERROR").
The command "ON 0" will generate "%SIM-ERROR: Invalid argument: 0".
This PR changes the HALT stop code from 0 to 5.
* Add support for 8259 interrupt controller.
* Add support for Cromemco and Tarbell Monitor ROMs.
* To allow port 0xFE to be used by the simh_dev.
* Use the CPU's SR instead of a SCP300F-specific one.
* 9513 RTC support.
