The SDS tape unit can't do write reverse (no magtape tape can, afaik).
So instead of testing for a particular write subop, the code just tests
that the write was done in BCD mode.
This is closer to how the hardware works.
Most history routines defined a local sim_eval of the proper length, but the
erroneous ones were fixed length machines that defined an integer variable
instead of an integer array of length 1. The VAX used the global sim_eval.
The changes follow the VAX practice.
These changes facilitate more robust parameter type checking and helps
to identify unexpected coding errors.
Most simulators can now also be compiled with a C++ compiler without
warnings.
Additionally, these changes have also been configured to facilitate easier
backporting of simulator and device simulation modules to run under the
simh v3.9+ SCP framework.
When stuffing the LOGOUT command to a pseudo-teletype, the command script processing program CCP encountered a race condition because the MUX timing was too slow. The pseudo-teletype did not reliably log off as desired. Cutting the event wait time in half fixed the problem.
The simulator stops when reading past EOF on the paper tape device's attached disk file (or if no file is attached to this device). The SDS timesharing system is capable of processing an end-of-record interrupt in these circumstances, resulting in proper error reporting to the user program that is reading paper tape.
This reverts commit 5551a0dd9c.
The original idea was that the state being put into simh registers would be required to have all useful information available when remote console executed commands. These steps were taken from the code that sim_instr() executed as it was exiting. After this change was made it was realized that once a remote console command executed it might change state that directly affected instruction execution. To solve this, the logic that executes before the instructions in sim_instr() would then need to be executed whenever the event dispatch processing completed. This approach is messy, burdensome and potentially a lot of overhead for every event dispatch even though almost none of the event dispatches would be for remote console command execution. A completely different approach was suggested by J. David Bryan. That alternative approach would be to have remote console commands execute outside of the sim_instr() routine. Thus allowing the existing prelude and postlude code in sim_instr() to be performed naturally and let the remote console activities run in the same context as all other simh commands. Recent changes to scp and sim_console implement this alternative approach and thus these original changes are completely irrelevant and are thus being removed.
Improper implementation of the OVT and OTO instructions. OV is always zero or one, so the Boolean AND in the original if statement would always fail. Also, these instructions are supposed to skip if overflow is not set, the opposite of the way it was coded.
1. In sim_instr, if an Unauthorized Memory Access trap occurs, the code was enforcing the 940 Reference Manual's admonition that:
"The instruction in the trap location must be a MARK PLACE AND BRANCH (BRM) instruction."
Normally there is a BRM TRAPM in location 041, but when exploring a memory trap, the TSS monitor code at CEX (SMEM) temporarily puts a BRU CEX2+1 in location 041.
Clearly the hardware allows BRU in the trap transfer vector, because the system uses that feature. Change simulator to allow BRM or BRU in Unauthorized Memory Access Trap vector word in location 041.
2. Page 17 of the 940 reference manual specifies special actions when the target address of a BRU, BRX, BRM or BRR instruction cannot be accessed because it's not in the memory map. The simulator was not doing this, causing TRAPM to operate with the address of the BR? instruction instead of its target address. The result was to allocate a page of zeros, which then trapped when the branch completed and transferred to a HLT instruction.
By modifying the code in sds_cpu.c to provide the correct trap address, monitor code TRAPM does not allocate a page, and instead allows any user-defined trap to fire off. This fixes the problem with DDT, which relies on this trap to then map in the DDT SBREK page to 34000 and then complete the transfer to it for command processing.
While debugging DDT subsystem of 940 time-sharing system, discovered NOP opcode used with indirection, non-zero operand address and tag field. I_V_OPO (opcode only) was redundant with I_V_NPN (no operand) opcode classes. Convert I_V_OPO to new "operand optional" class and use it for NOP, and add code to detect presence or absence of operand or tag for this class for machine code display and entry.
The existing conversion tables were for the 930 and earlier models of SDS computers. The SDS 940 altered these tables. This change selects the appropriate table based upon the current CPU mode -- whether operating as a 930 or a 940. See Appendix A of both the 930 and 940 reference manuals for detailed character conversion information. Correct 930 ASCII to internal table for ASCII input value 0140.
When reading from paper tape on the W channel and writing the drum on the E channel, intermittent errors and premature end-of-record were observed. The TST_XFR macro was failing to properly quality that a data character was available for a particular device and channel. Thus, a data ready condition for the drum would cause a bad transfer for another active device on a different channel.
1. Treat the SBRM SysPOP like the BRM opcode for calling a subroutine.
2. If the -a (atomic) switch is present with a BRM or SBRM instruction, place a breakpoint at EA+1 rather than EA, since the return link is placed at EA (BRM) or at *EA (SBRM) with subroutine execution commencing at EA+1.
Allow -f switch with Next to move forward in code.
Allow -a switch with Next for "atomic" behavior that excludes interrupts for all instructions.
Update sds_doc.doc to describe the new behavior.
Add -f switch ("force") to the Next command to set the temporary breakpoints regardless of instruction type. This is useful at
the bottom of loops or to avoid going off into unrelated code should an interrupt or memory paging trap occur.
The three CPU modes -- normal, monitor and user were represented by two binary flags (nml_mode and usr_mode). The code is simpler and easier to read if the three modes are represented by one three-valued variable, cpu_mode. In addition, record the CPU mode in the instruction history record, and add the mode to the history display.
In addition, add an optional flag to the SET CPU HISTORY=n command to *not* record instructions executed in a particular CPU mode. Flags are -n, -m and -u for normal, monitor and user mode respectively. For example, SET -m CPU HISTORY=n will only record instructions executed in normal or user mode, and will not record instructions executed in monitor mode. This change aids user-mode program debugging by not filling the history with monitor-mode service functions and interrupt activity.
Add new instruction class -- I_V_SPP for SYSPOPs and definitions for the standard ones provided by the time sharing system. Add instruction name annotation to the opc_val array.
The goals here being to simplify calling code while getting consistent output delivered everywhere it may be useful.
Modified most places which explicitly used sim_log or merely called printf to now avoid doing that and merely call sim_printf().
Instead of conditionally compiling in bootstrap support depending upon attached channel, determine dynamically based on RAD's current assignment to channel W or channel E. This allows using "set rad channel=W" for purposes of bootstrapping, and then relocating the RAD with "set rad channel=E" for running a TSS monitor that expects to find the RAD on channel E.
Normally the RAD is connected to the E channel and there is no bootstrap capability (because of hardwired WIM instruction). However, for completeness, add code to allow booting from the RAD if it is connected to the W channel. Add RAD_CHAN definition to define which controller the RAD is connected to.
Improve parentheses in bootstrap code that allows an optional word count (while also permitting the canonical bootstrap sequence).
The canonical boot sequence uses WIM 0,2 in location 5 and an initial load address in location 11 (and in the X register). This is limiting for devices like RAD that do not report an end-of-file, or for paper tape that report EOF too late and cause the WIM to fail. A simple load address in location 11, with bit 9 set to satisfy the BRX, doesn't do any word counting. The BRX always branches back to location 5.
This change allows a true negative word count to be placed in location 11 to work with a WIM XXXXX,2 where XXXXX is one location past the region to be loaded by the boot sequence. XXXXX plus the negative count in location 11 (buf[3]+buf[7]) initially points to the first location to be loaded, and the BRX will not branch when the word count is exhausted (register X=0) allowing the branch to the start address to be executed.
Old allowable boot sequence:
location 2 = WIM 12,2
location 3 = BRX 2
location 4 = LDX 11
location 5 = WIM 0,2
location 6 = SKS 21000
location 7 = BRX 5
location 10 = BRU Transfer Address
location 11 = Load address with bit 9 set to force BRX to branch
New allowable boot sequence:
location 2 = WIM 12,2
location 3 = BRX 2
location 4 = LDX 11
location 5 = WIM [end load address + 1],2
location 6 = SKS 21000
location 7 = BRX 5
location 10 = BRU Transfer Address
location 11 = Negative count to number of words to load
Received better fix from Mark Pizzolato for the problem of having 120 clock interrupts per second instead of 60. Tested for several hours and verified that wall-clock time matches TSS monitor time.
Clock is running twice as fast as it should -- 120 interrupts per second instead of 60. Cannot find problem in initialization or calibration or count-down code, so for now, divide rtc_tps by 2 prior to invoking sim_rtcn_calb. Now 940 Executive reports wall-clock time advancing at proper rate.
Breakpoint logic now allows four execution-type breakpoints:
-E as before, break if PC equals address, unqualified by mode
-M break if PC equals address and machine is in monitor mode
-N break if PC equals address and machine is in normal (SDS 930) mode
-U break if PC equals address and machine is in user mode
SDS internal ASCII differs from standard external ASCII. Alter the examine and deposit functions with -A switch to properly adjust between the two forms. Also allow strings rather than one-character per word as was in the original code. Clean up six-bit character display logic to use a loop.
Remove superfluous trailing blanks from lines in file.
rad_adjda was setting sba=0 at a sector boundary, which did not reflect that the first 12-bits of the sector have already be read or written. Must set sba=1 for proper addressing.
Removed superfluous end-of-line spaces from file.
1. In pot_fork, the permanently asserted interrupt, the interrupt bits were assigned in the wrong order -- bit 8 is interrupt 0 and bit 23 is interrupt 017 in each group of 16. Also, the group number was incorrectly calculated -- need to subtract 0200 before dividing by 020.
2. In case 3 of EOM and SKS when in SDS mode, it does not dispatch properly. The device table is set for Genie mode. Add test for device 077 in SDS mode and switch to device 1, which is Mux in Genie mode.
3. Add test to PIN to verify that scanner is locked before returning PIN data.
4. Mux should not queue a new interrupt for a flag type if it is already queued and pending for a different channel. If do so, when the CPU clears the interrupt, the second interrupt is lost.
5. If POT specifies interrupt but no Tx character present, queue a Tx interrupt immediately if the transmitter is not active. This technique is used by the 940 monitor to start output of the transmit character buffer.
6. Per the 940 reference manual, after servicing the highest priority interrupt on a particular channel, the scanner should look at all other channels before looking for additional interrupt types on the first channel. Change scanner to always resume scan with the Rx interrupt on the next channel from where the scanner paused.
Also removed superfluous trailing blanks from lines in file.
From actual monitor code, sequence used to read drum:
EOD* 10000B Alert Interlace
GDAC3: EOD 14202 I/O control mode EOD (mode 1)
A=0 High order memory address bits
Hicount=2 (Word count=04000=2KW)
POT GDBCL+2 Low-order memory address bits.
RRF (EOD 2226) Read RAD file (mode 0)
Problem is that RRF is clearing the interlace information saved by the previous POT and sets up for a new POT. That is, in sds_io.c, mod 0 of op_eomd always assumes that a POT will follow if the channel is C or greater. Have to add tests of chan_flag. If interlace is active, do not capture new information from this EOM/EOD.
Also removed superfluous trailing blanks from lines in file.
The single-instruction Clock Pulse interrupt (75 octal) may be a MIN or SKR instruction. The function rtc_inst increments (MIN) or decrements (SKR) the operand and tests for zero and generates a Clock Sync interrupt (74 octal) if so. However, the SDS 940 reference manual is incorrect; in the SKR case, the test should be if the result is negative.
1. When transitioning from monitor to user mode with the trap enabled, the trap was latching the monitor address of the transferring branch rather than the user-mode address of the branch target.
2. When executing a BRU, BRX or BRM in monitor mode, if the effective address was in user mode, the code neglected to transition the machine to user mode. And after doing so, it is necessary to check for an armed monitor-to-user trap.
Also removed superfluous trailing blanks from lines in file.
