This should work on all byte addressable host systems using GCC/clang to build.
The QEMU slirp code has been pried out of QEMU and stubs have been created to solve where the current slirp is entangled with the QEMU code. Ths slirp/simh directory contains all the necessary include and glue files to make this useful. Everything in the slirp directory is unmodified QEMU code.
This version of slirp is a fork from QEMU Version 2.4.0.1 slirp implementation
Taken from commit id of 474590efc51f262fb5d81ca417d510cb7fb7a914
in the qemu repository git://repo.or.cz/qemu/ar7.git
Thanks to Fabrice Bellard.
Vector values contained in device information blocks are the true bus relative vector values. CPU specific biased vector values are produced by the respective vector fetching logic and vector values are limited to 9 bits with <1:0> = 0 as specified in both the Unibus and Qbus documents.
Prior logic attempted to load the desired file from the current default directory and if that failed wrote the in memory boot code image to the desired file and then retried the desired load..
A user can still explicitly load a ROM image with a "LOAD -R romfile.bin" command prior to a BOOT attempt if they want to test or otherwise run with a different ROM.
Update description of DEVICE, UNIT, and REG. Correct a number of
typos and formatting glitches. Add description of UNIT_IDLE,
REG_UNIT. Add some missing details in fprint_sym and
sim_vm_is_subroutine_call. Document command matching rule.
cygwin now includes development packages for the SDL2 and SDL video
libraries (libSDL2-devel and libSDL-devel). Adjust makefile to find the
libSDL2.dll.a or libSDL.dll.a library.
Altered the calling sequences to fprint_sym and parse_sym in ex_reg and dep_reg to merge user-defined register flags with the radix in the addr parameter. This allows the print and parse routines to identify the register or determine how it is to be handled. These are called in lieu of the standard print and parse routines if a register has REG_VMIO or at least one user-defined flag set.
Using SDL2 the draw operations are performed in a separate thread and thus the data must be cached while the request is passed to the separate thread while control returns to the caller.
Problem was the console storage output buffer was masked with a WMASK instead of a BMASK (it is only a 8 bit register).
Also, the input interrupt processing cleared the output interrupt state instead of the input interrupt state. This would only be a problem when interrupts are actually used instead of polled I/O.
hp2100_ipl.c:
- Exposed "ipl_edtdelay" via a REG_HIDDEN register to allow user tuning
of the EDT delay that works around a race condition in the HP
2000/Access Time-Shared BASIC system.
- Corrected typos in comments and strings.
- Merged SIMH 3.x and 4.x socket calls via conditionals, so that the
module may be compiled for either version.
hp2100_mux.c:
- Corrected a typo in the RTS macro definition.
hp2100_sys.c:
- Added a cast to int for the parameter to "isspace" to avoid a compiler
warning.
hp2100_bugfixes.txt
- Added a description of the IPL hidden register fix.
VAX 11/.750 Boot ROM code makes non-longword memory references to MassBus and Unibus register space. Minor changes were necessary to allow this behavior which was architecturally undefined behavior, but had real code which depended on it.
Added a BOOTDEV option to the CPU to reflect the 4 position boot device selection switch on real VAX 11/750 hardware.
The UBA750 initial state started with the UBA map registers validly mapping the first 256KB of RAM to Unibus space.
Added simulated PCS/WCS memory which boot code on some operating systems (Ultrix and other BSD derived systems) automatically loaded on the VAX 11/750. PCS/WCS was also automatically loaded by the newer versions of the BOOT ROMs.
Overruns can happen on simulated MUX lines using TCP since multiple characters can arrive in a single network packet. Overruns still are reported if previous input characters haven't been read within 500ms. Edmund Marr reported this problem.
The source file to be updated provides emulation of the North Star DD
floppy disk controller. The proposed change steps the head only when the
step bit in the order byte transitions from 1 to 0. This is the way the
actual hardware functions. Previously, the emulation would step any time
an order was issued and the step bit was 1. This behavior caused some
original software (e.g., Lifeboat CP/M 2.2) to end up on an incorrect
track.
