This PR adds support for the Processor Technology VDM-1 display adapter and Sol-20 computer system. The VDM-1 was integrated into the Sol-20 but has been separated out into its own device.
This PR adds the following devices to the AltairZ80 simulator:
VDM1 - Processor Technology VDM-1 display adapter
SOL20 - Processor Technology SOL20 with SOLOS ROMs
SOL20K - SOL20 Keyboard (callback from VDM1)
SOL20T - SOL20 Tape (reads/writes cassette file images)
SOL20S - SOL20 Serial Port (TMXR capable)
SOL20P - SOL20 Printer Port (TMXR capable)
Used to initialize SCP timers to prevent problems during simulator startup
when THROTTLE is being used.
/*
* This sequence of instructions is a mix that mimics
* a resonable instruction set that is a close estimate
* to the calibrated result.
*/
static const char *cpu_clock_precalibrate_commands[] = {
"-m 100 LXI H,200H",
"-m 103 MVI B,0",
"-m 105 DCR B",
"-m 106 MOV M,B",
"-m 107 INX H",
"-m 108 JNZ 0105H",
"-m 10B JMP 0100H",
"PC 100",
NULL};
- Builds x86 and x64 regular snapshots.
x64: Mon Wed Fri
x86: Tue Thu Sat
ARM: Mon Thu Sun (ARM not enabled)
- Builds x64 on closed pull request, Release
- Manual trigger allows selection of ref, platform,
architecture, config, disposition
- Releases and daily snapshots are deployed automagically
- VS Project 2022 files updated for ARM, but not setup for
cross-builds (BuildROMs) or tested on ARM (no hardware)
- Fix makefile tests for cygwin
Proper initialization of the ADCS6 unit data structure depended on the
ADCS6 device being enabled. In cases where the ADCS6 unit was not
enabled, non-debug builds may crash on some host platforms depending on
compiler/memory layout.
This is to prevent confusion when questions come in.
Plus, a little advertising never hurts.
The version output will now include "Open SIMH", and the version
number will be '4.1.*' rather than '4.0.*'.
Start of support for PiDP10 front panel.
Moved interrupt checking from check_irq_level to clear_interrupt.
Pending interrupts now saved in IOB_PI.
Cleanup of KL10 Timer interrupts.
Minor code cleanup.
When the 3B2 simulator was set to allow idling, there was significant
clock drift related to the primary timer unit. It turns out that the
simulator was using `AIO_SET_INTERRUPT_LATENCY` and `sim_rtcn_tick_ack`
incorrectly. They are not needed with the structure of system timers in
the 3B2 architecture.
As pointed out by @markpizz , the only allowed macro to initialize UNIT
structures is the UDATA macro.
Setting additional UNIT data structure items should be set through explicit
initialization code in the DEVICE reset routine.
AltairZ80 uses 0 for the VM-specific HLT instruction stop code.
SCP defines SCPE_OK as 0.
SCP uses 0 to mean all errors ("ON ERROR").
The command "ON 0" will generate "%SIM-ERROR: Invalid argument: 0".
This PR changes the HALT stop code from 0 to 5.
* Add support for 8259 interrupt controller.
* Add support for Cromemco and Tarbell Monitor ROMs.
* To allow port 0xFE to be used by the simh_dev.
* Use the CPU's SR instead of a SCP300F-specific one.
* 9513 RTC support.
