folkert van heusden
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2838695fb6
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debugger enhancements
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2022-11-10 13:26:45 +01:00 |
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folkert van heusden
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2fd1da58bb
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Merge branch 'master' into d_i
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2022-11-10 09:13:22 +01:00 |
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folkert van heusden
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5b1d75fb74
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disassembler fix (SWAB)
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2022-07-03 19:34:39 +02:00 |
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folkert van heusden
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0d7cbe3da9
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replaced addresses by defines
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2022-06-28 17:58:04 +02:00 |
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folkert van heusden
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2717799df4
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- fix for busy loop in console_posix (due to poll with 0ms timeout)
- disable kw11-l interrupt when emulation is not running
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2022-06-26 01:41:58 +02:00 |
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folkert van heusden
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42fc44b206
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page written bit only when written
double trap: use stack from 000004
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2022-06-24 20:03:32 +02:00 |
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folkert van heusden
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ad44232120
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double trap handling (work in progress)
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2022-06-19 15:31:26 +02:00 |
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folkert van heusden
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f4d991e86a
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Debugging
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2022-06-19 02:33:06 +02:00 |
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folkert van heusden
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7e1f7a8102
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redundant check
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2022-06-19 00:31:23 +02:00 |
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folkert van heusden
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31edf022cc
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RTI/RTT shall not change the PSW in user/supervisor mode
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2022-06-18 18:05:31 +02:00 |
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folkert van heusden
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51670ef199
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double traps
odd addressing trap
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2022-06-18 12:10:23 +02:00 |
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folkert van heusden
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7427ddc226
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PDR-len calculation fix(?)
do not update MMR0 when already set
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2022-06-18 11:42:40 +02:00 |
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folkert van heusden
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9d55740a0f
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SR0 errors by KKTBD0 fixed
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2022-06-18 08:48:29 +02:00 |
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folkert van heusden
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015ef244b8
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Merge branch 'master' into d_i
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2022-06-18 08:05:40 +02:00 |
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folkert van heusden
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4b788bb620
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Set bit 12 to 1 if trap
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2022-06-17 20:48:16 +02:00 |
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folkert van heusden
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89bca61148
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Bugfix: must look at bits 15/14/13 of MMR0
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2022-06-17 20:18:28 +02:00 |
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folkert van heusden
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d101ab3088
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MMR2 is locked when bits 0160000 in MMR0 are set (either of them)
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2022-06-17 19:51:53 +02:00 |
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folkert van heusden
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a9090e0acd
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show instruction count together with the mips-count
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2022-06-16 22:35:28 +02:00 |
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folkert van heusden
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c033268ee6
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Do not update W-bit when MMR0 is touched
Include exception number in logging
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2022-06-16 20:10:55 +02:00 |
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folkert van heusden
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0f78c37d84
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11/34 does not have bit 9 in MMR0
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2022-06-16 19:33:39 +02:00 |
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folkert van heusden
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0b18a5e4cc
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mm fixes
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2022-06-15 12:08:13 +02:00 |
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folkert van heusden
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81dc6d8924
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trap: read from D-space
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2022-06-13 21:53:59 +02:00 |
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folkert van heusden
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a460aa9d82
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PSW handling fixes
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2022-06-12 22:34:09 +02:00 |
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folkert van heusden
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9b3cb02064
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ADC/SBC fixes
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2022-06-12 22:13:04 +02:00 |
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folkert van heusden
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ff8f8be672
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ADC v flag fix
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2022-06-12 22:08:11 +02:00 |
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folkert van heusden
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710cf2bbad
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SBC for registers fix
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2022-06-12 22:00:45 +02:00 |
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folkert van heusden
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5ea14bddd3
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micro opt
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2022-06-11 19:29:06 +02:00 |
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folkert van heusden
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c20b9554d8
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streamlined get/set_Register
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2022-06-11 16:02:55 +02:00 |
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folkert van heusden
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7a9ccc651b
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logging facility - remove \n & reduce logging when not needed
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2022-06-11 09:44:00 +02:00 |
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folkert van heusden
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92d96a4d43
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logging facility
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2022-06-11 09:35:30 +02:00 |
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folkert van heusden
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dd3b1d9d66
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Renamed 'FIXME' to 'TODO' for a few cases: they're really TODOs and
lgtm.com complains about them.
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2022-06-11 08:59:07 +02:00 |
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folkert van heusden
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2d7f202530
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use of iterate after erase
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2022-06-11 08:47:24 +02:00 |
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folkert van heusden
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8d8af7153b
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Event handling (stop/interrupt) clean-up
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2022-06-10 20:59:36 +02:00 |
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folkert van heusden
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ee8d772426
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MFPI/MTPI require special handling for SP
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2022-06-10 20:30:18 +02:00 |
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folkert van heusden
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94181e94bd
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KW11-L
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2022-06-09 19:10:22 +02:00 |
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folkert van heusden
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3466cefbed
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MUL: clear V-flag and correct setting of result in registers
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2022-06-09 14:46:20 +02:00 |
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folkert van heusden
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bb6e599813
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HI/LO were swapped for MUL
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2022-06-09 14:02:49 +02:00 |
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folkert van heusden
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8e6eae64da
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instructions with two registers to work on are R[nr] and R[nr | 1] (not + 1)
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2022-06-09 12:39:52 +02:00 |
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folkert van heusden
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f4b7f0a3cd
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fix for ASHC on negative value
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2022-06-09 09:46:20 +02:00 |
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folkert van heusden
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d243364743
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ASHC: set V flag, correction for shift value
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2022-06-09 08:48:30 +02:00 |
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folkert van heusden
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5770bdc263
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ASH now bug-free?
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2022-06-08 22:09:11 +02:00 |
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folkert van heusden
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782095555d
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ASH fixes
- lower 6 bit are addressing mode + register number
- fix for sign-bit extension
To do: flags
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2022-06-03 18:46:04 +02:00 |
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folkert van heusden
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649516df18
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MARK versus MTPS
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2022-06-03 11:48:06 +02:00 |
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folkert van heusden
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1e748d3d37
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All write-access to 0177776 should not affect the flag registers
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2022-06-02 22:22:05 +02:00 |
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folkert van heusden
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5a77604127
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MOV(B) to 0177776 should not set the flags
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2022-06-02 21:42:55 +02:00 |
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folkert van heusden
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3df8aea12c
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Split 'step()' into _a and _b so to prevent confusing disassembly of an
instruction that won't be executed anyway due to an interrupt/trap.
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2022-04-30 12:16:19 +02:00 |
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folkert van heusden
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5a4057f6a1
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trap: always register deltas unless error set in MMR0
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2022-04-14 17:50:18 +02:00 |
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folkert van heusden
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1673548c37
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MMR1/2
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2022-04-13 23:38:46 +02:00 |
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folkert van heusden
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a90547c3d1
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micro-opt
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2022-04-13 20:53:54 +02:00 |
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folkert van heusden
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841d0d9720
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RESET clears the interrupt-queue
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2022-04-13 17:48:49 +02:00 |
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