Coverity flagged one magtape simulator for having fewer case breakouts
than the range of MTSE_x errors, after they were expanded for
MTSE_LEOT (listed as "V4 compatibility") and MTSE_RUNAWAY (for
Dave Bryan's implementation of erase and erase gap).
According to Dave, it turns out that MTSE_RUNAWAY can only be
returned if the magtape simulator supports and implements a density
specification and the ERASE function. The simulators Bob Supnik wrote
don't meet that criteria, so the expanded errors can't be returned.
Simply add a "default" case to the map logic returning SCPE_IERR for
unexpected cases.
Historically this functionality was reimplemented within each
DEVICE simulator often with slightly different implementations
and inconsistencies. Solving this globally within SCP required
changes in many places, but should henceforth be reasonably
managed.
As discussed in #1034
Array REGister definitions have been made consistent by passing the
name of the array object. This allows proper sizing assessment
to occur in the register validation logic.
Some previously described array REGister initializers were not really
arrays. Some were structures and others were merely pointers to
someplace in memory that it was desirable to view as a scalar array.
Structures or other blob data should now use SAVEDATA. Virtual
arrays intended to be interpret some part of memory as scalar data
now use VBRDATA initializers.
Array REGister definitions have been made consistent by passing the
address of the whole array object. This allows proper sizing assessment
to occur in the register validation logic.
Some devices have dedicated units that perform various independent
functions (often timing) that are independent of the primary device unit
which is ATTACHed. This services to help interpret debug information
that may be produced.
These changes facilitate more robust parameter type checking and helps
to identify unexpected coding errors.
Most simulators can now also be compiled with a C++ compiler without
warnings.
Additionally, these changes have also been configured to facilitate easier
backporting of simulator and device simulation modules to run under the
simh v3.9+ SCP framework.
Vector values contained in device information blocks are the true bus relative vector values. CPU specific biased vector values are produced by the respective vector fetching logic and vector values are limited to 9 bits with <1:0> = 0 as specified in both the Unibus and Qbus documents.
Here's a PDP11 SIMH bug as old as the simulator itself: the reset_cpu routine sets the PS to 340 (interrupts disabled). This causes some versions of Lunar Lander not to work. In fact, the initial state of the PS is not architecturally standardized:
04: cleared (from schematics)
05: cleared (from manual)
20: cleared (from schematics)
34: cleared (from schematics), set to 340 on boot?
40: cleared (from schematics)
44: cleared on init, set to 340 on boot (from schematics, manual)
45: cleared (from schematics)
60: cleared (from schematics)
70: cleared (from schematics)
T11: set to 340 (from spec)
LSI11, F11: 4 mode behavior (from memory on power recovery, cleared on GO, 340 on boot, mode 3 undefined)
J11: 4 mode behavior (from memory on power recovery, cleared on GO, 340 on boot, 340 on jump to custom PROM)
The story seems to be this. All non-VLSI PDP11s used TTL chips to implement the PS, either discrete flip-flops, or 4b registers, or both.
Starting with the first system, the 11/20, they were wired clear on the processor INIT signal (power-up or front panel START switch), so that all internal state started as 0. This worked fine, because START also reset the Unibus and cleared all interrupt enables. So even though the processor was as IPL = 0, no interrupts were possible. Then along came the LSI11...
The LSI11 implemented a line-time clock with NO INTERRUPT DISABLE. Thus, if IPL was left at 0 and a bootstrap routine from a slow device was started (e.g., a floppy drive), the clock would tick, and an interrupt would occur, before the bootstrap routine finished. Because no vectors were set up, the processor would crash. So the LSI11 started the practice, carried over to all later PDP11 VLSI chips, of setting the PS to 340 before jumping to a boot ROM.
The T11 did this in all modes of startup, because its only startup behavior was to jump to a "boot" routine. It did not have a console of any kind.
Accordingly, it appears that the cpu_reset routine needs to set the PS based on the processor model. Further, all boot routines need to set the PS to 0 or 340 based on the processor model. (It's probably safe for boot routines just to set the PS to 340, but it's not technically
accurate.)
Show IOSPACE doesn't always get the number of devices right due to device creativity.
o The distinction between UNIT and DEVICE has blurred
o MUX devices merge several physical devices into one device/unit
o Dynamic device sizing has made things more volatile.
This edit solves the problem for SHOW IOSPACE by adding an (optional) word to the DIBs.
The word contains the amount of IO space consumed by each instance of the physical device that's being emulated.
E.G., if it's a DZ11, the device is the DZ11 module, or 8 lines, even though the MUX device may support 32.
This enables SHOW IOSPACE to determine the number of physical devices being emulated, which is what folks need when configuring software. The word may have other uses - in a generic dynamic device sizing routine - which is why the amount of IOSPACE per device was chosen rather than the 'number of physical devices.'
The edit should not make any existing device regress. If the new word (ulnt) is zero (not initialized), SHOW IOSPACE will default to the number of units in the device, or if there's no device (CPUs), 1 as before. If it is present, the number of devices is the calculated as total allocation/allocation-per-device.
The edit updates all the devices that seem to require this treatment, and all the processors that define the UNIBUS/QBUS DIBs.
Fixed auto configure bugs which didn't allow Fixed CSR Addresses or Fixed Vectors to be set using the auto configure information.
Fixed display of address and vectors to indicate that the assigned address and/or vector is in the floating set.
Added extended definitions to the auto configure table to reflect all known potential static and floating and static addresses as of VMS V5.5-2
Changed the name of the VAX 11/780 console floppy device name to RXC from RX (which collides with a Unibus name for the RX11).
- Removed flawed logic which assumed that sim_interval was meaningful when referenced by an asynchronous thread.
- Adjust the event_time of events removed from the asynch queue to account for the average time spent on the queue before the event was noticed by the instruction execution thread.
- Added a sim_activate_notbefore function which specifies an rtime which is the earliest time the event should fire.
- Changed the 'wakeup from idle' logic to force an immediate asynch queue check if the wakeup was not due to a timeout (i.e. it was due to an asynch queue insertion).
- Fixed the descrip.mms to build asynchronous support on AXP and IA64 VMS with kernel threads enabled
