Add consistent debug options to track TODR activities and the values which
are set. Debug data will display the VMS time related to the values set and
read.
Previously sim_interval was adjusted by 1 plus the total number of bytes
referenced in string instructions (SCANC, SPANC, LOCC, SKPC, CMPC3,
CMPC5, MOVC3, MOVC5). Since the amount of data that a string
instruction can reference is arbitrarily large (32bit size), the adjustment
to sim_interval could be ridiculously excessive. This can result in wild
variances in clock calibration when large string data are referenced.
Various boot ROM activities, including testing the Interval Timers, presume
that ROM based code execute instructions at 1 instruction per usec.
To accommodate this, we not only throttle memory accesses to ROM space,
but we also use instruction based delays when the interval timers are
programmed from the ROM for short duration delays.
The original idling model called sim_idle() within the context of a scheduled
event running on the CPU unit. The overhead of scheduling and the related
dispatch serve no specific purpose.
Meanwhile, the 'work' involved in determing if idling is possible is about
equivalent to the work of executing an additional instruction. Therefore
sim_idle is invoked with an argument which causes the sim_interval to be
adjusted by 1 on each call that doesn't actually perform an idle sleep. This
adjustment keeps the calibrated instruction execution rate consistent with
other purely non-idle instruction mixes.
Clock ticks for these simulatrs are performed by programmatic setup of the
interval timer device (TMR) and have nothing to do with the TODR which
increments at 100Hz, but doesn't generate ticks to the simulated system.
Removing pseudo ticking of the TODR improves simulator behavior
when idling. As previously implement, the timing of the TODR and TMR
ticks weren't aligned and and idle simulator would have to wake up to
service both tick activities.
The real hardware has a TODR which changes every 10ms to reflect changes
to wall clock time. This is already completely achieved by referencing the
host system time whenever the TODR register is referenced. No need for
to simulate pseudo ticking.
The real interval timer hardware generates ticks a the rate specifically
programmed in the interval timer device registers. The common cases
programmed the ticks at 10 ms intervals (100Hz), but real operating systems
exist which programmed ticks at 16667 usecs (60Hz).
When the TODR device (CLK) is attached to a state file, it operates in OS
agnostic mode. This file can now be ported between hosts with different
endianness and work consistently to track the time of year.
Additionally, the VAX and VAX750 TODR values now properly don't
progress when they have zero values (or when they overflow back to zero).
Asynchronous clocks are now built for all simulators which are built with
SIM_ASYNCH_IO defined. The default behavior has asynchronous clocks
disabled since this is still experimental, but it can be enabled with
SET TIMER ASYNC.
Catchup clock ticks are now available, but since they're experimental,
they aren't enabled by default. Catchup ticks are only available if the
simulators clock device calls sim_rtcn_tick_ack to acknowledge processing
of clock ticks. The VAX simulators have been modified to leverage this.
Catchup clock ticks can be enabled with SET TIMER CATCHUP
Additionally, an idle threshold is provided which can be used to
influence when clock calibration may be suppressed. The default is not
to suppress calibration activities.
The various timer behaviors are visible with the SHOW TIMER command.
The state of the operating timer facilities is visible with: SHOW CLOCK
Timer events which are queued are visible with the SHOW QUEUE command.
Polling is now done at least every 500ms even if the prior input
character hasn't been processed yet. This allows ^E to provide a way
to exit a simulator which otherwise isn't reading from the console port.
- Previous changes made to support 32V's 60HZ clock tick introduced changes
which didn't properly handle increments and interrupt generation while single
stepping the timer.
- The icr_rd routine returned an incorrect value when interpolation was
necessary due to a missing cast when converting from double to uint32.
- Properly start the timer from the current state of the interval count register
when the timer was previously stopped.
Recent enhancements to idle/infinite loop detection generalized handling
of detecting 'loop to self' cases. This was done without considering that
some instructions have side effects (i.e. change other state like the stack
pointer) and thus aren't merely loop to self cases.
This problem was reported in #315
These changes facilitate more robust parameter type checking and helps
to identify unexpected coding errors.
Most simulators can now also be compiled with a C++ compiler without
warnings.
Additionally, these changes have also been configured to facilitate easier
backporting of simulator and device simulation modules to run under the
simh v3.9+ SCP framework.
