Removing pseudo ticking of the TODR improves simulator behavior
when idling. As previously implement, the timing of the TODR and TMR
ticks weren't aligned and and idle simulator would have to wake up to
service both tick activities.
The real hardware has a TODR which changes every 10ms to reflect changes
to wall clock time. This is already completely achieved by referencing the
host system time whenever the TODR register is referenced. No need for
to simulate pseudo ticking.
The real interval timer hardware generates ticks a the rate specifically
programmed in the interval timer device registers. The common cases
programmed the ticks at 10 ms intervals (100Hz), but real operating systems
exist which programmed ticks at 16667 usecs (60Hz).
When the TODR device (CLK) is attached to a state file, it operates in OS
agnostic mode. This file can now be ported between hosts with different
endianness and work consistently to track the time of year.
Additionally, the VAX and VAX750 TODR values now properly don't
progress when they have zero values (or when they overflow back to zero).
Asynchronous clocks are now built for all simulators which are built with
SIM_ASYNCH_IO defined. The default behavior has asynchronous clocks
disabled since this is still experimental, but it can be enabled with
SET TIMER ASYNC.
Catchup clock ticks are now available, but since they're experimental,
they aren't enabled by default. Catchup ticks are only available if the
simulators clock device calls sim_rtcn_tick_ack to acknowledge processing
of clock ticks. The VAX simulators have been modified to leverage this.
Catchup clock ticks can be enabled with SET TIMER CATCHUP
Additionally, an idle threshold is provided which can be used to
influence when clock calibration may be suppressed. The default is not
to suppress calibration activities.
The various timer behaviors are visible with the SHOW TIMER command.
The state of the operating timer facilities is visible with: SHOW CLOCK
Timer events which are queued are visible with the SHOW QUEUE command.
Polling is now done at least every 500ms even if the prior input
character hasn't been processed yet. This allows ^E to provide a way
to exit a simulator which otherwise isn't reading from the console port.
- Previous changes made to support 32V's 60HZ clock tick introduced changes
which didn't properly handle increments and interrupt generation while single
stepping the timer.
- The icr_rd routine returned an incorrect value when interpolation was
necessary due to a missing cast when converting from double to uint32.
- Properly start the timer from the current state of the interval count register
when the timer was previously stopped.
Recent enhancements to idle/infinite loop detection generalized handling
of detecting 'loop to self' cases. This was done without considering that
some instructions have side effects (i.e. change other state like the stack
pointer) and thus aren't merely loop to self cases.
This problem was reported in #315
These changes facilitate more robust parameter type checking and helps
to identify unexpected coding errors.
Most simulators can now also be compiled with a C++ compiler without
warnings.
Additionally, these changes have also been configured to facilitate easier
backporting of simulator and device simulation modules to run under the
simh v3.9+ SCP framework.
When a mix of Massbus devices are configured with some enabled and
others disabled, the MBA's need to be allocated and properly configured
in the desired preferred order (RP, TU, RS). On the PDP11, this interacts
with auto-configure since the RH devices are visible in the Unibus I/O
page. On the PDP11 the second Massbus device can only be configured
if the TM device is disabled since the auto-configure assigned vectors
overlap for RHB and TM.
Problem originally reported in #301.
Observations made about NVR behavior on real hardware:
1) Aligned writes only affect a single RAM location
without regard to the size of write, so no double
pumping on writes.
2) Unaligned (offset 3) writes do nothing without regard to size of the write
3) Unaligned (offset 1) write 0 to the next higher NVR RAM location.
4) Longword aligned and Unaligned (offset 3) reads return the same NVR RAM
value in the the upper and lower words of the result.
5) Unaligned (offset 1) reads reference the next higher NVR RAM cell for
word and longword reads.
- Fix write behavior to match hardware.
- Fix read behavior to double pump word values for all unaligned word and longword
reads.
- In VMS mode, the day and month have to behave correctly to map the
current day of year to the equivalent day of year in 1982
- The month maintained and returned by the watch chip has January as 1
while the tm_mon field in the 'struct tm' has 0 for January.
A user could change the contents of the PSL via a DEPOSIT command.
If the resulting PSL indicates Interrupt Stack and IPL is 0, then this is
equivalent to MTPR #0,#IPL which is explicitly described as "undefined"
When a MTPR #0,#IPL is performed, the VAX chip microcode doesn't check,
neither does the 780 microcode. Nothing bad will happen immediately,
however when an interrupt occurs, the saved PSL will now contain IPL 0
and Interrupt Stack. This combination will cause the REI dismissing the
taken interrupt to fail. To avoid a user manually creating this via
a DEPOSIT command or to potentially detect this condition while stepping
through instructions this check refuses to execute when the PSL is
invalid. This change merely provides an explanation.
On page 5-37 of the VAX SRM (DEC standard 32), the REI pseudo-code defines
exactly what a legal PSL looks like. The check at the beginning of
sim_instr is a direct implementation of that check, intended to prevent
the user from creating an inconsistent PSL through the simulator console.
In a VAX chip, the console code would exit by a genuine REI, and any
illegal value created by the user would cause a system stop (return to the
console).
On page 5-43, the revision history notes that in rev 8 of chapter 5,
MTPR #0,#IPL was made undefined. Because MXPR is privileged, and the
general assumption was that VMS knew what it was doing, no one realized
the potential inconsistency that MTPR #IPL could create until it was
too late. "Undefined" allows any behavior, up to and including blowing up
the system.
This is invoked with STEP -R nnn, or CONT -R. Execution will continue
across any new subroutines which are called and stop after the current
routine executes a RET or RSB instruction.
SET CPU IDLE={OS{:n}} where n is the idle stability delay
which is also the clock calibration delay.
A -D switch on a SHOW -D CPU IDLE command will
display the stability delay as will a SHOW CLOCK command.
