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390 commits

Author SHA1 Message Date
folkert van heusden
050b0f7ea5 clean-up 2023-03-13 13:33:57 +01:00
folkert van heusden
4618c86ffa Revert "RTI/RTT shall not change the PSW in user/supervisor mode" 
This reverts commit 31edf022cc.

Seems to break at least XXDP EKBAD0.BIC
 2023-03-13 10:10:13 +01:00
folkert van heusden
08d8c75d58 - readPhysical 
- initialize psw to 0 to match pypdp (for diff)
- SUB instruction V-flag may have been incorrect
- MFPI/MTPI flags
- MFPI readPhysical
- bootloader from pypdp (for diff)
 2023-03-12 22:32:53 +01:00
folkert van heusden
60210e4f82 Merge fix for 2fd1da58bb 
The fault in that merge caused two sets of pc/psw to be pushed on the
stack.
 2023-03-12 13:19:54 +01:00
folkert van heusden
d68a5af55e writePhysical 2023-03-11 21:54:18 +01:00
folkert van heusden
6f20ce864f disassembler fix 2022-11-11 21:50:30 +01:00
folkert van heusden
2838695fb6 debugger enhancements 2022-11-10 13:26:45 +01:00
folkert van heusden
2fd1da58bb Merge branch 'master' into d_i 2022-11-10 09:13:22 +01:00
folkert van heusden
5b1d75fb74 disassembler fix (SWAB) 2022-07-03 19:34:39 +02:00
folkert van heusden
0d7cbe3da9 replaced addresses by defines 2022-06-28 17:58:04 +02:00
folkert van heusden
2717799df4 - fix for busy loop in console_posix (due to poll with 0ms timeout) 
- disable kw11-l interrupt when emulation is not running
 2022-06-26 01:41:58 +02:00
folkert van heusden
42fc44b206 page written bit only when written 
double trap: use stack from 000004
 2022-06-24 20:03:32 +02:00
folkert van heusden
ad44232120 double trap handling (work in progress) 2022-06-19 15:31:26 +02:00
folkert van heusden
f4d991e86a Debugging 2022-06-19 02:33:06 +02:00
folkert van heusden
7e1f7a8102 redundant check 2022-06-19 00:31:23 +02:00
folkert van heusden
31edf022cc RTI/RTT shall not change the PSW in user/supervisor mode 2022-06-18 18:05:31 +02:00
folkert van heusden
51670ef199 double traps 
odd addressing trap
 2022-06-18 12:10:23 +02:00
folkert van heusden
7427ddc226 PDR-len calculation fix(?) 
do not update MMR0 when already set
 2022-06-18 11:42:40 +02:00
folkert van heusden
9d55740a0f SR0 errors by KKTBD0 fixed 2022-06-18 08:48:29 +02:00
folkert van heusden
015ef244b8 Merge branch 'master' into d_i 2022-06-18 08:05:40 +02:00
folkert van heusden
4b788bb620 Set bit 12 to 1 if trap 2022-06-17 20:48:16 +02:00
folkert van heusden
89bca61148 Bugfix: must look at bits 15/14/13 of MMR0 2022-06-17 20:18:28 +02:00
folkert van heusden
d101ab3088 MMR2 is locked when bits 0160000 in MMR0 are set (either of them) 2022-06-17 19:51:53 +02:00
folkert van heusden
a9090e0acd show instruction count together with the mips-count 2022-06-16 22:35:28 +02:00
folkert van heusden
c033268ee6 Do not update W-bit when MMR0 is touched 
Include exception number in logging
 2022-06-16 20:10:55 +02:00
folkert van heusden
0f78c37d84 11/34 does not have bit 9 in MMR0 2022-06-16 19:33:39 +02:00
folkert van heusden
0b18a5e4cc mm fixes 2022-06-15 12:08:13 +02:00
folkert van heusden
81dc6d8924 trap: read from D-space 2022-06-13 21:53:59 +02:00
folkert van heusden
a460aa9d82 PSW handling fixes 2022-06-12 22:34:09 +02:00
folkert van heusden
9b3cb02064 ADC/SBC fixes 2022-06-12 22:13:04 +02:00
folkert van heusden
ff8f8be672 ADC v flag fix 2022-06-12 22:08:11 +02:00
folkert van heusden
710cf2bbad SBC for registers fix 2022-06-12 22:00:45 +02:00
folkert van heusden
5ea14bddd3 micro opt 2022-06-11 19:29:06 +02:00
folkert van heusden
c20b9554d8 streamlined get/set_Register 2022-06-11 16:02:55 +02:00
folkert van heusden
7a9ccc651b logging facility - remove \n & reduce logging when not needed 2022-06-11 09:44:00 +02:00
folkert van heusden
92d96a4d43 logging facility 2022-06-11 09:35:30 +02:00
folkert van heusden
dd3b1d9d66 Renamed 'FIXME' to 'TODO' for a few cases: they're really TODOs and 
lgtm.com complains about them.
 2022-06-11 08:59:07 +02:00
folkert van heusden
2d7f202530 use of iterate after erase 2022-06-11 08:47:24 +02:00
folkert van heusden
8d8af7153b Event handling (stop/interrupt) clean-up 2022-06-10 20:59:36 +02:00
folkert van heusden
ee8d772426 MFPI/MTPI require special handling for SP 2022-06-10 20:30:18 +02:00
folkert van heusden
94181e94bd KW11-L 2022-06-09 19:10:22 +02:00
folkert van heusden
3466cefbed MUL: clear V-flag and correct setting of result in registers 2022-06-09 14:46:20 +02:00
folkert van heusden
bb6e599813 HI/LO were swapped for MUL 2022-06-09 14:02:49 +02:00
folkert van heusden
8e6eae64da instructions with two registers to work on are R[nr] and R[nr | 1] (not + 1) 2022-06-09 12:39:52 +02:00
folkert van heusden
f4b7f0a3cd fix for ASHC on negative value 2022-06-09 09:46:20 +02:00
folkert van heusden
d243364743 ASHC: set V flag, correction for shift value 2022-06-09 08:48:30 +02:00
folkert van heusden
5770bdc263 ASH now bug-free? 2022-06-08 22:09:11 +02:00
folkert van heusden
782095555d ASH fixes 
- lower 6 bit are addressing mode + register number
- fix for sign-bit extension

To do: flags
 2022-06-03 18:46:04 +02:00
folkert van heusden
649516df18 MARK versus MTPS 2022-06-03 11:48:06 +02:00
folkert van heusden
1e748d3d37 All write-access to 0177776 should not affect the flag registers 2022-06-02 22:22:05 +02:00