From page 6-6 of DEC STD 032 (the VAX architecture spec):
"Execution of MTPR src, #PR$_ASTLVL with src<31:0> GEQU 5 results in
UNDEFINED behavior. The preferred implementation is to cause a reserved
operand fault." MicroVAX II, CVAX, and Rigel all conform to the preferred
behavior, as does the current simulator, which was written from the CVAX
microcode. NVAX masks to 3b and does not take an exception on a value
GEQU 5.
The 1982 Architecture Handbook describes ASTLVL as a 3b register, with
src<31:3> ignored/read as zero, and exceptions taken on values GEQU 5.
The780 microcode masks the input value to 3b before doing the GEQU 5 test.
The ASTLVL test needs to be model specific.
I suspect the behavior became undefined when MicroVAX II simplified the
original test to save a microword. I do not see how the code fragment Matt
references could work on a MicroVAX II, which was supported under 4.5.
Perhaps the device Matt mentions couldn't exist on a MicroVAX II?
For those who wants the gory details... uVAX, CVAX, and Rigel do an
unsigned compare on the unmasked src and the constant 5. Carry out
means reserved operand. Overflow is ignored. So an input of 0x80000002 -
0x00000005 (done in the data path as 0x80000002 + 0xFFFFFFFB) generates overflow (ignored) and carry out.
# Conflicts:
# VAX/vaxmod_defs.h
These changes facilitate more robust parameter type checking and helps
to identify unexpected coding errors.
Most simulators can now also be compiled with a C++ compiler without
warnings.
Additionally, these changes have also been configured to facilitate easier
backporting of simulator and device simulation modules to run under the
simh v3.9+ SCP framework.
When a mix of Massbus devices are configured with some enabled and
others disabled, the MBA's need to be allocated and properly configured
in the desired preferred order (RP, TU, RS). On the PDP11, this interacts
with auto-configure since the RH devices are visible in the Unibus I/O
page. On the PDP11 the second Massbus device can only be configured
if the TM device is disabled since the auto-configure assigned vectors
overlap for RHB and TM.
Problem originally reported in #301.
Dynamically configured devices simulate multiple controllers with a single DEVICE structure and can have the number of controllers being simulated set by the user. DLI, DZ, DUP, DMC, TDC, VH, DC are all dynamically configured devices.
DLI and TDC are dynamically configured devices which get static bus addresses.
Vector values contained in device information blocks are the true bus relative vector values. CPU specific biased vector values are produced by the respective vector fetching logic and vector values are limited to 9 bits with <1:0> = 0 as specified in both the Unibus and Qbus documents.
VAX 11/.750 Boot ROM code makes non-longword memory references to MassBus and Unibus register space. Minor changes were necessary to allow this behavior which was architecturally undefined behavior, but had real code which depended on it.
Added a BOOTDEV option to the CPU to reflect the 4 position boot device selection switch on real VAX 11/750 hardware.
The UBA750 initial state started with the UBA map registers validly mapping the first 256KB of RAM to Unibus space.
Added simulated PCS/WCS memory which boot code on some operating systems (Ultrix and other BSD derived systems) automatically loaded on the VAX 11/750. PCS/WCS was also automatically loaded by the newer versions of the BOOT ROMs.
Design Notes for Fixing VAX Unaligned Access to IO and Register Space
Problem Statement: VAX unaligned accesses are handled by reading the
surrounding longword (or longwords) and
a) for reads, extracting the addressed addressed word or longword
b) for writes, inserting the addressed word or longword and then
writing the surrounding longword (or longwords) back
This is correct for all memory cases. On the 11/780, the unaligned
access to register or IO space causes an error, as it should. On
CVAX, it causes incorrect behavior, by either performing too many
QBus references, or performing read-modify-writes instead of pure
writes, or accessing the wrong Qbus locations.
The problem cannot be trivially solved with address manipulation.
The core issues is that on CVAX, unaligned access is done to
exactly as many bytes as are required, using a base longword
address and a byte mask. There are five cases, corresponding to
word and longword lengths, and byte offsets 1, 2 (longword only),
and 3. Further, behavior is different for reads and writes, because
the Qbus always performs word operations on reads, leaving it to
the processor to extract a byte if needed.
Conceptual design: Changes in vax_mmu.c:
Unaligned access is done with two separate physical addresses, pa
and pa1, because if the access crosses a page boundary, pa1 may
not be contiguous with pa. It's worth noting that in an unaligned
access, the low part of the data begins at pa (complete with byte
offset), but the high parts begins at pa1 & ~03 (always in the
low-order end of the second longword).
To handle unaligned data, we will add two routines for read and
write unaligned:
data = ReadU (pa, len);
WriteU (pa, len, val);
Note that the length can be 1, 2, or 3 bytes. For ReadU, data is
return right-aligned and masked. For WriteU, val is expected to
be right-aligned and masked.
The read-unaligned flows are changed as follows:
if (mapen && ((off + lnt) > VA_PAGSIZE)) { /* cross page? */
vpn = VA_GETVPN (va + lnt); /* vpn 2nd page */
tbi = VA_GETTBI (vpn);
xpte = (va & VA_S0)? stlb[tbi]: ptlb[tbi]; /* access tlb */
if (((xpte.pte & acc) == 0) || (xpte.tag != vpn) ||
((acc & TLB_WACC) && ((xpte.pte & TLB_M) == 0)))
xpte = fill (va + lnt, lnt, acc, NULL); /* fill if needed */
pa1 = ((xpte.pte & TLB_PFN) | VA_GETOFF (va + 4)) & ~03;
}
else pa1 = ((pa + 4) & PAMASK) & ~03; /* not cross page */
bo = pa & 3;
if (lnt >= L_LONG) { /* lw unaligned? */
sc = bo << 3;
wl = ReadU (pa, L_LONG - bo); /* read both fragments */
wh = ReadU (pa1, bo); /* extract */
return ((wl | (wh << (32 - sc))) & LMASK);
}
else if (bo == 1) /* read within lw */
return ReadU (pa, L_WORD);
else {
wl = ReadU (pa, L_BYTE); /* word cross lw */
wh = ReadU (pa1, L_BYTE); /* read, extract */
return (wl | (wh << 8));
}
These are not very different, but they do reflect that ReadU returns
right-aligned and properly masked data, rather than the encapsulating
longword.
The write-unaligned flows change rather more drastically:
if (mapen && ((off + lnt) > VA_PAGSIZE)) {
vpn = VA_GETVPN (va + 4);
tbi = VA_GETTBI (vpn);
xpte = (va & VA_S0)? stlb[tbi]: ptlb[tbi]; /* access tlb */
if (((xpte.pte & acc) == 0) || (xpte.tag != vpn) ||
((xpte.pte & TLB_M) == 0))
xpte = fill (va + lnt, lnt, acc, NULL);
pa1 = ((xpte.pte & TLB_PFN) | VA_GETOFF (va + 4)) & ~03;
}
else pa1 = ((pa + 4) & PAMASK) & ~03;
bo = pa & 3;
if (lnt >= L_LONG) {
sc = bo << 3;
WriteU (pa, L_LONG - bo, val & insert[L_LONG - bo]);
WriteU (pa, bo, (val >> (32 - sc)) & insert[bo]);
}
else if (bo == 1) /* read within lw */
WriteU (pa, L_WORD, val & WMASK);
else { /* word cross lw */
WriteU (pa, L_BYTE, val & BMASK);
WriteU (pa, L_BYTE, (val >> 8) & BMASK);
}
return;
}
Note that all the burden here has been thrown on the WriteU routine.
-------------
ReadU is the simpler of the two routines that needs to be written.
It will handle memory reads and defer register and IO space to
model-specific unaligned handlers.
int32 ReadU (uint32 pa, int32 lnt)
{
int32 dat;
int32 sc = (pa & 3) << 3;
if (ADDR_IS_MEM (pa))
dat = M[pa >> 2];
else {
mchk = REF_V;
if (ADDR_IS_IO (pa))
dat = ReadIOU (pa, lnt);
else dat = ReadRegU (pa, lnt);
}
return ((dat >> sc) & insert[lnt]);
}
Note that the ReadIOU and ReadRegU return a "full longword," just
like their aligned counterparts, and ReadU right-aligns the result,
just as ReadB, ReadW, and ReadL do.
WriteU must handle the memory read-modify-write sequence. However,
it defers register and IO space to model-specific unaligned handlers.
void WriteU (uint32 pa, int32 lnt, int32 val)
{
if (ADDR_IS_MEM (pa)) {
int32 bo = pa & 3;
int32 sc = bo << 3;
M[pa >> 2] = (M[pa >> 2] & ~(insert[len] << sc) | (val << sc);
}
else if ADDR_IS_IO (pa)
WriteIOU (pa, lnt, val);
else WriteRegU (pa, lnt, val);
return;
}
--------------
For the 11/780, ReadIOU, ReadRegU, WriteIOU, and WriteRegU all do the
same thing: they throw an SBI machine check. We can write explicit
routines to do this (and remove the unaligned checks from all the
normal adapter flows), or leave things as they are and simply define
the four routines as macros that go to the normal routines. So there's
very little to do.
On CVAX, I suspect that ReadRegU and WriteRegU behave like the
normal routines. The CVAX specs don't say much, but CMCTL (the memory
controller) notes that it ignores the byte mask and treats every
access as an aligned longword access. I suspect this is true for
the other CVAX support chips, but I no longer have chip specs.
The Qbus, on the other hand... that's a fun one. Note that all of
these cases are presented to the existing aligned IO routine:
bo = 0, byte, word, or longword length
bo = 2, word
bo = 1, 2, 3, byte length
All the other cases are going to end up at ReadIOU and WriteIOU,
and they must turn the request into the exactly correct number of
Qbus accesses AND NO MORE, because Qbus reads can have side-effects,
and word read-modify-write is NOT the same as a byte write.
The read cases are:
bo = 0, byte or word - read one word
bo = 1, byte - read one word
bo = 2, byte or word - read one word
bo = 3, byte - read one word
bo = 0, triword - read two words
bo = 1, word or triword - read two words
ReadIOU is very similar to the existing ReadIO:
int32 ReadIOU (uint32 pa, int32 lnt)
{
int32 iod;
iod = ReadQb (pa); /* wd from Qbus */
if ((lnt + (pa & 1)) <= 2) /* byte or word & even */
iod = iod << ((pa & 2)? 16: 0); /* one op */
else iod = (ReadQb (pa + 2) << 16) | iod; /* two ops, get 2nd wd */
SET_IRQL;
return iod;
}
The write cases are:
bo = x, lnt = byte - write one byte
bo = 0 or 2, lnt = word - write one word
bo = 1, lnt = word - write two bytes
bo = 0, lnt = triword - write word, byte
bo = 1, lnt = triword - write byte, word
WriteIOU is similar to the existing WriteIO:
void WriteIO (uint32 pa, int32 val, int32 lnt)
{
switch (lnt) {
case L_BYTE: /* byte */
WriteQb (pa, val & BMASK, WRITEB);
break;
case L_WORD: /* word */
if (pa & 1) { /* odd addr? */
WriteQb (pa, val & BMASK, WRITEB);
WriteQb (pa + 1, (val >> 8) & BMASK, WRITEB);
}
else WriteQb (pa, val, WRITE);
break;
case 3: /* triword */
if (pa & 1) { /* odd addr? */
WriteQb (pa, val & BMASK, WRITEB);
WriteQb (pa + 1, (val >> 8) & WMASK, WRITE);
}
else {
WriteQb (pa, val & WMASK, WRITE);
WriteQb (pa + 2, (val >> 16) & BMASK, WRITEB);
}
break;
}
SET_IRQL;
return;
}
-----------------
I think this handles all the cases.
/Bob Supnik
Conflicts:
VAX/vax780_defs.h
VAX/vax_mmu.c
VAX/vaxmod_defs.h
Show IOSPACE doesn't always get the number of devices right due to device creativity.
o The distinction between UNIT and DEVICE has blurred
o MUX devices merge several physical devices into one device/unit
o Dynamic device sizing has made things more volatile.
This edit solves the problem for SHOW IOSPACE by adding an (optional) word to the DIBs.
The word contains the amount of IO space consumed by each instance of the physical device that's being emulated.
E.G., if it's a DZ11, the device is the DZ11 module, or 8 lines, even though the MUX device may support 32.
This enables SHOW IOSPACE to determine the number of physical devices being emulated, which is what folks need when configuring software. The word may have other uses - in a generic dynamic device sizing routine - which is why the amount of IOSPACE per device was chosen rather than the 'number of physical devices.'
The edit should not make any existing device regress. If the new word (ulnt) is zero (not initialized), SHOW IOSPACE will default to the number of units in the device, or if there's no device (CPUs), 1 as before. If it is present, the number of devices is the calculated as total allocation/allocation-per-device.
The edit updates all the devices that seem to require this treatment, and all the processors that define the UNIBUS/QBUS DIBs.
Fixed auto configure bugs which didn't allow Fixed CSR Addresses or Fixed Vectors to be set using the auto configure information.
Fixed display of address and vectors to indicate that the assigned address and/or vector is in the floating set.
Added extended definitions to the auto configure table to reflect all known potential static and floating and static addresses as of VMS V5.5-2
Changed the name of the VAX 11/780 console floppy device name to RXC from RX (which collides with a Unibus name for the RX11).
pdp11_dmc.c
- Fixed DMA bug which wrote data into the wrong simulated memory address.
- Fixed incoming IP address checking.
pdp11_io_lib.c
- Added the DMC device to the autoconfigure device table
vax780_defs.h
- Added comment for DMC11
The makefile now works for Linux and most Unix's. However, for Solaris
and MacOS, you must first export the OSTYPE environment variable:
> export OSTYPE
> make
Otherwise, you will get build errors.
1. New Features
1.1 3.8-0
1.1.1 SCP and Libraries
- BREAK, NOBREAK, and SHOW BREAK with no argument will set, clear, and
show (respectively) a breakpoint at the current PC.
1.1.2 GRI
- Added support for the GRI-99 processor.
1.1.3 HP2100
- Added support for the BACI terminal interface.
- Added support for RTE OS/VMA/EMA, SIGNAL, VIS firmware extensions.
1.1.4 Nova
- Added support for 64KW memory (implemented in third-party CPU's).
1.1.5 PDP-11
- Added support for DC11, RC11, KE11A, KG11A.
- Added modem control support for DL11.
- Added ASCII character support for all 8b devices.
1.2 3.8-1
1.2.1 SCP and libraries
- Added capability to set line connection order for terminal multiplexers.
1.2.2 HP2100
- Added support for 12620A/12936A privileged interrupt fence.
- Added support for 12792C eight-channel asynchronous multiplexer.
1.3 3.8-2
1.3.1 SCP and libraries
- Added line history capability for *nix hosts.
- Added "SHOW SHOW" and "SHOW <dev> SHOW" commands.
1.3.2 1401
- Added "no rewind" option to magtape boot.
1.3.3 PDP-11
- Added RD32 support to RQ
- Added debug support to RL
1.3.4 PDP-8
- Added FPP support (many thanks to Rick Murphy for debugging the code)
1.3.5 VAX-11/780
- Added AUTORESTART switch support, and VMS REBOOT command support
2. Bugs Fixed
Please see the revision history on http://simh.trailing-edge.com or
in the source module sim_rev.h.
The makefile now works for Linux and most Unix's. Howevr, for Solaris
and MacOS, you must first export the OSTYPE environment variable:
> export OSTYPE
> make
Otherwise, you will get build errors.
1. New Features
1.1 3.8-0
1.1.1 SCP and Libraries
- BREAK, NOBREAK, and SHOW BREAK with no argument will set, clear, and
show (respectively) a breakpoint at the current PC.
1.1.2 GRI
- Added support for the GRI-99 processor.
1.1.3 HP2100
- Added support for the BACI terminal interface.
- Added support for RTE OS/VMA/EMA, SIGNAL, VIS firmware extensions.
1.1.4 Nova
- Added support for 64KW memory (implemented in third-party CPU's).
1.1.5 PDP-11
- Added support for DC11, RC11, KE11A, KG11A.
- Added modem control support for DL11.
- Added ASCII character support for all 8b devices.
1.2 3.8-1
1.2.1 SCP and libraries
- Added capability to set line connection order for terminal multiplexers.
1.2.2 HP2100
- Added support for 12620A/12936A privileged interrupt fence.
- Added support for 12792C eight-channel asynchronous multiplexer.
2. Bugs Fixed
Please see the revision history on http://simh.trailing-edge.com or
in the source module sim_rev.h.
The makefile now works for Linux and most Unix's. Howevr, for Solaris
and MacOS, you must first export the OSTYPE environment variable:
> export OSTYPE
> make
Otherwise, you will get build errors.
1. New Features
1.1 3.8-0
1.1.1 SCP and Libraries
- BREAK, NOBREAK, and SHOW BREAK with no argument will set, clear, and
show (respectively) a breakpoint at the current PC.
1.2 GRI
- Added support for the GRI-99 processor.
1.3 HP2100
- Added support for the BACI terminal interface.
- Added support for RTE OS/VMA/EMA, SIGNAL, VIS firmware extensions.
1.4 Nova
- Added support for 64KW memory (implemented in third-party CPU's).
1.5 PDP-11
- Added support for DC11, RC11, KE11A, KG11A.
- Added modem control support for DL11.
- Added ASCII character support for all 8b devices.
2. Bugs Fixed
Please see the revision history on http://simh.trailing-edge.com or
in the source module sim_rev.h.
1. New Features
1.1 3.7-0
1.1.1 SCP
- Added SET THROTTLE and SET NOTHROTTLE commands to regulate simulator
execution rate and host resource utilization.
- Added idle support (based on work by Mark Pizzolato).
- Added -e to control error processing in nested DO commands (from
Dave Bryan).
1.1.2 HP2100
- Added Double Integer instructions, 1000-F CPU, and Floating Point
Processor (from Dave Bryan).
- Added 2114 and 2115 CPUs, 12607B and 12578A DMA controllers, and
21xx binary loader protection (from Dave Bryan).
1.1.3 Interdata
- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
state.
1.1.4 PDP-11
- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
state (WAIT instruction executed).
- Added TA11/TU60 cassette support.
1.1.5 PDP-8
- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
state (keyboard poll loop or jump-to-self).
- Added TA8E/TU60 cassette support.
1.1.6 PDP-1
- Added support for 16-channel sequence break system.
- Added support for PDP-1D extended features and timesharing clock.
- Added support for Type 630 data communications subsystem.
1.1.6 PDP-4/7/9/15
- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
state (keyboard poll loop or jump-to-self).
1.1.7 VAX, VAX780
- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
state (more than 200 cycles at IPL's 0, 1, or 3 in kernel mode).
1.1.8 PDP-10
- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
state (operating system dependent).
- Added CD20 (CD11) support.
2. Bugs Fixed
Please see the revision history on http://simh.trailing-edge.com or
in the source module sim_rev.h.
1. New Features
1.1 3.7-0
1.1.1 SCP
- Added SET THROTTLE and SET NOTHROTTLE commands to regulate simulator
execution rate and host resource utilization.
- Added idle support (based on work by Mark Pizzolato).
- Added -e to control error processing in nested DO commands (from
Dave Bryan).
1.1.2 HP2100
- Added Double Integer instructions, 1000-F CPU, and Floating Point
Processor (from Dave Bryan).
- Added 2114 and 2115 CPUs, 12607B and 12578A DMA controllers, and
21xx binary loader protection (from Dave Bryan).
1.1.3 Interdata
- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
state.
1.1.4 PDP-11
- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
state (WAIT instruction executed).
- Added TA11/TU60 cassette support.
1.1.5 PDP-8
- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
state (keyboard poll loop or jump-to-self).
- Added TA8E/TU60 cassette support.
1.1.6 PDP-1
- Added support for 16-channel sequence break system.
- Added support for PDP-1D extended features and timesharing clock.
- Added support for Type 630 data communications subsystem.
1.1.6 PDP-4/7/9/15
- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
state (keyboard poll loop or jump-to-self).
1.1.7 VAX, VAX780
- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
state (more than 200 cycles at IPL's 0, 1, or 3 in kernel mode).
1.1.8 PDP-10
- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
state (operating system dependent).
- Added CD20 (CD11) support.
2. Bugs Fixed
Please see the revision history on http://simh.trailing-edge.com or
in the source module sim_rev.h.
The save/restore format has been updated to improve its reliability.
As a result, save files prior to release 3.0 are no longer supported.
The text documentation files are obsolete and are no longer included
with the distribution. Up-to-date PDF documentation files are
available on the SimH web site.
1. New Features
1.1 3.6-0
1.1.1 Most magnetic tapes
- Added support for limiting tape capacity to a particular size in MB
1.1.2 IBM 7090/7094
- First release
1.1.3 VAX-11/780
- Added FLOAD command, loads system file from console floppy disk
1.1.4 VAX, VAX-11/780, and PDP-11
- Added card reader support (from John Dundas)
1.1.5 PDP-11
- Added instruction history
2. Bugs Fixed
Please see the revision history on http://simh.trailing-edge.com or
in the source module sim_rev.h.
The source set has been extensively overhauled. For correct
viewing, set Visual C++ or Emacs to have tab stops every 4
characters.
1. New Features
1.1 3.5-0
1.1.1 All Ethernet devices
- Added Windows user-defined adapter names (from Timothe Litt)
1.1.2 Interdata, SDS, HP, PDP-8, PDP-18b terminal multiplexors
- Added support for SET <unit>n DISCONNECT
1.1.3 VAX
- Added latent QDSS support
- Revised autoconfigure to handle QDSS
1.1.4 PDP-11
- Revised autoconfigure to handle more cases
1.2 3.5-1
No new features
1.3 3.5-2
1.3.1 All ASCII terminals
- Most ASCII terminal emulators have supported 7-bit and 8-bit
operation; where required, they have also supported an upper-
case only or KSR-emulation mode. This release adds a new mode,
7P, for 7-bit printing characters. In 7P mode, non-printing
characters in the range 0-31 (decimal), and 127 (decimal), are
automatically suppressed. This prevents printing of fill
characters under Windows.
The printable character set for ASCII code values 0-31 can be
changed with the SET CONSOLE PCHAR command. Code value 127
(DELETE) is always suppressed.
1.3.2 VAX-11/780
- First release. The VAX-11/780 has successfully run VMS V7.2. The
commercial instructions and compatability mode have not been
extensively tested. The Ethernet controller is not working yet
and is disabled.
2. Bugs Fixed
2.1 3.5-0
2.1.1 SCP and libraries
- Trim trailing spaces on all input (for example, attach file names)
- Fixed sim_sock spurious SIGPIPE error in Unix/Linux
- Fixed sim_tape misallocation of TPC map array for 64b simulators
2.1.2 1401
- Fixed bug, CPU reset was clearing SSB through SSG
2.1.3 PDP-11
- Fixed bug in VH vector display routine
- Fixed XU runt packet processing (found by Tim Chapman)
2.1.4 Interdata
- Fixed bug in SHOW PAS CONN/STATS
- Fixed potential integer overflow exception in divide
2.1.5 SDS
- Fixed bug in SHOW MUX CONN/STATS
2.1.6 HP
- Fixed bug in SHOW MUX CONN/STATS
2.1.7 PDP-8
- Fixed bug in SHOW TTIX CONN/STATS
- Fixed bug in SET/SHOW TTOXn LOG
2.1.8 PDP-18b
- Fixed bug in SHOW TTIX CONN/STATS
- Fixed bug in SET/SHOW TTOXn LOG
2.1.9 Nova, Eclipse
- Fixed potential integer overflow exception in divide
2.2 3.5-1
2.2.1 1401
- Changed character encodings to be compatible with Pierce 709X simulator
- Added mode for old/new character encodings
2.2.2 1620
- Changed character encodings to be compatible with Pierce 709X simulator
2.2.3 PDP-10
- Changed MOVNI to eliminate GCC warning
2.2.4 VAX
- Fixed bug in structure definitions with 32b compilation options
- Fixed bug in autoconfiguration table
2.2.5 PDP-11
- Fixed bug in autoconfiguration table
2.3 3.5-2
2.3.1 PDP-10
- RP: fixed drive clear not to clear disk address
2.3.2 PDP-11 (VAX, VAX-11/780, for shared peripherals)
- HK: fixed overlap seek interaction with drive select, drive clear, etc
- RQ, TM, TQ, TS, TU: widened address display to 64b when USE_ADDR64 option selected
- TU: changed default adapter from TM02 to TM03 (required by VMS)
- RP: fixed drive clear not to clear disk address
- RP, TU: fixed device enable/disable to enabled/disable Massbus adapter as well
- XQ: fixed register access alignment bug (found by Doug Carman)
2.3.3 PDP-8
- RL: fixed IOT 61 decoding bug (found by David Gesswein)
- DF, DT, RF: fixed register access alignment bug (found by Doug Carman)
2.3.4 VAX
- Fixed CVTfi to trap on integer overflow if PSW<iv> is set
- Fixed breakpoint detection when USE_ADDR64 option selected
The memory layout for the Interdata simulators has been changed.
Do not use Interdata SAVE files from prior revisions with V3.4.
1. New Features in 3.4
1.1 SCP and Libraries
- Revised interpretation of fprint_sym, fparse_sym returns
- Revised syntax for SET DEBUG
- DO command nesting allowed to ten levels
1.2 Interdata
- Revised memory model to be 16b instead of 8b
1.3 HP2100
- Added Fast FORTRAN Processor instructions
- Added SET OFFLINE/ONLINE and SET UNLOAD/LOAD commands to tapes and disks
2. Bugs Fixed in 3.4-0
2.1 Interdata
- Fixed bug in show history routine (from Mark Hittinger)
- Fixed bug in initial memory allocation
2.2 PDP-10
- Fixed TU bug, ERASE and WREOF should not clear done (reported by
Rich Alderson)
- Fixed TU error reporting
2.3 PDP-11
- Fixed TU error reporting
