Changing the CPU type or MEMORY size/configuration causes memory
resources mapped by other devices to be removed. This is not made
clear by "HELP CPU" and the user has no feedback that this is
happening.
This PR does the following:
1) HELP SET CPU shows that SET CPU MEMORY requires a value.
2) Feedback is provided if the value is omitted or not properly formatted.
3) Unmapped memory resources caused by a SET CPU command are displayed
on the SIMH console.
4) Adds a SET CPU RESIZEMEMORY command that resizes system memory
without unmapping other device memory resources.
The MEM dump command would not display past SET CPU xK memory
size. This prevented displaying ROMs or other RAM windows when
a lower amount of memory was specified. This PR changes MEM to
always display a minimum of a 64K regardless of main RAM size.
Adds 6850 DCD status latch to M2SIO devices.
Adds vector interrupt support to M2SIO devices.
Removes CTS inactive transmit disable from PMMI device.
Adds IMSAI-style programmed output to CPU/SIO devices.
SET CPU PO will display "PO: AREG" upon an "OUT 0FFH"
instruction.
SET CPU NOPO will disable the function (default).
Corrects problem with Mode 0 interrupts.
When the CPU receives an interrupt, it pushes the current
program counter on the stack. The current implementation
of Mode 0 was performing interrupt processing after fetching
the next opcode from RAM, which also increases the PC by 1.
This caused PC+1 to be pushed on the stack. The interrupt
processing is now done prior to fetching the next opcode,
preserving the correct program counter.
After adding the sim_clock_precalibrate_commands, the PC was not zero
at the sim> prompt after loading altairz80.
Set CPU_S to zero in cpu_reset to address this issue.
Used to initialize SCP timers to prevent problems during simulator startup
when THROTTLE is being used.
/*
* This sequence of instructions is a mix that mimics
* a resonable instruction set that is a close estimate
* to the calibrated result.
*/
static const char *cpu_clock_precalibrate_commands[] = {
"-m 100 LXI H,200H",
"-m 103 MVI B,0",
"-m 105 DCR B",
"-m 106 MOV M,B",
"-m 107 INX H",
"-m 108 JNZ 0105H",
"-m 10B JMP 0100H",
"PC 100",
NULL};
The AB Digital Design B810 RAM card is a 256K Dynamic RAM card
with onboard refresh logic. AltairZ80 support emulates four of
these cards for a total of 16 banks.
As used for the OASIS operating system, the B810 is configured
with common memory at the low addresses (0000h-3FFFh) with 16
banks of 48K from 4000h-FFFFh.
In order to have the common memory appear from 0000-3FFFh, set
the COMMONLOW register to 1:
D COMMONLOW 1
No address value are changed, by a pointer the the array object is
explicitly provided which allows validation logic to determine the
size of the array object rather than merely it's first element.
These changes facilitate more robust parameter type checking and helps
to identify unexpected coding errors.
Most simulators can now also be compiled with a C++ compiler without
warnings.
Additionally, these changes have also been configured to facilitate easier
backporting of simulator and device simulation modules to run under the
simh v3.9+ SCP framework.
